423aa5e130
gcc 6.2 and 6.4 fails to compile lib/librte_ipsec/sa.c
with the following errors:
lib/librte_ipsec/sa.c:
In function inline_outb_tun_pkt_process:
x86_64-native-linuxapp-gcc/include/rte_memcpy.h:337:2:
error: array subscript is above array bounds [-Werror=array-bounds]
rte_mov32((uint8_t *)dst + 1 * 32, (const uint8_t *)src + 1 * 32);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
...
It complains about the following lines of code:
esp_outb_tun_pkt_prepare(struct rte_ipsec_sa *sa, rte_be64_t
....
/* update spi, seqn and iv */
esph = (struct esp_hdr *)(ph + sa->hdr_len);
iv = (uint64_t *)(esph + 1);
rte_memcpy(iv, ivp, sa->iv_len);
While I believe it is a false positive,
it is too excessive to use rte_memcpy() here,
as IV length could be only 0/8/16 bytes.
So introduce small helper function to copy IV and use it
instead of rte_memcpy().
Fixes: 4d7ea3e1459b ("ipsec: implement SA data-path API")
Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
149 lines
3.0 KiB
C
149 lines
3.0 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2018 Intel Corporation
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*/
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#ifndef _CRYPTO_H_
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#define _CRYPTO_H_
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/**
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* @file crypto.h
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* Contains crypto specific functions/structures/macros used internally
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* by ipsec library.
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*/
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/*
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* AES-GCM devices have some specific requirements for IV and AAD formats.
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* Ideally that to be done by the driver itself.
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*/
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struct aead_gcm_iv {
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uint32_t salt;
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uint64_t iv;
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uint32_t cnt;
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} __attribute__((packed));
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struct aead_gcm_aad {
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uint32_t spi;
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/*
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* RFC 4106, section 5:
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* Two formats of the AAD are defined:
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* one for 32-bit sequence numbers, and one for 64-bit ESN.
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*/
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union {
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uint32_t u32[2];
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uint64_t u64;
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} sqn;
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uint32_t align0; /* align to 16B boundary */
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} __attribute__((packed));
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struct gcm_esph_iv {
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struct esp_hdr esph;
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uint64_t iv;
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} __attribute__((packed));
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static inline void
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aead_gcm_iv_fill(struct aead_gcm_iv *gcm, uint64_t iv, uint32_t salt)
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{
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gcm->salt = salt;
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gcm->iv = iv;
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gcm->cnt = rte_cpu_to_be_32(1);
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}
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/*
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* RFC 4106, 5 AAD Construction
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* spi and sqn should already be converted into network byte order.
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* Make sure that not used bytes are zeroed.
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*/
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static inline void
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aead_gcm_aad_fill(struct aead_gcm_aad *aad, rte_be32_t spi, rte_be64_t sqn,
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int esn)
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{
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aad->spi = spi;
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if (esn)
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aad->sqn.u64 = sqn;
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else {
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aad->sqn.u32[0] = sqn_low32(sqn);
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aad->sqn.u32[1] = 0;
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}
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aad->align0 = 0;
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}
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static inline void
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gen_iv(uint64_t iv[IPSEC_MAX_IV_QWORD], rte_be64_t sqn)
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{
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iv[0] = sqn;
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iv[1] = 0;
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}
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/*
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* Helper routine to copy IV
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* Righ now we support only algorithms with IV length equals 0/8/16 bytes.
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*/
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static inline void
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copy_iv(uint64_t dst[IPSEC_MAX_IV_QWORD],
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const uint64_t src[IPSEC_MAX_IV_QWORD], uint32_t len)
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{
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RTE_BUILD_BUG_ON(IPSEC_MAX_IV_SIZE != 2 * sizeof(uint64_t));
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switch (len) {
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case IPSEC_MAX_IV_SIZE:
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dst[1] = src[1];
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/* fallthrough */
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case sizeof(uint64_t):
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dst[0] = src[0];
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/* fallthrough */
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case 0:
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break;
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default:
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/* should never happen */
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RTE_ASSERT(NULL);
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}
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}
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/*
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* from RFC 4303 3.3.2.1.4:
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* If the ESN option is enabled for the SA, the high-order 32
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* bits of the sequence number are appended after the Next Header field
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* for purposes of this computation, but are not transmitted.
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*/
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/*
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* Helper function that moves ICV by 4B below, and inserts SQN.hibits.
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* icv parameter points to the new start of ICV.
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*/
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static inline void
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insert_sqh(uint32_t sqh, void *picv, uint32_t icv_len)
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{
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uint32_t *icv;
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int32_t i;
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RTE_ASSERT(icv_len % sizeof(uint32_t) == 0);
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icv = picv;
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icv_len = icv_len / sizeof(uint32_t);
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for (i = icv_len; i-- != 0; icv[i] = icv[i - 1])
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;
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icv[i] = sqh;
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}
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/*
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* Helper function that moves ICV by 4B up, and removes SQN.hibits.
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* icv parameter points to the new start of ICV.
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*/
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static inline void
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remove_sqh(void *picv, uint32_t icv_len)
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{
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uint32_t i, *icv;
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RTE_ASSERT(icv_len % sizeof(uint32_t) == 0);
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icv = picv;
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icv_len = icv_len / sizeof(uint32_t);
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for (i = 0; i != icv_len; i++)
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icv[i] = icv[i + 1];
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}
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#endif /* _CRYPTO_H_ */
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