6c7f491e7f
In this commit we generalize the movement of user-specified meta data between mbufs and FPGA AXIS tuser fields using user-defined hook functions. - Previous use of PMD dynfields are removed - Remove emptied rte_pmd_ark.h - Hook function added to ark_user_ext - Add hook function calls in Rx and Tx paths - Update guide with example of hook function use Signed-off-by: Ed Czeck <ed.czeck@atomicrules.com>
166 lines
4.5 KiB
C
166 lines
4.5 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright (c) 2015-2018 Atomic Rules LLC
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*/
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#ifndef _ARK_UDM_H_
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#define _ARK_UDM_H_
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#include <stdint.h>
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#include <rte_memory.h>
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/* The UDM or Upstream Data Mover is an internal Arkville hardware
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* module for moving packet from the RX packet streams to host memory.
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* This module is *not* intended for end-user manipulation, hence
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* there is minimal documentation.
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*/
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/* Meta data structure passed from FPGA, must match layout in FPGA
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* -- 32 bytes
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*/
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struct ark_rx_meta {
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uint32_t user_meta[5]; /* user defined based on fpga code */
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uint8_t reserved[10];
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uint16_t pkt_len;
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} __rte_packed;
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/*
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* UDM hardware structures
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* These are overlay structures to a memory mapped FPGA device. These
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* structs will never be instantiated in ram memory
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*/
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#define ARK_RX_WRITE_TIME_NS 2500
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#define ARK_UDM_SETUP 0
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#define ARK_UDM_CONST2 0xbACECACE
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#define ARK_UDM_CONST3 0x334d4455
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#define ARK_UDM_CONST ARK_UDM_CONST3
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struct ark_udm_setup_t {
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uint32_t r0;
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uint32_t r4;
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volatile uint32_t cycle_count;
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uint32_t const0;
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};
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#define ARK_UDM_CFG 0x010
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struct ark_udm_cfg_t {
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volatile uint32_t stop_flushed; /* RO */
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volatile uint32_t command;
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uint32_t dataroom;
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uint32_t headroom;
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};
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typedef enum {
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ARK_UDM_START = 0x1,
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ARK_UDM_STOP = 0x2,
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ARK_UDM_RESET = 0x3
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} ark_udm_commands;
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#define ARK_UDM_STATS 0x020
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struct ark_udm_stats_t {
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volatile uint64_t rx_byte_count;
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volatile uint64_t rx_packet_count;
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volatile uint64_t rx_mbuf_count;
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volatile uint64_t rx_sent_packets;
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};
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#define ARK_UDM_PQ 0x040
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struct ark_udm_queue_stats_t {
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volatile uint64_t q_byte_count;
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volatile uint64_t q_packet_count; /* includes drops */
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volatile uint64_t q_mbuf_count;
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volatile uint64_t q_ff_packet_count;
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volatile uint64_t q_pkt_drop;
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uint32_t q_enable;
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};
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#define ARK_UDM_TLP 0x0070
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struct ark_udm_tlp_t {
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volatile uint64_t pkt_drop; /* global */
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volatile uint32_t tlp_q1;
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volatile uint32_t tlp_q2;
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volatile uint32_t tlp_q3;
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volatile uint32_t tlp_q4;
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volatile uint32_t tlp_full;
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};
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#define ARK_UDM_PCIBP 0x00a0
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struct ark_udm_pcibp_t {
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volatile uint32_t pci_clear;
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volatile uint32_t pci_empty;
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volatile uint32_t pci_q1;
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volatile uint32_t pci_q2;
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volatile uint32_t pci_q3;
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volatile uint32_t pci_q4;
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volatile uint32_t pci_full;
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};
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#define ARK_UDM_TLP_PS 0x00bc
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struct ark_udm_tlp_ps_t {
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volatile uint32_t tlp_clear;
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volatile uint32_t tlp_ps_min;
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volatile uint32_t tlp_ps_max;
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volatile uint32_t tlp_full_ps_min;
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volatile uint32_t tlp_full_ps_max;
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volatile uint32_t tlp_dw_ps_min;
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volatile uint32_t tlp_dw_ps_max;
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volatile uint32_t tlp_pldw_ps_min;
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volatile uint32_t tlp_pldw_ps_max;
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};
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#define ARK_UDM_RT_CFG 0x00e0
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struct ark_udm_rt_cfg_t {
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rte_iova_t hw_prod_addr;
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uint32_t write_interval; /* 4ns cycles */
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volatile uint32_t prod_idx; /* RO */
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};
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/* Consolidated structure */
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#define ARK_UDM_EXPECT_SIZE (0x00fc + 4)
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#define ARK_UDM_QOFFSET ARK_UDM_EXPECT_SIZE
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struct ark_udm_t {
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struct ark_udm_setup_t setup;
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struct ark_udm_cfg_t cfg;
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struct ark_udm_stats_t stats;
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struct ark_udm_queue_stats_t qstats;
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uint8_t reserved1[(ARK_UDM_TLP - ARK_UDM_PQ) -
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sizeof(struct ark_udm_queue_stats_t)];
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struct ark_udm_tlp_t tlp;
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uint8_t reserved2[(ARK_UDM_PCIBP - ARK_UDM_TLP) -
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sizeof(struct ark_udm_tlp_t)];
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struct ark_udm_pcibp_t pcibp;
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struct ark_udm_tlp_ps_t tlp_ps;
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struct ark_udm_rt_cfg_t rt_cfg;
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int8_t reserved3[(ARK_UDM_EXPECT_SIZE - ARK_UDM_RT_CFG) -
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sizeof(struct ark_udm_rt_cfg_t)];
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};
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int ark_udm_verify(struct ark_udm_t *udm);
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int ark_udm_stop(struct ark_udm_t *udm, int wait);
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void ark_udm_start(struct ark_udm_t *udm);
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int ark_udm_reset(struct ark_udm_t *udm);
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void ark_udm_configure(struct ark_udm_t *udm,
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uint32_t headroom,
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uint32_t dataroom,
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uint32_t write_interval_ns);
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void ark_udm_write_addr(struct ark_udm_t *udm, rte_iova_t addr);
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void ark_udm_stats_reset(struct ark_udm_t *udm);
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void ark_udm_dump_stats(struct ark_udm_t *udm, const char *msg);
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void ark_udm_dump_queue_stats(struct ark_udm_t *udm, const char *msg,
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uint16_t qid);
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void ark_udm_dump(struct ark_udm_t *udm, const char *msg);
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void ark_udm_dump_perf(struct ark_udm_t *udm, const char *msg);
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void ark_udm_dump_setup(struct ark_udm_t *udm, uint16_t q_id);
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int ark_udm_is_flushed(struct ark_udm_t *udm);
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/* Per queue data */
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uint64_t ark_udm_dropped(struct ark_udm_t *udm);
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uint64_t ark_udm_bytes(struct ark_udm_t *udm);
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uint64_t ark_udm_packets(struct ark_udm_t *udm);
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void ark_udm_queue_stats_reset(struct ark_udm_t *udm);
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void ark_udm_queue_enable(struct ark_udm_t *udm, int enable);
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#endif
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