ffd0ec015b
This patch optimizes the Rx performance by adding the rx_free_thresh related process in the '.rx_pkt_burst' ops implementation function named hns3_recv_pkts. The related change as follows: 1. Adding the rx_free_thresh related process to reduce the number of writing the HNS3_RING_RX_HEAD_REG register. 2. Adjusting the internal macro named DEFAULT_RX_FREE_THRESH to 32 and adjusting HNS3_MIN_RING_DESC to 64 to make the effect of the thresh more obvious. Signed-off-by: Chengwen Feng <fengchengwen@huawei.com> Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com>
328 lines
8.6 KiB
C
328 lines
8.6 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2018-2019 Hisilicon Limited.
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*/
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#ifndef _HNS3_RXTX_H_
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#define _HNS3_RXTX_H_
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#define HNS3_MIN_RING_DESC 64
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#define HNS3_MAX_RING_DESC 32768
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#define HNS3_DEFAULT_RING_DESC 1024
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#define HNS3_ALIGN_RING_DESC 32
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#define HNS3_RING_BASE_ALIGN 128
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#define HNS3_BD_SIZE_512_TYPE 0
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#define HNS3_BD_SIZE_1024_TYPE 1
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#define HNS3_BD_SIZE_2048_TYPE 2
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#define HNS3_BD_SIZE_4096_TYPE 3
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#define HNS3_RX_FLAG_VLAN_PRESENT 0x1
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#define HNS3_RX_FLAG_L3ID_IPV4 0x0
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#define HNS3_RX_FLAG_L3ID_IPV6 0x1
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#define HNS3_RX_FLAG_L4ID_UDP 0x0
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#define HNS3_RX_FLAG_L4ID_TCP 0x1
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#define HNS3_RXD_DMAC_S 0
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#define HNS3_RXD_DMAC_M (0x3 << HNS3_RXD_DMAC_S)
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#define HNS3_RXD_VLAN_S 2
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#define HNS3_RXD_VLAN_M (0x3 << HNS3_RXD_VLAN_S)
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#define HNS3_RXD_L3ID_S 4
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#define HNS3_RXD_L3ID_M (0xf << HNS3_RXD_L3ID_S)
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#define HNS3_RXD_L4ID_S 8
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#define HNS3_RXD_L4ID_M (0xf << HNS3_RXD_L4ID_S)
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#define HNS3_RXD_FRAG_B 12
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#define HNS3_RXD_STRP_TAGP_S 13
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#define HNS3_RXD_STRP_TAGP_M (0x3 << HNS3_RXD_STRP_TAGP_S)
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#define HNS3_RXD_L2E_B 16
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#define HNS3_RXD_L3E_B 17
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#define HNS3_RXD_L4E_B 18
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#define HNS3_RXD_TRUNCAT_B 19
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#define HNS3_RXD_HOI_B 20
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#define HNS3_RXD_DOI_B 21
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#define HNS3_RXD_OL3E_B 22
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#define HNS3_RXD_OL4E_B 23
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#define HNS3_RXD_GRO_COUNT_S 24
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#define HNS3_RXD_GRO_COUNT_M (0x3f << HNS3_RXD_GRO_COUNT_S)
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#define HNS3_RXD_GRO_FIXID_B 30
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#define HNS3_RXD_GRO_ECN_B 31
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#define HNS3_RXD_ODMAC_S 0
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#define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S)
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#define HNS3_RXD_OVLAN_S 2
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#define HNS3_RXD_OVLAN_M (0x3 << HNS3_RXD_OVLAN_S)
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#define HNS3_RXD_OL3ID_S 4
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#define HNS3_RXD_OL3ID_M (0xf << HNS3_RXD_OL3ID_S)
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#define HNS3_RXD_OL4ID_S 8
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#define HNS3_RXD_OL4ID_M (0xf << HNS3_RXD_OL4ID_S)
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#define HNS3_RXD_FBHI_S 12
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#define HNS3_RXD_FBHI_M (0x3 << HNS3_RXD_FBHI_S)
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#define HNS3_RXD_FBLI_S 14
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#define HNS3_RXD_FBLI_M (0x3 << HNS3_RXD_FBLI_S)
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#define HNS3_RXD_BDTYPE_S 0
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#define HNS3_RXD_BDTYPE_M (0xf << HNS3_RXD_BDTYPE_S)
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#define HNS3_RXD_VLD_B 4
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#define HNS3_RXD_UDP0_B 5
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#define HNS3_RXD_EXTEND_B 7
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#define HNS3_RXD_FE_B 8
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#define HNS3_RXD_LUM_B 9
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#define HNS3_RXD_CRCP_B 10
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#define HNS3_RXD_L3L4P_B 11
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#define HNS3_RXD_TSIND_S 12
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#define HNS3_RXD_TSIND_M (0x7 << HNS3_RXD_TSIND_S)
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#define HNS3_RXD_LKBK_B 15
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#define HNS3_RXD_GRO_SIZE_S 16
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#define HNS3_RXD_GRO_SIZE_M (0x3ff << HNS3_RXD_GRO_SIZE_S)
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#define HNS3_TXD_L3T_S 0
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#define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S)
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#define HNS3_TXD_L4T_S 2
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#define HNS3_TXD_L4T_M (0x3 << HNS3_TXD_L4T_S)
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#define HNS3_TXD_L3CS_B 4
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#define HNS3_TXD_L4CS_B 5
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#define HNS3_TXD_VLAN_B 6
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#define HNS3_TXD_TSO_B 7
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#define HNS3_TXD_L2LEN_S 8
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#define HNS3_TXD_L2LEN_M (0xff << HNS3_TXD_L2LEN_S)
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#define HNS3_TXD_L3LEN_S 16
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#define HNS3_TXD_L3LEN_M (0xff << HNS3_TXD_L3LEN_S)
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#define HNS3_TXD_L4LEN_S 24
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#define HNS3_TXD_L4LEN_M (0xffUL << HNS3_TXD_L4LEN_S)
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#define HNS3_TXD_OL3T_S 0
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#define HNS3_TXD_OL3T_M (0x3 << HNS3_TXD_OL3T_S)
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#define HNS3_TXD_OVLAN_B 2
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#define HNS3_TXD_MACSEC_B 3
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#define HNS3_TXD_TUNTYPE_S 4
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#define HNS3_TXD_TUNTYPE_M (0xf << HNS3_TXD_TUNTYPE_S)
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#define HNS3_TXD_BDTYPE_S 0
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#define HNS3_TXD_BDTYPE_M (0xf << HNS3_TXD_BDTYPE_S)
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#define HNS3_TXD_FE_B 4
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#define HNS3_TXD_SC_S 5
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#define HNS3_TXD_SC_M (0x3 << HNS3_TXD_SC_S)
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#define HNS3_TXD_EXTEND_B 7
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#define HNS3_TXD_VLD_B 8
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#define HNS3_TXD_RI_B 9
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#define HNS3_TXD_RA_B 10
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#define HNS3_TXD_TSYN_B 11
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#define HNS3_TXD_DECTTL_S 12
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#define HNS3_TXD_DECTTL_M (0xf << HNS3_TXD_DECTTL_S)
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#define HNS3_TXD_MSS_S 0
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#define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S)
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#define HNS3_L2_LEN_UNIT 1UL
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#define HNS3_L3_LEN_UNIT 2UL
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#define HNS3_L4_LEN_UNIT 2UL
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enum hns3_pkt_l2t_type {
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HNS3_L2_TYPE_UNICAST,
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HNS3_L2_TYPE_MULTICAST,
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HNS3_L2_TYPE_BROADCAST,
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HNS3_L2_TYPE_INVALID,
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};
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enum hns3_pkt_l3t_type {
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HNS3_L3T_NONE,
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HNS3_L3T_IPV6,
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HNS3_L3T_IPV4,
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HNS3_L3T_RESERVED
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};
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enum hns3_pkt_l4t_type {
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HNS3_L4T_UNKNOWN,
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HNS3_L4T_TCP,
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HNS3_L4T_UDP,
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HNS3_L4T_SCTP
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};
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enum hns3_pkt_ol3t_type {
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HNS3_OL3T_NONE,
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HNS3_OL3T_IPV6,
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HNS3_OL3T_IPV4_NO_CSUM,
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HNS3_OL3T_IPV4_CSUM
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};
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enum hns3_pkt_tun_type {
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HNS3_TUN_NONE,
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HNS3_TUN_MAC_IN_UDP,
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HNS3_TUN_NVGRE,
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HNS3_TUN_OTHER
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};
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/* hardware spec ring buffer format */
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struct hns3_desc {
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union {
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uint64_t addr;
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struct {
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uint32_t addr0;
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uint32_t addr1;
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};
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};
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union {
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struct {
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uint16_t vlan_tag;
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uint16_t send_size;
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union {
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/*
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* L3T | L4T | L3CS | L4CS | VLAN | TSO |
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* L2_LEN
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*/
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uint32_t type_cs_vlan_tso_len;
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struct {
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uint8_t type_cs_vlan_tso;
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uint8_t l2_len;
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uint8_t l3_len;
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uint8_t l4_len;
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};
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};
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uint16_t outer_vlan_tag;
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uint16_t tv;
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union {
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/* OL3T | OVALAN | MACSEC */
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uint32_t ol_type_vlan_len_msec;
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struct {
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uint8_t ol_type_vlan_msec;
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uint8_t ol2_len;
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uint8_t ol3_len;
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uint8_t ol4_len;
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};
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};
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uint32_t paylen;
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uint16_t tp_fe_sc_vld_ra_ri;
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uint16_t mss;
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} tx;
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struct {
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uint32_t l234_info;
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uint16_t pkt_len;
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uint16_t size;
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uint32_t rss_hash;
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uint16_t fd_id;
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uint16_t vlan_tag;
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union {
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uint32_t ol_info;
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struct {
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uint16_t o_dm_vlan_id_fb;
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uint16_t ot_vlan_tag;
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};
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};
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uint32_t bd_base_info;
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} rx;
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};
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} __rte_packed;
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struct hns3_entry {
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struct rte_mbuf *mbuf;
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};
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struct hns3_rx_queue {
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void *io_base;
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struct hns3_adapter *hns;
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struct rte_mempool *mb_pool;
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struct hns3_desc *rx_ring;
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uint64_t rx_ring_phys_addr; /* RX ring DMA address */
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const struct rte_memzone *mz;
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struct hns3_entry *sw_ring;
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struct rte_mbuf *pkt_first_seg;
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struct rte_mbuf *pkt_last_seg;
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uint16_t queue_id;
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uint16_t port_id;
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uint16_t nb_rx_desc;
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uint16_t nb_rx_hold;
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uint16_t rx_tail;
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uint16_t next_to_clean;
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uint16_t next_to_use;
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uint16_t rx_buf_len;
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uint16_t rx_free_thresh;
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bool rx_deferred_start; /* don't start this queue in dev start */
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bool configured; /* indicate if rx queue has been configured */
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uint64_t l2_errors;
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uint64_t pkt_len_errors;
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uint64_t l3_csum_erros;
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uint64_t l4_csum_erros;
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uint64_t ol3_csum_erros;
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uint64_t ol4_csum_erros;
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};
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struct hns3_tx_queue {
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void *io_base;
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struct hns3_adapter *hns;
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struct hns3_desc *tx_ring;
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uint64_t tx_ring_phys_addr; /* TX ring DMA address */
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const struct rte_memzone *mz;
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struct hns3_entry *sw_ring;
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uint16_t queue_id;
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uint16_t port_id;
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uint16_t nb_tx_desc;
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uint16_t next_to_clean;
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uint16_t next_to_use;
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uint16_t tx_bd_ready;
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bool tx_deferred_start; /* don't start this queue in dev start */
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bool configured; /* indicate if tx queue has been configured */
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};
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struct hns3_queue_info {
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const char *type; /* point to queue memory name */
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const char *ring_name; /* point to hardware ring name */
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uint16_t idx;
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uint16_t nb_desc;
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unsigned int socket_id;
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};
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#define HNS3_TX_CKSUM_OFFLOAD_MASK ( \
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PKT_TX_OUTER_IPV6 | \
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PKT_TX_OUTER_IPV4 | \
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PKT_TX_OUTER_IP_CKSUM | \
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PKT_TX_IPV6 | \
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PKT_TX_IPV4 | \
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PKT_TX_IP_CKSUM | \
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PKT_TX_L4_MASK | \
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PKT_TX_TUNNEL_MASK)
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enum hns3_cksum_status {
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HNS3_CKSUM_NONE = 0,
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HNS3_L3_CKSUM_ERR = 1,
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HNS3_L4_CKSUM_ERR = 2,
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HNS3_OUTER_L3_CKSUM_ERR = 4,
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HNS3_OUTER_L4_CKSUM_ERR = 8
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};
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void hns3_dev_rx_queue_release(void *queue);
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void hns3_dev_tx_queue_release(void *queue);
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void hns3_free_all_queues(struct rte_eth_dev *dev);
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int hns3_reset_all_queues(struct hns3_adapter *hns);
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int hns3_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
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int hns3_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
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int hns3_start_queues(struct hns3_adapter *hns, bool reset_queue);
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int hns3_stop_queues(struct hns3_adapter *hns, bool reset_queue);
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void hns3_dev_release_mbufs(struct hns3_adapter *hns);
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int hns3_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
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unsigned int socket, const struct rte_eth_rxconf *conf,
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struct rte_mempool *mp);
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int hns3_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
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unsigned int socket, const struct rte_eth_txconf *conf);
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uint16_t hns3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts);
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uint16_t hns3_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
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uint16_t nb_pkts);
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uint16_t hns3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
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uint16_t nb_pkts);
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const uint32_t *hns3_dev_supported_ptypes_get(struct rte_eth_dev *dev);
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void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev);
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void hns3_tqp_intr_enable(struct hns3_hw *hw, uint16_t tpq_int_num, bool en);
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int hns3_set_fake_rx_or_tx_queues(struct rte_eth_dev *dev, uint16_t nb_rx_q,
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uint16_t nb_tx_q);
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#endif /* _HNS3_RXTX_H_ */
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