2015-09-21 15:52:41 +00:00
|
|
|
/*-
|
|
|
|
* BSD LICENSE
|
|
|
|
*
|
2016-01-26 17:47:22 +00:00
|
|
|
* Copyright (c) Intel Corporation.
|
2015-09-21 15:52:41 +00:00
|
|
|
* All rights reserved.
|
|
|
|
*
|
|
|
|
* Redistribution and use in source and binary forms, with or without
|
|
|
|
* modification, are permitted provided that the following conditions
|
|
|
|
* are met:
|
|
|
|
*
|
|
|
|
* * Redistributions of source code must retain the above copyright
|
|
|
|
* notice, this list of conditions and the following disclaimer.
|
|
|
|
* * Redistributions in binary form must reproduce the above copyright
|
|
|
|
* notice, this list of conditions and the following disclaimer in
|
|
|
|
* the documentation and/or other materials provided with the
|
|
|
|
* distribution.
|
|
|
|
* * Neither the name of Intel Corporation nor the names of its
|
|
|
|
* contributors may be used to endorse or promote products derived
|
|
|
|
* from this software without specific prior written permission.
|
|
|
|
*
|
|
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
|
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
|
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
|
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
|
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
|
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
|
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
|
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
|
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
|
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
|
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
|
|
*/
|
|
|
|
|
2016-04-29 18:04:33 +00:00
|
|
|
/**
|
|
|
|
* \file
|
|
|
|
* NVMe specification definitions
|
|
|
|
*/
|
|
|
|
|
2015-09-21 15:52:41 +00:00
|
|
|
#ifndef SPDK_NVME_SPEC_H
|
|
|
|
#define SPDK_NVME_SPEC_H
|
|
|
|
|
2016-02-12 14:52:35 +00:00
|
|
|
#ifdef __cplusplus
|
|
|
|
extern "C" {
|
|
|
|
#endif
|
|
|
|
|
2015-09-21 15:52:41 +00:00
|
|
|
#include <stdint.h>
|
|
|
|
#include <stddef.h>
|
|
|
|
|
2016-01-08 21:37:12 +00:00
|
|
|
#include "spdk/assert.h"
|
|
|
|
|
2015-09-21 15:52:41 +00:00
|
|
|
/**
|
|
|
|
* Use to mark a command to apply to all namespaces, or to retrieve global
|
|
|
|
* log pages.
|
|
|
|
*/
|
2016-02-09 18:06:48 +00:00
|
|
|
#define SPDK_NVME_GLOBAL_NS_TAG ((uint32_t)0xFFFFFFFF)
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-03-23 23:30:38 +00:00
|
|
|
#define SPDK_NVME_MAX_IO_QUEUES (65535)
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-05-03 21:54:25 +00:00
|
|
|
#define SPDK_NVME_ADMIN_QUEUE_MIN_ENTRIES 2
|
|
|
|
#define SPDK_NVME_ADMIN_QUEUE_MAX_ENTRIES 4096
|
|
|
|
|
|
|
|
#define SPDK_NVME_IO_QUEUE_MIN_ENTRIES 2
|
|
|
|
#define SPDK_NVME_IO_QUEUE_MAX_ENTRIES 65536
|
|
|
|
|
2015-12-24 02:34:38 +00:00
|
|
|
/**
|
|
|
|
* Indicates the maximum number of range sets that may be specified
|
|
|
|
* in the dataset mangement command.
|
|
|
|
*/
|
2016-02-09 18:06:48 +00:00
|
|
|
#define SPDK_NVME_DATASET_MANAGEMENT_MAX_RANGES 256
|
2015-12-24 02:34:38 +00:00
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
union spdk_nvme_cap_lo_register {
|
2015-09-21 15:52:41 +00:00
|
|
|
uint32_t raw;
|
|
|
|
struct {
|
|
|
|
/** maximum queue entries supported */
|
|
|
|
uint32_t mqes : 16;
|
|
|
|
|
|
|
|
/** contiguous queues required */
|
|
|
|
uint32_t cqr : 1;
|
|
|
|
|
|
|
|
/** arbitration mechanism supported */
|
|
|
|
uint32_t ams : 2;
|
|
|
|
|
|
|
|
uint32_t reserved1 : 5;
|
|
|
|
|
|
|
|
/** timeout */
|
|
|
|
uint32_t to : 8;
|
|
|
|
} bits;
|
|
|
|
};
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_STATIC_ASSERT(sizeof(union spdk_nvme_cap_lo_register) == 4, "Incorrect size");
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
union spdk_nvme_cap_hi_register {
|
2015-09-21 15:52:41 +00:00
|
|
|
uint32_t raw;
|
|
|
|
struct {
|
|
|
|
/** doorbell stride */
|
|
|
|
uint32_t dstrd : 4;
|
|
|
|
|
|
|
|
uint32_t reserved3 : 1;
|
|
|
|
|
|
|
|
/** command sets supported */
|
|
|
|
uint32_t css_nvm : 1;
|
|
|
|
|
|
|
|
uint32_t css_reserved : 3;
|
|
|
|
uint32_t reserved2 : 7;
|
|
|
|
|
|
|
|
/** memory page size minimum */
|
|
|
|
uint32_t mpsmin : 4;
|
|
|
|
|
|
|
|
/** memory page size maximum */
|
|
|
|
uint32_t mpsmax : 4;
|
|
|
|
|
|
|
|
uint32_t reserved1 : 8;
|
|
|
|
} bits;
|
|
|
|
};
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_STATIC_ASSERT(sizeof(union spdk_nvme_cap_hi_register) == 4, "Incorrect size");
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
union spdk_nvme_cc_register {
|
2015-09-21 15:52:41 +00:00
|
|
|
uint32_t raw;
|
|
|
|
struct {
|
|
|
|
/** enable */
|
|
|
|
uint32_t en : 1;
|
|
|
|
|
|
|
|
uint32_t reserved1 : 3;
|
|
|
|
|
|
|
|
/** i/o command set selected */
|
|
|
|
uint32_t css : 3;
|
|
|
|
|
|
|
|
/** memory page size */
|
|
|
|
uint32_t mps : 4;
|
|
|
|
|
|
|
|
/** arbitration mechanism selected */
|
|
|
|
uint32_t ams : 3;
|
|
|
|
|
|
|
|
/** shutdown notification */
|
|
|
|
uint32_t shn : 2;
|
|
|
|
|
|
|
|
/** i/o submission queue entry size */
|
|
|
|
uint32_t iosqes : 4;
|
|
|
|
|
|
|
|
/** i/o completion queue entry size */
|
|
|
|
uint32_t iocqes : 4;
|
|
|
|
|
|
|
|
uint32_t reserved2 : 8;
|
|
|
|
} bits;
|
|
|
|
};
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_STATIC_ASSERT(sizeof(union spdk_nvme_cc_register) == 4, "Incorrect size");
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
enum spdk_nvme_shn_value {
|
|
|
|
SPDK_NVME_SHN_NORMAL = 0x1,
|
|
|
|
SPDK_NVME_SHN_ABRUPT = 0x2,
|
2015-09-21 15:52:41 +00:00
|
|
|
};
|
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
union spdk_nvme_csts_register {
|
2015-09-21 15:52:41 +00:00
|
|
|
uint32_t raw;
|
|
|
|
struct {
|
|
|
|
/** ready */
|
|
|
|
uint32_t rdy : 1;
|
|
|
|
|
|
|
|
/** controller fatal status */
|
|
|
|
uint32_t cfs : 1;
|
|
|
|
|
|
|
|
/** shutdown status */
|
|
|
|
uint32_t shst : 2;
|
|
|
|
|
|
|
|
uint32_t reserved1 : 28;
|
|
|
|
} bits;
|
|
|
|
};
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_STATIC_ASSERT(sizeof(union spdk_nvme_csts_register) == 4, "Incorrect size");
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
enum spdk_nvme_shst_value {
|
|
|
|
SPDK_NVME_SHST_NORMAL = 0x0,
|
|
|
|
SPDK_NVME_SHST_OCCURRING = 0x1,
|
|
|
|
SPDK_NVME_SHST_COMPLETE = 0x2,
|
2015-09-21 15:52:41 +00:00
|
|
|
};
|
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
union spdk_nvme_aqa_register {
|
2015-09-21 15:52:41 +00:00
|
|
|
uint32_t raw;
|
|
|
|
struct {
|
|
|
|
/** admin submission queue size */
|
|
|
|
uint32_t asqs : 12;
|
|
|
|
|
|
|
|
uint32_t reserved1 : 4;
|
|
|
|
|
|
|
|
/** admin completion queue size */
|
|
|
|
uint32_t acqs : 12;
|
|
|
|
|
|
|
|
uint32_t reserved2 : 4;
|
|
|
|
} bits;
|
|
|
|
};
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_STATIC_ASSERT(sizeof(union spdk_nvme_aqa_register) == 4, "Incorrect size");
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-02-16 06:55:28 +00:00
|
|
|
union spdk_nvme_vs_register {
|
|
|
|
uint32_t raw;
|
|
|
|
struct {
|
|
|
|
uint32_t reserved1 : 8;
|
|
|
|
/** indicates the minor version */
|
|
|
|
uint32_t mnr : 8;
|
|
|
|
/** indicates the major version */
|
|
|
|
uint32_t mjr : 16;
|
|
|
|
} bits;
|
|
|
|
};
|
|
|
|
SPDK_STATIC_ASSERT(sizeof(union spdk_nvme_vs_register) == 4, "Incorrect size");
|
|
|
|
|
|
|
|
union spdk_nvme_cmbloc_register {
|
|
|
|
uint32_t raw;
|
|
|
|
struct {
|
|
|
|
/** indicator of BAR which contains controller memory buffer(CMB) */
|
|
|
|
uint32_t bir : 3;
|
|
|
|
uint32_t reserved1 : 9;
|
|
|
|
/** offset of CMB in multiples of the size unit */
|
|
|
|
uint32_t ofst : 20;
|
|
|
|
} bits;
|
|
|
|
};
|
|
|
|
SPDK_STATIC_ASSERT(sizeof(union spdk_nvme_cmbloc_register) == 4, "Incorrect size");
|
|
|
|
|
|
|
|
union spdk_nvme_cmbsz_register {
|
|
|
|
uint32_t raw;
|
|
|
|
struct {
|
|
|
|
/** support submission queues in CMB */
|
|
|
|
uint32_t sqs : 1;
|
|
|
|
/** support completion queues in CMB */
|
|
|
|
uint32_t cqs : 1;
|
|
|
|
/** support PRP and SGLs lists in CMB */
|
|
|
|
uint32_t lists : 1;
|
|
|
|
/** support read data and metadata in CMB */
|
|
|
|
uint32_t rds : 1;
|
|
|
|
/** support write data and metadata in CMB */
|
|
|
|
uint32_t wds : 1;
|
|
|
|
uint32_t reserved1 : 3;
|
|
|
|
/** indicates the granularity of the size unit */
|
|
|
|
uint32_t szu : 4;
|
|
|
|
/** size of CMB in multiples of the size unit */
|
|
|
|
uint32_t sz : 20;
|
|
|
|
} bits;
|
|
|
|
};
|
|
|
|
SPDK_STATIC_ASSERT(sizeof(union spdk_nvme_cmbsz_register) == 4, "Incorrect size");
|
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
struct spdk_nvme_registers {
|
2015-09-21 15:52:41 +00:00
|
|
|
/** controller capabilities */
|
2016-02-09 18:06:48 +00:00
|
|
|
union spdk_nvme_cap_lo_register cap_lo;
|
|
|
|
union spdk_nvme_cap_hi_register cap_hi;
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-02-16 06:55:28 +00:00
|
|
|
/** version of NVMe specification */
|
|
|
|
union spdk_nvme_vs_register vs;
|
2015-09-21 15:52:41 +00:00
|
|
|
uint32_t intms; /* interrupt mask set */
|
|
|
|
uint32_t intmc; /* interrupt mask clear */
|
|
|
|
|
|
|
|
/** controller configuration */
|
2016-02-09 18:06:48 +00:00
|
|
|
union spdk_nvme_cc_register cc;
|
2015-09-21 15:52:41 +00:00
|
|
|
|
|
|
|
uint32_t reserved1;
|
2016-03-01 23:28:29 +00:00
|
|
|
union spdk_nvme_csts_register csts; /* controller status */
|
2015-09-21 15:52:41 +00:00
|
|
|
uint32_t nssr; /* NVM subsystem reset */
|
|
|
|
|
|
|
|
/** admin queue attributes */
|
2016-02-09 18:06:48 +00:00
|
|
|
union spdk_nvme_aqa_register aqa;
|
2015-09-21 15:52:41 +00:00
|
|
|
|
|
|
|
uint64_t asq; /* admin submission queue base addr */
|
|
|
|
uint64_t acq; /* admin completion queue base addr */
|
2016-02-16 06:55:28 +00:00
|
|
|
/** controller memory buffer location */
|
|
|
|
union spdk_nvme_cmbloc_register cmbloc;
|
|
|
|
/** controller memory buffer size */
|
|
|
|
union spdk_nvme_cmbsz_register cmbsz;
|
|
|
|
uint32_t reserved3[0x3f0];
|
2015-09-21 15:52:41 +00:00
|
|
|
|
|
|
|
struct {
|
|
|
|
uint32_t sq_tdbl; /* submission queue tail doorbell */
|
|
|
|
uint32_t cq_hdbl; /* completion queue head doorbell */
|
|
|
|
} doorbell[1];
|
|
|
|
};
|
|
|
|
|
|
|
|
/* NVMe controller register space offsets */
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_STATIC_ASSERT(0x00 == offsetof(struct spdk_nvme_registers, cap_lo),
|
|
|
|
"Incorrect register offset");
|
|
|
|
SPDK_STATIC_ASSERT(0x08 == offsetof(struct spdk_nvme_registers, vs), "Incorrect register offset");
|
|
|
|
SPDK_STATIC_ASSERT(0x0C == offsetof(struct spdk_nvme_registers, intms),
|
|
|
|
"Incorrect register offset");
|
|
|
|
SPDK_STATIC_ASSERT(0x10 == offsetof(struct spdk_nvme_registers, intmc),
|
|
|
|
"Incorrect register offset");
|
|
|
|
SPDK_STATIC_ASSERT(0x14 == offsetof(struct spdk_nvme_registers, cc), "Incorrect register offset");
|
|
|
|
SPDK_STATIC_ASSERT(0x1C == offsetof(struct spdk_nvme_registers, csts), "Incorrect register offset");
|
|
|
|
SPDK_STATIC_ASSERT(0x20 == offsetof(struct spdk_nvme_registers, nssr), "Incorrect register offset");
|
|
|
|
SPDK_STATIC_ASSERT(0x24 == offsetof(struct spdk_nvme_registers, aqa), "Incorrect register offset");
|
|
|
|
SPDK_STATIC_ASSERT(0x28 == offsetof(struct spdk_nvme_registers, asq), "Incorrect register offset");
|
|
|
|
SPDK_STATIC_ASSERT(0x30 == offsetof(struct spdk_nvme_registers, acq), "Incorrect register offset");
|
2016-02-16 06:55:28 +00:00
|
|
|
SPDK_STATIC_ASSERT(0x38 == offsetof(struct spdk_nvme_registers, cmbloc),
|
|
|
|
"Incorrect register offset");
|
|
|
|
SPDK_STATIC_ASSERT(0x3C == offsetof(struct spdk_nvme_registers, cmbsz),
|
|
|
|
"Incorrect register offset");
|
2016-02-09 18:06:48 +00:00
|
|
|
|
|
|
|
enum spdk_nvme_sgl_descriptor_type {
|
|
|
|
SPDK_NVME_SGL_TYPE_DATA_BLOCK = 0x0,
|
|
|
|
SPDK_NVME_SGL_TYPE_BIT_BUCKET = 0x1,
|
|
|
|
SPDK_NVME_SGL_TYPE_SEGMENT = 0x2,
|
|
|
|
SPDK_NVME_SGL_TYPE_LAST_SEGMENT = 0x3,
|
2015-09-21 15:52:41 +00:00
|
|
|
/* 0x4 - 0xe reserved */
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_NVME_SGL_TYPE_VENDOR_SPECIFIC = 0xf
|
2015-09-21 15:52:41 +00:00
|
|
|
};
|
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
struct __attribute__((packed)) spdk_nvme_sgl_descriptor {
|
2015-09-21 15:52:41 +00:00
|
|
|
uint64_t address;
|
|
|
|
uint32_t length;
|
|
|
|
uint8_t reserved[3];
|
|
|
|
|
2016-03-28 15:50:49 +00:00
|
|
|
/** SGL descriptor type specific */
|
|
|
|
uint8_t type_specific : 4;
|
|
|
|
|
2015-09-21 15:52:41 +00:00
|
|
|
/** SGL descriptor type */
|
|
|
|
uint8_t type : 4;
|
|
|
|
|
|
|
|
};
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_STATIC_ASSERT(sizeof(struct spdk_nvme_sgl_descriptor) == 16, "Incorrect size");
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
enum spdk_nvme_psdt_value {
|
|
|
|
SPDK_NVME_PSDT_PRP = 0x0,
|
|
|
|
SPDK_NVME_PSDT_SGL_MPTR_CONTIG = 0x1,
|
|
|
|
SPDK_NVME_PSDT_SGL_MPTR_SGL = 0x2,
|
|
|
|
SPDK_NVME_PSDT_RESERVED = 0x3
|
2015-09-21 15:52:41 +00:00
|
|
|
};
|
|
|
|
|
2016-02-29 22:22:18 +00:00
|
|
|
/**
|
|
|
|
* Submission queue priority values for Create I/O Submission Queue Command.
|
|
|
|
*
|
|
|
|
* Only valid for weighted round robin arbitration method.
|
|
|
|
*/
|
|
|
|
enum spdk_nvme_qprio {
|
|
|
|
SPDK_NVME_QPRIO_URGENT = 0x0,
|
|
|
|
SPDK_NVME_QPRIO_HIGH = 0x1,
|
|
|
|
SPDK_NVME_QPRIO_MEDIUM = 0x2,
|
|
|
|
SPDK_NVME_QPRIO_LOW = 0x3
|
|
|
|
};
|
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
struct spdk_nvme_cmd {
|
2015-09-21 15:52:41 +00:00
|
|
|
/* dword 0 */
|
|
|
|
uint16_t opc : 8; /* opcode */
|
|
|
|
uint16_t fuse : 2; /* fused operation */
|
|
|
|
uint16_t rsvd1 : 4;
|
|
|
|
uint16_t psdt : 2;
|
|
|
|
uint16_t cid; /* command identifier */
|
|
|
|
|
|
|
|
/* dword 1 */
|
|
|
|
uint32_t nsid; /* namespace identifier */
|
|
|
|
|
|
|
|
/* dword 2-3 */
|
|
|
|
uint32_t rsvd2;
|
|
|
|
uint32_t rsvd3;
|
|
|
|
|
|
|
|
/* dword 4-5 */
|
|
|
|
uint64_t mptr; /* metadata pointer */
|
|
|
|
|
|
|
|
/* dword 6-9: data pointer */
|
|
|
|
union {
|
|
|
|
struct {
|
|
|
|
uint64_t prp1; /* prp entry 1 */
|
|
|
|
uint64_t prp2; /* prp entry 2 */
|
|
|
|
} prp;
|
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
struct spdk_nvme_sgl_descriptor sgl1;
|
2015-09-21 15:52:41 +00:00
|
|
|
} dptr;
|
|
|
|
|
|
|
|
/* dword 10-15 */
|
|
|
|
uint32_t cdw10; /* command-specific */
|
|
|
|
uint32_t cdw11; /* command-specific */
|
|
|
|
uint32_t cdw12; /* command-specific */
|
|
|
|
uint32_t cdw13; /* command-specific */
|
|
|
|
uint32_t cdw14; /* command-specific */
|
|
|
|
uint32_t cdw15; /* command-specific */
|
|
|
|
};
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_STATIC_ASSERT(sizeof(struct spdk_nvme_cmd) == 64, "Incorrect size");
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
struct spdk_nvme_status {
|
2015-09-21 15:52:41 +00:00
|
|
|
uint16_t p : 1; /* phase tag */
|
|
|
|
uint16_t sc : 8; /* status code */
|
|
|
|
uint16_t sct : 3; /* status code type */
|
|
|
|
uint16_t rsvd2 : 2;
|
|
|
|
uint16_t m : 1; /* more */
|
|
|
|
uint16_t dnr : 1; /* do not retry */
|
|
|
|
};
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_STATIC_ASSERT(sizeof(struct spdk_nvme_status) == 2, "Incorrect size");
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
/**
|
|
|
|
* Completion queue entry
|
|
|
|
*/
|
|
|
|
struct spdk_nvme_cpl {
|
2015-09-21 15:52:41 +00:00
|
|
|
/* dword 0 */
|
|
|
|
uint32_t cdw0; /* command-specific */
|
|
|
|
|
|
|
|
/* dword 1 */
|
|
|
|
uint32_t rsvd1;
|
|
|
|
|
|
|
|
/* dword 2 */
|
|
|
|
uint16_t sqhd; /* submission queue head pointer */
|
|
|
|
uint16_t sqid; /* submission queue identifier */
|
|
|
|
|
|
|
|
/* dword 3 */
|
|
|
|
uint16_t cid; /* command identifier */
|
2016-02-09 18:06:48 +00:00
|
|
|
struct spdk_nvme_status status;
|
2015-09-21 15:52:41 +00:00
|
|
|
};
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_STATIC_ASSERT(sizeof(struct spdk_nvme_cpl) == 16, "Incorrect size");
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
/**
|
|
|
|
* Dataset Management range
|
|
|
|
*/
|
|
|
|
struct spdk_nvme_dsm_range {
|
2015-09-21 15:52:41 +00:00
|
|
|
uint32_t attributes;
|
|
|
|
uint32_t length;
|
|
|
|
uint64_t starting_lba;
|
|
|
|
};
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_STATIC_ASSERT(sizeof(struct spdk_nvme_dsm_range) == 16, "Incorrect size");
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
/**
|
|
|
|
* Status code types
|
|
|
|
*/
|
|
|
|
enum spdk_nvme_status_code_type {
|
|
|
|
SPDK_NVME_SCT_GENERIC = 0x0,
|
|
|
|
SPDK_NVME_SCT_COMMAND_SPECIFIC = 0x1,
|
|
|
|
SPDK_NVME_SCT_MEDIA_ERROR = 0x2,
|
2015-09-21 15:52:41 +00:00
|
|
|
/* 0x3-0x6 - reserved */
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_NVME_SCT_VENDOR_SPECIFIC = 0x7,
|
2015-09-21 15:52:41 +00:00
|
|
|
};
|
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
/**
|
|
|
|
* Generic command status codes
|
|
|
|
*/
|
|
|
|
enum spdk_nvme_generic_command_status_code {
|
|
|
|
SPDK_NVME_SC_SUCCESS = 0x00,
|
|
|
|
SPDK_NVME_SC_INVALID_OPCODE = 0x01,
|
|
|
|
SPDK_NVME_SC_INVALID_FIELD = 0x02,
|
|
|
|
SPDK_NVME_SC_COMMAND_ID_CONFLICT = 0x03,
|
|
|
|
SPDK_NVME_SC_DATA_TRANSFER_ERROR = 0x04,
|
|
|
|
SPDK_NVME_SC_ABORTED_POWER_LOSS = 0x05,
|
|
|
|
SPDK_NVME_SC_INTERNAL_DEVICE_ERROR = 0x06,
|
|
|
|
SPDK_NVME_SC_ABORTED_BY_REQUEST = 0x07,
|
|
|
|
SPDK_NVME_SC_ABORTED_SQ_DELETION = 0x08,
|
|
|
|
SPDK_NVME_SC_ABORTED_FAILED_FUSED = 0x09,
|
|
|
|
SPDK_NVME_SC_ABORTED_MISSING_FUSED = 0x0a,
|
|
|
|
SPDK_NVME_SC_INVALID_NAMESPACE_OR_FORMAT = 0x0b,
|
|
|
|
SPDK_NVME_SC_COMMAND_SEQUENCE_ERROR = 0x0c,
|
|
|
|
|
|
|
|
SPDK_NVME_SC_LBA_OUT_OF_RANGE = 0x80,
|
|
|
|
SPDK_NVME_SC_CAPACITY_EXCEEDED = 0x81,
|
|
|
|
SPDK_NVME_SC_NAMESPACE_NOT_READY = 0x82,
|
2015-09-21 15:52:41 +00:00
|
|
|
};
|
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
/**
|
|
|
|
* Command specific status codes
|
|
|
|
*/
|
|
|
|
enum spdk_nvme_command_specific_status_code {
|
|
|
|
SPDK_NVME_SC_COMPLETION_QUEUE_INVALID = 0x00,
|
|
|
|
SPDK_NVME_SC_INVALID_QUEUE_IDENTIFIER = 0x01,
|
|
|
|
SPDK_NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED = 0x02,
|
|
|
|
SPDK_NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED = 0x03,
|
2015-09-21 15:52:41 +00:00
|
|
|
/* 0x04 - reserved */
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED = 0x05,
|
|
|
|
SPDK_NVME_SC_INVALID_FIRMWARE_SLOT = 0x06,
|
|
|
|
SPDK_NVME_SC_INVALID_FIRMWARE_IMAGE = 0x07,
|
|
|
|
SPDK_NVME_SC_INVALID_INTERRUPT_VECTOR = 0x08,
|
|
|
|
SPDK_NVME_SC_INVALID_LOG_PAGE = 0x09,
|
|
|
|
SPDK_NVME_SC_INVALID_FORMAT = 0x0a,
|
|
|
|
SPDK_NVME_SC_FIRMWARE_REQUIRES_RESET = 0x0b,
|
|
|
|
|
|
|
|
SPDK_NVME_SC_CONFLICTING_ATTRIBUTES = 0x80,
|
|
|
|
SPDK_NVME_SC_INVALID_PROTECTION_INFO = 0x81,
|
|
|
|
SPDK_NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE = 0x82,
|
2015-09-21 15:52:41 +00:00
|
|
|
};
|
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
/**
|
|
|
|
* Media error status codes
|
|
|
|
*/
|
|
|
|
enum spdk_nvme_media_error_status_code {
|
|
|
|
SPDK_NVME_SC_WRITE_FAULTS = 0x80,
|
|
|
|
SPDK_NVME_SC_UNRECOVERED_READ_ERROR = 0x81,
|
|
|
|
SPDK_NVME_SC_GUARD_CHECK_ERROR = 0x82,
|
|
|
|
SPDK_NVME_SC_APPLICATION_TAG_CHECK_ERROR = 0x83,
|
|
|
|
SPDK_NVME_SC_REFERENCE_TAG_CHECK_ERROR = 0x84,
|
|
|
|
SPDK_NVME_SC_COMPARE_FAILURE = 0x85,
|
|
|
|
SPDK_NVME_SC_ACCESS_DENIED = 0x86,
|
2015-09-21 15:52:41 +00:00
|
|
|
};
|
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
/**
|
|
|
|
* Admin opcodes
|
|
|
|
*/
|
|
|
|
enum spdk_nvme_admin_opcode {
|
|
|
|
SPDK_NVME_OPC_DELETE_IO_SQ = 0x00,
|
|
|
|
SPDK_NVME_OPC_CREATE_IO_SQ = 0x01,
|
|
|
|
SPDK_NVME_OPC_GET_LOG_PAGE = 0x02,
|
2015-09-21 15:52:41 +00:00
|
|
|
/* 0x03 - reserved */
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_NVME_OPC_DELETE_IO_CQ = 0x04,
|
|
|
|
SPDK_NVME_OPC_CREATE_IO_CQ = 0x05,
|
|
|
|
SPDK_NVME_OPC_IDENTIFY = 0x06,
|
2015-09-21 15:52:41 +00:00
|
|
|
/* 0x07 - reserved */
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_NVME_OPC_ABORT = 0x08,
|
|
|
|
SPDK_NVME_OPC_SET_FEATURES = 0x09,
|
|
|
|
SPDK_NVME_OPC_GET_FEATURES = 0x0a,
|
2015-09-21 15:52:41 +00:00
|
|
|
/* 0x0b - reserved */
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_NVME_OPC_ASYNC_EVENT_REQUEST = 0x0c,
|
|
|
|
SPDK_NVME_OPC_NS_MANAGEMENT = 0x0d,
|
2015-09-21 15:52:41 +00:00
|
|
|
/* 0x0e-0x0f - reserved */
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_NVME_OPC_FIRMWARE_COMMIT = 0x10,
|
|
|
|
SPDK_NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD = 0x11,
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_NVME_OPC_NS_ATTACHMENT = 0x15,
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_NVME_OPC_FORMAT_NVM = 0x80,
|
|
|
|
SPDK_NVME_OPC_SECURITY_SEND = 0x81,
|
|
|
|
SPDK_NVME_OPC_SECURITY_RECEIVE = 0x82,
|
2015-09-21 15:52:41 +00:00
|
|
|
};
|
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
/**
|
|
|
|
* NVM command set opcodes
|
|
|
|
*/
|
|
|
|
enum spdk_nvme_nvm_opcode {
|
|
|
|
SPDK_NVME_OPC_FLUSH = 0x00,
|
|
|
|
SPDK_NVME_OPC_WRITE = 0x01,
|
|
|
|
SPDK_NVME_OPC_READ = 0x02,
|
2015-09-21 15:52:41 +00:00
|
|
|
/* 0x03 - reserved */
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_NVME_OPC_WRITE_UNCORRECTABLE = 0x04,
|
|
|
|
SPDK_NVME_OPC_COMPARE = 0x05,
|
2015-09-21 15:52:41 +00:00
|
|
|
/* 0x06-0x07 - reserved */
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_NVME_OPC_WRITE_ZEROES = 0x08,
|
|
|
|
SPDK_NVME_OPC_DATASET_MANAGEMENT = 0x09,
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_NVME_OPC_RESERVATION_REGISTER = 0x0d,
|
|
|
|
SPDK_NVME_OPC_RESERVATION_REPORT = 0x0e,
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_NVME_OPC_RESERVATION_ACQUIRE = 0x11,
|
|
|
|
SPDK_NVME_OPC_RESERVATION_RELEASE = 0x15,
|
2015-09-21 15:52:41 +00:00
|
|
|
};
|
|
|
|
|
2016-05-27 15:39:45 +00:00
|
|
|
/**
|
|
|
|
* Data transfer (bits 1:0) of an NVMe opcode.
|
|
|
|
*
|
|
|
|
* \sa spdk_nvme_opc_get_data_transfer
|
|
|
|
*/
|
|
|
|
enum spdk_nvme_data_transfer {
|
|
|
|
/** Opcode does not transfer data */
|
|
|
|
SPDK_NVME_DATA_NONE = 0,
|
|
|
|
/** Opcode transfers data from host to controller (e.g. Write) */
|
|
|
|
SPDK_NVME_DATA_HOST_TO_CONTROLLER = 1,
|
|
|
|
/** Opcode transfers data from controller to host (e.g. Read) */
|
|
|
|
SPDK_NVME_DATA_CONTROLLER_TO_HOST = 2,
|
|
|
|
/** Opcode transfers data both directions */
|
|
|
|
SPDK_NVME_DATA_BIDIRECTIONAL = 3
|
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Extract the Data Transfer bits from an NVMe opcode.
|
|
|
|
*
|
|
|
|
* This determines whether a command requires a data buffer and
|
|
|
|
* which direction (host to controller or controller to host) it is
|
|
|
|
* transferred.
|
|
|
|
*/
|
|
|
|
static inline enum spdk_nvme_data_transfer spdk_nvme_opc_get_data_transfer(uint8_t opc)
|
|
|
|
{
|
|
|
|
return opc & 3;
|
|
|
|
}
|
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
enum spdk_nvme_feat {
|
2015-09-21 15:52:41 +00:00
|
|
|
/* 0x00 - reserved */
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_NVME_FEAT_ARBITRATION = 0x01,
|
|
|
|
SPDK_NVME_FEAT_POWER_MANAGEMENT = 0x02,
|
|
|
|
SPDK_NVME_FEAT_LBA_RANGE_TYPE = 0x03,
|
|
|
|
SPDK_NVME_FEAT_TEMPERATURE_THRESHOLD = 0x04,
|
|
|
|
SPDK_NVME_FEAT_ERROR_RECOVERY = 0x05,
|
|
|
|
SPDK_NVME_FEAT_VOLATILE_WRITE_CACHE = 0x06,
|
|
|
|
SPDK_NVME_FEAT_NUMBER_OF_QUEUES = 0x07,
|
|
|
|
SPDK_NVME_FEAT_INTERRUPT_COALESCING = 0x08,
|
|
|
|
SPDK_NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION = 0x09,
|
|
|
|
SPDK_NVME_FEAT_WRITE_ATOMICITY = 0x0A,
|
|
|
|
SPDK_NVME_FEAT_ASYNC_EVENT_CONFIGURATION = 0x0B,
|
|
|
|
SPDK_NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION = 0x0C,
|
|
|
|
SPDK_NVME_FEAT_HOST_MEM_BUFFER = 0x0D,
|
2015-09-21 15:52:41 +00:00
|
|
|
/* 0x0C-0x7F - reserved */
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_NVME_FEAT_SOFTWARE_PROGRESS_MARKER = 0x80,
|
2016-01-22 08:39:55 +00:00
|
|
|
/* 0x81-0xBF - command set specific */
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_NVME_FEAT_HOST_IDENTIFIER = 0x81,
|
|
|
|
SPDK_NVME_FEAT_HOST_RESERVE_MASK = 0x82,
|
|
|
|
SPDK_NVME_FEAT_HOST_RESERVE_PERSIST = 0x83,
|
2015-09-21 15:52:41 +00:00
|
|
|
/* 0xC0-0xFF - vendor specific */
|
|
|
|
};
|
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
enum spdk_nvme_dsm_attribute {
|
|
|
|
SPDK_NVME_DSM_ATTR_INTEGRAL_READ = 0x1,
|
|
|
|
SPDK_NVME_DSM_ATTR_INTEGRAL_WRITE = 0x2,
|
|
|
|
SPDK_NVME_DSM_ATTR_DEALLOCATE = 0x4,
|
2015-09-21 15:52:41 +00:00
|
|
|
};
|
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
struct spdk_nvme_power_state {
|
2015-09-21 15:52:41 +00:00
|
|
|
uint16_t mp; /* bits 15:00: maximum power */
|
|
|
|
|
|
|
|
uint8_t reserved1;
|
|
|
|
|
|
|
|
uint8_t mps : 1; /* bit 24: max power scale */
|
|
|
|
uint8_t nops : 1; /* bit 25: non-operational state */
|
|
|
|
uint8_t reserved2 : 6;
|
|
|
|
|
|
|
|
uint32_t enlat; /* bits 63:32: entry latency in microseconds */
|
|
|
|
uint32_t exlat; /* bits 95:64: exit latency in microseconds */
|
|
|
|
|
|
|
|
uint8_t rrt : 5; /* bits 100:96: relative read throughput */
|
|
|
|
uint8_t reserved3 : 3;
|
|
|
|
|
|
|
|
uint8_t rrl : 5; /* bits 108:104: relative read latency */
|
|
|
|
uint8_t reserved4 : 3;
|
|
|
|
|
|
|
|
uint8_t rwt : 5; /* bits 116:112: relative write throughput */
|
|
|
|
uint8_t reserved5 : 3;
|
|
|
|
|
|
|
|
uint8_t rwl : 5; /* bits 124:120: relative write latency */
|
|
|
|
uint8_t reserved6 : 3;
|
|
|
|
|
|
|
|
uint8_t reserved7[16];
|
|
|
|
};
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_STATIC_ASSERT(sizeof(struct spdk_nvme_power_state) == 32, "Incorrect size");
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
struct __attribute__((packed)) spdk_nvme_ctrlr_data {
|
2015-09-21 15:52:41 +00:00
|
|
|
/* bytes 0-255: controller capabilities and features */
|
|
|
|
|
|
|
|
/** pci vendor id */
|
|
|
|
uint16_t vid;
|
|
|
|
|
|
|
|
/** pci subsystem vendor id */
|
|
|
|
uint16_t ssvid;
|
|
|
|
|
|
|
|
/** serial number */
|
|
|
|
int8_t sn[20];
|
|
|
|
|
|
|
|
/** model number */
|
|
|
|
int8_t mn[40];
|
|
|
|
|
|
|
|
/** firmware revision */
|
|
|
|
uint8_t fr[8];
|
|
|
|
|
|
|
|
/** recommended arbitration burst */
|
|
|
|
uint8_t rab;
|
|
|
|
|
|
|
|
/** ieee oui identifier */
|
|
|
|
uint8_t ieee[3];
|
|
|
|
|
|
|
|
/** multi-interface capabilities */
|
|
|
|
uint8_t mic;
|
|
|
|
|
|
|
|
/** maximum data transfer size */
|
|
|
|
uint8_t mdts;
|
|
|
|
|
|
|
|
/** controller id */
|
|
|
|
uint16_t cntlid;
|
|
|
|
|
|
|
|
/** version */
|
|
|
|
uint32_t ver;
|
|
|
|
|
|
|
|
/** RTD3 resume latency */
|
|
|
|
uint32_t rtd3r;
|
|
|
|
|
|
|
|
/** RTD3 entry latency */
|
|
|
|
uint32_t rtd3e;
|
|
|
|
|
|
|
|
/** optional asynchronous events supported */
|
|
|
|
uint32_t oaes;
|
|
|
|
|
|
|
|
uint8_t reserved1[160];
|
|
|
|
|
|
|
|
/* bytes 256-511: admin command set attributes */
|
|
|
|
|
|
|
|
/** optional admin command support */
|
|
|
|
struct {
|
|
|
|
/* supports security send/receive commands */
|
|
|
|
uint16_t security : 1;
|
|
|
|
|
|
|
|
/* supports format nvm command */
|
|
|
|
uint16_t format : 1;
|
|
|
|
|
|
|
|
/* supports firmware activate/download commands */
|
|
|
|
uint16_t firmware : 1;
|
|
|
|
|
2016-02-25 03:44:44 +00:00
|
|
|
/* supports ns manage/ns attach commands */
|
|
|
|
uint16_t ns_manage : 1;
|
|
|
|
|
|
|
|
uint16_t oacs_rsvd : 12;
|
2015-09-21 15:52:41 +00:00
|
|
|
} oacs;
|
|
|
|
|
|
|
|
/** abort command limit */
|
|
|
|
uint8_t acl;
|
|
|
|
|
|
|
|
/** asynchronous event request limit */
|
|
|
|
uint8_t aerl;
|
|
|
|
|
|
|
|
/** firmware updates */
|
|
|
|
struct {
|
|
|
|
/* first slot is read-only */
|
|
|
|
uint8_t slot1_ro : 1;
|
|
|
|
|
|
|
|
/* number of firmware slots */
|
|
|
|
uint8_t num_slots : 3;
|
|
|
|
|
2016-05-03 05:18:39 +00:00
|
|
|
/* support activation without reset */
|
|
|
|
uint8_t activation_without_reset : 1;
|
|
|
|
|
|
|
|
uint8_t frmw_rsvd : 3;
|
2015-09-21 15:52:41 +00:00
|
|
|
} frmw;
|
|
|
|
|
|
|
|
/** log page attributes */
|
|
|
|
struct {
|
|
|
|
/* per namespace smart/health log page */
|
|
|
|
uint8_t ns_smart : 1;
|
2016-01-06 05:43:33 +00:00
|
|
|
/* command effects log page */
|
|
|
|
uint8_t celp : 1;
|
2016-06-21 17:13:09 +00:00
|
|
|
/* extended data for get log page */
|
|
|
|
uint8_t edlp: 1;
|
|
|
|
uint8_t lpa_rsvd : 5;
|
2015-09-21 15:52:41 +00:00
|
|
|
} lpa;
|
|
|
|
|
|
|
|
/** error log page entries */
|
|
|
|
uint8_t elpe;
|
|
|
|
|
|
|
|
/** number of power states supported */
|
|
|
|
uint8_t npss;
|
|
|
|
|
|
|
|
/** admin vendor specific command configuration */
|
|
|
|
struct {
|
|
|
|
/* admin vendor specific commands use disk format */
|
|
|
|
uint8_t spec_format : 1;
|
|
|
|
|
|
|
|
uint8_t avscc_rsvd : 7;
|
|
|
|
} avscc;
|
|
|
|
|
|
|
|
/** autonomous power state transition attributes */
|
|
|
|
struct {
|
|
|
|
/** controller supports autonomous power state transitions */
|
|
|
|
uint8_t supported : 1;
|
|
|
|
|
|
|
|
uint8_t apsta_rsvd : 7;
|
|
|
|
} apsta;
|
|
|
|
|
|
|
|
/** warning composite temperature threshold */
|
|
|
|
uint16_t wctemp;
|
|
|
|
|
|
|
|
/** critical composite temperature threshold */
|
|
|
|
uint16_t cctemp;
|
|
|
|
|
|
|
|
/** maximum time for firmware activation */
|
|
|
|
uint16_t mtfa;
|
|
|
|
|
|
|
|
/** host memory buffer preferred size */
|
|
|
|
uint32_t hmpre;
|
|
|
|
|
|
|
|
/** host memory buffer minimum size */
|
|
|
|
uint32_t hmmin;
|
|
|
|
|
|
|
|
/** total NVM capacity */
|
|
|
|
uint64_t tnvmcap[2];
|
|
|
|
|
|
|
|
/** unallocated NVM capacity */
|
|
|
|
uint64_t unvmcap[2];
|
|
|
|
|
|
|
|
/** replay protected memory block support */
|
|
|
|
struct {
|
|
|
|
uint8_t num_rpmb_units : 3;
|
|
|
|
uint8_t auth_method : 3;
|
|
|
|
uint8_t reserved1 : 2;
|
|
|
|
|
|
|
|
uint8_t reserved2;
|
|
|
|
|
|
|
|
uint8_t total_size;
|
|
|
|
uint8_t access_size;
|
|
|
|
} rpmbs;
|
|
|
|
|
|
|
|
uint8_t reserved2[196];
|
|
|
|
|
|
|
|
/* bytes 512-703: nvm command set attributes */
|
|
|
|
|
|
|
|
/** submission queue entry size */
|
|
|
|
struct {
|
|
|
|
uint8_t min : 4;
|
|
|
|
uint8_t max : 4;
|
|
|
|
} sqes;
|
|
|
|
|
|
|
|
/** completion queue entry size */
|
|
|
|
struct {
|
|
|
|
uint8_t min : 4;
|
|
|
|
uint8_t max : 4;
|
|
|
|
} cqes;
|
|
|
|
|
|
|
|
uint8_t reserved3[2];
|
|
|
|
|
|
|
|
/** number of namespaces */
|
|
|
|
uint32_t nn;
|
|
|
|
|
|
|
|
/** optional nvm command support */
|
|
|
|
struct {
|
|
|
|
uint16_t compare : 1;
|
|
|
|
uint16_t write_unc : 1;
|
|
|
|
uint16_t dsm: 1;
|
2015-12-22 21:55:25 +00:00
|
|
|
uint16_t write_zeroes: 1;
|
|
|
|
uint16_t set_features_save: 1;
|
|
|
|
uint16_t reservations: 1;
|
|
|
|
uint16_t reserved: 10;
|
2015-09-21 15:52:41 +00:00
|
|
|
} oncs;
|
|
|
|
|
|
|
|
/** fused operation support */
|
|
|
|
uint16_t fuses;
|
|
|
|
|
|
|
|
/** format nvm attributes */
|
2016-03-07 06:29:50 +00:00
|
|
|
struct {
|
|
|
|
uint8_t format_all_ns: 1;
|
|
|
|
uint8_t erase_all_ns: 1;
|
|
|
|
uint8_t crypto_erase_supported: 1;
|
|
|
|
uint8_t reserved: 5;
|
|
|
|
} fna;
|
2015-09-21 15:52:41 +00:00
|
|
|
|
|
|
|
/** volatile write cache */
|
|
|
|
struct {
|
|
|
|
uint8_t present : 1;
|
|
|
|
uint8_t reserved : 7;
|
|
|
|
} vwc;
|
|
|
|
|
|
|
|
/** atomic write unit normal */
|
|
|
|
uint16_t awun;
|
|
|
|
|
|
|
|
/** atomic write unit power fail */
|
|
|
|
uint16_t awupf;
|
|
|
|
|
|
|
|
/** NVM vendor specific command configuration */
|
|
|
|
uint8_t nvscc;
|
|
|
|
|
|
|
|
uint8_t reserved531;
|
|
|
|
|
|
|
|
/** atomic compare & write unit */
|
|
|
|
uint16_t acwu;
|
|
|
|
|
|
|
|
uint16_t reserved534;
|
|
|
|
|
|
|
|
/** SGL support */
|
|
|
|
struct {
|
|
|
|
uint32_t supported : 1;
|
|
|
|
uint32_t reserved : 15;
|
|
|
|
uint32_t bit_bucket_descriptor_supported : 1;
|
|
|
|
uint32_t metadata_pointer_supported : 1;
|
|
|
|
uint32_t oversized_sgl_supported : 1;
|
|
|
|
} sgls;
|
|
|
|
|
|
|
|
uint8_t reserved4[164];
|
|
|
|
|
|
|
|
/* bytes 704-2047: i/o command set attributes */
|
|
|
|
uint8_t reserved5[1344];
|
|
|
|
|
|
|
|
/* bytes 2048-3071: power state descriptors */
|
2016-02-09 18:06:48 +00:00
|
|
|
struct spdk_nvme_power_state psd[32];
|
2015-09-21 15:52:41 +00:00
|
|
|
|
|
|
|
/* bytes 3072-4095: vendor specific */
|
|
|
|
uint8_t vs[1024];
|
|
|
|
};
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_STATIC_ASSERT(sizeof(struct spdk_nvme_ctrlr_data) == 4096, "Incorrect size");
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
struct spdk_nvme_ns_data {
|
2015-09-21 15:52:41 +00:00
|
|
|
/** namespace size */
|
|
|
|
uint64_t nsze;
|
|
|
|
|
|
|
|
/** namespace capacity */
|
|
|
|
uint64_t ncap;
|
|
|
|
|
|
|
|
/** namespace utilization */
|
|
|
|
uint64_t nuse;
|
|
|
|
|
|
|
|
/** namespace features */
|
|
|
|
struct {
|
|
|
|
/** thin provisioning */
|
|
|
|
uint8_t thin_prov : 1;
|
|
|
|
uint8_t reserved1 : 7;
|
|
|
|
} nsfeat;
|
|
|
|
|
|
|
|
/** number of lba formats */
|
|
|
|
uint8_t nlbaf;
|
|
|
|
|
|
|
|
/** formatted lba size */
|
|
|
|
struct {
|
|
|
|
uint8_t format : 4;
|
|
|
|
uint8_t extended : 1;
|
|
|
|
uint8_t reserved2 : 3;
|
|
|
|
} flbas;
|
|
|
|
|
|
|
|
/** metadata capabilities */
|
|
|
|
struct {
|
|
|
|
/** metadata can be transferred as part of data prp list */
|
|
|
|
uint8_t extended : 1;
|
|
|
|
|
|
|
|
/** metadata can be transferred with separate metadata pointer */
|
|
|
|
uint8_t pointer : 1;
|
|
|
|
|
|
|
|
/** reserved */
|
|
|
|
uint8_t reserved3 : 6;
|
|
|
|
} mc;
|
|
|
|
|
|
|
|
/** end-to-end data protection capabilities */
|
|
|
|
struct {
|
|
|
|
/** protection information type 1 */
|
|
|
|
uint8_t pit1 : 1;
|
|
|
|
|
|
|
|
/** protection information type 2 */
|
|
|
|
uint8_t pit2 : 1;
|
|
|
|
|
|
|
|
/** protection information type 3 */
|
|
|
|
uint8_t pit3 : 1;
|
|
|
|
|
|
|
|
/** first eight bytes of metadata */
|
|
|
|
uint8_t md_start : 1;
|
|
|
|
|
|
|
|
/** last eight bytes of metadata */
|
|
|
|
uint8_t md_end : 1;
|
|
|
|
} dpc;
|
|
|
|
|
|
|
|
/** end-to-end data protection type settings */
|
|
|
|
struct {
|
|
|
|
/** protection information type */
|
|
|
|
uint8_t pit : 3;
|
|
|
|
|
|
|
|
/** 1 == protection info transferred at start of metadata */
|
|
|
|
/** 0 == protection info transferred at end of metadata */
|
|
|
|
uint8_t md_start : 1;
|
|
|
|
|
|
|
|
uint8_t reserved4 : 4;
|
|
|
|
} dps;
|
|
|
|
|
|
|
|
/** namespace multi-path I/O and namespace sharing capabilities */
|
|
|
|
struct {
|
|
|
|
uint8_t can_share : 1;
|
|
|
|
uint8_t reserved : 7;
|
|
|
|
} nmic;
|
|
|
|
|
|
|
|
/** reservation capabilities */
|
2016-01-27 03:10:01 +00:00
|
|
|
union {
|
|
|
|
struct {
|
|
|
|
/** supports persist through power loss */
|
|
|
|
uint8_t persist : 1;
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-01-27 03:10:01 +00:00
|
|
|
/** supports write exclusive */
|
|
|
|
uint8_t write_exclusive : 1;
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-01-27 03:10:01 +00:00
|
|
|
/** supports exclusive access */
|
|
|
|
uint8_t exclusive_access : 1;
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-01-27 03:10:01 +00:00
|
|
|
/** supports write exclusive - registrants only */
|
|
|
|
uint8_t write_exclusive_reg_only : 1;
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-01-27 03:10:01 +00:00
|
|
|
/** supports exclusive access - registrants only */
|
|
|
|
uint8_t exclusive_access_reg_only : 1;
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-01-27 03:10:01 +00:00
|
|
|
/** supports write exclusive - all registrants */
|
|
|
|
uint8_t write_exclusive_all_reg : 1;
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-01-27 03:10:01 +00:00
|
|
|
/** supports exclusive access - all registrants */
|
|
|
|
uint8_t exclusive_access_all_reg : 1;
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-01-27 03:10:01 +00:00
|
|
|
uint8_t reserved : 1;
|
|
|
|
} rescap;
|
|
|
|
uint8_t raw;
|
|
|
|
} nsrescap;
|
2015-09-21 15:52:41 +00:00
|
|
|
/** format progress indicator */
|
2016-03-08 06:00:07 +00:00
|
|
|
struct {
|
|
|
|
uint8_t percentage_remaining : 7;
|
|
|
|
uint8_t fpi_supported : 1;
|
|
|
|
} fpi;
|
2015-09-21 15:52:41 +00:00
|
|
|
|
|
|
|
uint8_t reserved33;
|
|
|
|
|
|
|
|
/** namespace atomic write unit normal */
|
|
|
|
uint16_t nawun;
|
|
|
|
|
|
|
|
/** namespace atomic write unit power fail */
|
|
|
|
uint16_t nawupf;
|
|
|
|
|
|
|
|
/** namespace atomic compare & write unit */
|
|
|
|
uint16_t nacwu;
|
|
|
|
|
|
|
|
/** namespace atomic boundary size normal */
|
|
|
|
uint16_t nabsn;
|
|
|
|
|
|
|
|
/** namespace atomic boundary offset */
|
|
|
|
uint16_t nabo;
|
|
|
|
|
|
|
|
/** namespace atomic boundary size power fail */
|
|
|
|
uint16_t nabspf;
|
|
|
|
|
|
|
|
uint16_t reserved46;
|
|
|
|
|
|
|
|
/** NVM capacity */
|
|
|
|
uint64_t nvmcap[2];
|
|
|
|
|
|
|
|
uint8_t reserved64[40];
|
|
|
|
|
|
|
|
/** namespace globally unique identifier */
|
|
|
|
uint8_t nguid[16];
|
|
|
|
|
|
|
|
/** IEEE extended unique identifier */
|
|
|
|
uint64_t eui64;
|
|
|
|
|
|
|
|
/** lba format support */
|
|
|
|
struct {
|
|
|
|
/** metadata size */
|
|
|
|
uint32_t ms : 16;
|
|
|
|
|
|
|
|
/** lba data size */
|
|
|
|
uint32_t lbads : 8;
|
|
|
|
|
|
|
|
/** relative performance */
|
|
|
|
uint32_t rp : 2;
|
|
|
|
|
|
|
|
uint32_t reserved6 : 6;
|
|
|
|
} lbaf[16];
|
|
|
|
|
|
|
|
uint8_t reserved6[192];
|
|
|
|
|
|
|
|
uint8_t vendor_specific[3712];
|
|
|
|
};
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_STATIC_ASSERT(sizeof(struct spdk_nvme_ns_data) == 4096, "Incorrect size");
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-01-22 08:39:55 +00:00
|
|
|
/**
|
|
|
|
* Reservation Type Encoding
|
|
|
|
*/
|
2016-02-09 18:06:48 +00:00
|
|
|
enum spdk_nvme_reservation_type {
|
2016-01-22 08:39:55 +00:00
|
|
|
/* 0x00 - reserved */
|
|
|
|
|
|
|
|
/* Write Exclusive Reservation */
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_NVME_RESERVE_WRITE_EXCLUSIVE = 0x1,
|
2016-01-22 08:39:55 +00:00
|
|
|
|
|
|
|
/* Exclusive Access Reservation */
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_NVME_RESERVE_EXCLUSIVE_ACCESS = 0x2,
|
2016-01-22 08:39:55 +00:00
|
|
|
|
|
|
|
/* Write Exclusive - Registrants Only Reservation */
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_NVME_RESERVE_WRITE_EXCLUSIVE_REG_ONLY = 0x3,
|
2016-01-22 08:39:55 +00:00
|
|
|
|
|
|
|
/* Exclusive Access - Registrants Only Reservation */
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_NVME_RESERVE_EXCLUSIVE_ACCESS_REG_ONLY = 0x4,
|
2016-01-22 08:39:55 +00:00
|
|
|
|
|
|
|
/* Write Exclusive - All Registrants Reservation */
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_NVME_RESERVE_WRITE_EXCLUSIVE_ALL_REGS = 0x5,
|
2016-01-22 08:39:55 +00:00
|
|
|
|
|
|
|
/* Exclusive Access - All Registrants Reservation */
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_NVME_RESERVE_EXCLUSIVE_ACCESS_ALL_REGS = 0x6,
|
2016-01-22 08:39:55 +00:00
|
|
|
|
|
|
|
/* 0x7-0xFF - Reserved */
|
|
|
|
};
|
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
struct spdk_nvme_reservation_acquire_data {
|
2016-01-22 08:39:55 +00:00
|
|
|
/** current reservation key */
|
|
|
|
uint64_t crkey;
|
|
|
|
/** preempt reservation key */
|
|
|
|
uint64_t prkey;
|
|
|
|
};
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_STATIC_ASSERT(sizeof(struct spdk_nvme_reservation_acquire_data) == 16, "Incorrect size");
|
2016-01-22 08:39:55 +00:00
|
|
|
|
|
|
|
/**
|
|
|
|
* Reservation Acquire action
|
|
|
|
*/
|
2016-02-09 18:06:48 +00:00
|
|
|
enum spdk_nvme_reservation_acquire_action {
|
|
|
|
SPDK_NVME_RESERVE_ACQUIRE = 0x0,
|
|
|
|
SPDK_NVME_RESERVE_PREEMPT = 0x1,
|
|
|
|
SPDK_NVME_RESERVE_PREEMPT_ABORT = 0x2,
|
2016-01-22 08:39:55 +00:00
|
|
|
};
|
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
struct __attribute__((packed)) spdk_nvme_reservation_status_data {
|
2016-01-22 08:39:55 +00:00
|
|
|
/** reservation action generation counter */
|
|
|
|
uint32_t generation;
|
|
|
|
/** reservation type */
|
|
|
|
uint8_t type;
|
|
|
|
/** number of registered controllers */
|
|
|
|
uint16_t nr_regctl;
|
|
|
|
uint16_t reserved1;
|
|
|
|
/** persist through power loss state */
|
|
|
|
uint8_t ptpl_state;
|
|
|
|
uint8_t reserved[14];
|
|
|
|
};
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_STATIC_ASSERT(sizeof(struct spdk_nvme_reservation_status_data) == 24, "Incorrect size");
|
2016-01-22 08:39:55 +00:00
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
struct __attribute__((packed)) spdk_nvme_reservation_ctrlr_data {
|
2016-01-22 08:39:55 +00:00
|
|
|
uint16_t ctrlr_id;
|
|
|
|
/** reservation status */
|
|
|
|
struct {
|
|
|
|
uint8_t status : 1;
|
|
|
|
uint8_t reserved1 : 7;
|
|
|
|
} rcsts;
|
|
|
|
uint8_t reserved2[5];
|
|
|
|
/** host identifier */
|
|
|
|
uint64_t host_id;
|
|
|
|
/** reservation key */
|
|
|
|
uint64_t key;
|
|
|
|
};
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_STATIC_ASSERT(sizeof(struct spdk_nvme_reservation_ctrlr_data) == 24, "Incorrect size");
|
2016-01-22 08:39:55 +00:00
|
|
|
|
|
|
|
/**
|
|
|
|
* Change persist through power loss state for
|
|
|
|
* Reservation Register command
|
|
|
|
*/
|
2016-02-09 18:06:48 +00:00
|
|
|
enum spdk_nvme_reservation_register_cptpl {
|
|
|
|
SPDK_NVME_RESERVE_PTPL_NO_CHANGES = 0x0,
|
|
|
|
SPDK_NVME_RESERVE_PTPL_CLEAR_POWER_ON = 0x2,
|
|
|
|
SPDK_NVME_RESERVE_PTPL_PERSIST_POWER_LOSS = 0x3,
|
2016-01-22 08:39:55 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Registration action for Reservation Register command
|
|
|
|
*/
|
2016-02-09 18:06:48 +00:00
|
|
|
enum spdk_nvme_reservation_register_action {
|
|
|
|
SPDK_NVME_RESERVE_REGISTER_KEY = 0x0,
|
|
|
|
SPDK_NVME_RESERVE_UNREGISTER_KEY = 0x1,
|
|
|
|
SPDK_NVME_RESERVE_REPLACE_KEY = 0x2,
|
2016-01-22 08:39:55 +00:00
|
|
|
};
|
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
struct spdk_nvme_reservation_register_data {
|
2016-01-22 08:39:55 +00:00
|
|
|
/** current reservation key */
|
|
|
|
uint64_t crkey;
|
|
|
|
/** new reservation key */
|
|
|
|
uint64_t nrkey;
|
|
|
|
};
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_STATIC_ASSERT(sizeof(struct spdk_nvme_reservation_register_data) == 16, "Incorrect size");
|
2016-01-22 08:39:55 +00:00
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
struct spdk_nvme_reservation_key_data {
|
2016-01-22 08:39:55 +00:00
|
|
|
/** current reservation key */
|
|
|
|
uint64_t crkey;
|
|
|
|
};
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_STATIC_ASSERT(sizeof(struct spdk_nvme_reservation_key_data) == 8, "Incorrect size");
|
2016-01-22 08:39:55 +00:00
|
|
|
|
|
|
|
/**
|
|
|
|
* Reservation Release action
|
|
|
|
*/
|
2016-02-09 18:06:48 +00:00
|
|
|
enum spdk_nvme_reservation_release_action {
|
|
|
|
SPDK_NVME_RESERVE_RELEASE = 0x0,
|
|
|
|
SPDK_NVME_RESERVE_CLEAR = 0x1,
|
2016-01-22 08:39:55 +00:00
|
|
|
};
|
|
|
|
|
2016-01-15 20:01:30 +00:00
|
|
|
/**
|
2016-02-09 18:06:48 +00:00
|
|
|
* Log page identifiers for SPDK_NVME_OPC_GET_LOG_PAGE
|
2016-01-15 20:01:30 +00:00
|
|
|
*/
|
2016-02-09 18:06:48 +00:00
|
|
|
enum spdk_nvme_log_page {
|
2015-09-21 15:52:41 +00:00
|
|
|
/* 0x00 - reserved */
|
2016-01-15 20:01:30 +00:00
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
/** Error information (mandatory) - \ref spdk_nvme_error_information_entry */
|
|
|
|
SPDK_NVME_LOG_ERROR = 0x01,
|
2016-01-15 20:01:30 +00:00
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
/** SMART / health information (mandatory) - \ref spdk_nvme_health_information_page */
|
|
|
|
SPDK_NVME_LOG_HEALTH_INFORMATION = 0x02,
|
2016-01-15 20:01:30 +00:00
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
/** Firmware slot information (mandatory) - \ref spdk_nvme_firmware_page */
|
|
|
|
SPDK_NVME_LOG_FIRMWARE_SLOT = 0x03,
|
2016-01-15 20:01:30 +00:00
|
|
|
|
|
|
|
/** Changed namespace list (optional) */
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_NVME_LOG_CHANGED_NS_LIST = 0x04,
|
2016-01-15 20:01:30 +00:00
|
|
|
|
|
|
|
/** Command effects log (optional) */
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_NVME_LOG_COMMAND_EFFECTS_LOG = 0x05,
|
2016-01-15 20:01:30 +00:00
|
|
|
|
2016-06-21 17:13:09 +00:00
|
|
|
/* 0x06-0x6F - reserved */
|
|
|
|
|
|
|
|
/** Discovery(refer to the NVMe over Fabrics specification) */
|
|
|
|
SPDK_NVME_LOG_DISCOVERY = 0x70,
|
|
|
|
|
|
|
|
/* 0x71-0x7f - reserved for NVMe over Fabrics */
|
2016-01-15 20:01:30 +00:00
|
|
|
|
|
|
|
/** Reservation notification (optional) */
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_NVME_LOG_RESERVATION_NOTIFICATION = 0x80,
|
2016-01-15 20:01:30 +00:00
|
|
|
|
2016-01-06 05:43:33 +00:00
|
|
|
/* 0x81-0xBF - I/O command set specific */
|
2016-01-15 20:01:30 +00:00
|
|
|
|
2015-09-21 15:52:41 +00:00
|
|
|
/* 0xC0-0xFF - vendor specific */
|
|
|
|
};
|
|
|
|
|
2016-01-15 20:01:30 +00:00
|
|
|
/**
|
2016-02-09 18:06:48 +00:00
|
|
|
* Error information log page (\ref SPDK_NVME_LOG_ERROR)
|
2016-01-15 20:01:30 +00:00
|
|
|
*/
|
2016-02-09 18:06:48 +00:00
|
|
|
struct spdk_nvme_error_information_entry {
|
2015-09-21 15:52:41 +00:00
|
|
|
uint64_t error_count;
|
|
|
|
uint16_t sqid;
|
|
|
|
uint16_t cid;
|
2016-02-09 18:06:48 +00:00
|
|
|
struct spdk_nvme_status status;
|
2015-09-21 15:52:41 +00:00
|
|
|
uint16_t error_location;
|
|
|
|
uint64_t lba;
|
|
|
|
uint32_t nsid;
|
|
|
|
uint8_t vendor_specific;
|
|
|
|
uint8_t reserved[35];
|
|
|
|
};
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_STATIC_ASSERT(sizeof(struct spdk_nvme_error_information_entry) == 64, "Incorrect size");
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
union spdk_nvme_critical_warning_state {
|
2015-09-21 15:52:41 +00:00
|
|
|
uint8_t raw;
|
|
|
|
|
|
|
|
struct {
|
|
|
|
uint8_t available_spare : 1;
|
|
|
|
uint8_t temperature : 1;
|
|
|
|
uint8_t device_reliability : 1;
|
|
|
|
uint8_t read_only : 1;
|
|
|
|
uint8_t volatile_memory_backup : 1;
|
|
|
|
uint8_t reserved : 3;
|
|
|
|
} bits;
|
|
|
|
};
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_STATIC_ASSERT(sizeof(union spdk_nvme_critical_warning_state) == 1, "Incorrect size");
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-01-15 20:01:30 +00:00
|
|
|
/**
|
2016-02-09 18:06:48 +00:00
|
|
|
* SMART / health information page (\ref SPDK_NVME_LOG_HEALTH_INFORMATION)
|
2016-01-15 20:01:30 +00:00
|
|
|
*/
|
2016-02-09 18:06:48 +00:00
|
|
|
struct __attribute__((packed)) spdk_nvme_health_information_page {
|
|
|
|
union spdk_nvme_critical_warning_state critical_warning;
|
2015-09-21 15:52:41 +00:00
|
|
|
|
|
|
|
uint16_t temperature;
|
|
|
|
uint8_t available_spare;
|
|
|
|
uint8_t available_spare_threshold;
|
|
|
|
uint8_t percentage_used;
|
|
|
|
|
|
|
|
uint8_t reserved[26];
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Note that the following are 128-bit values, but are
|
|
|
|
* defined as an array of 2 64-bit values.
|
|
|
|
*/
|
|
|
|
/* Data Units Read is always in 512-byte units. */
|
|
|
|
uint64_t data_units_read[2];
|
|
|
|
/* Data Units Written is always in 512-byte units. */
|
|
|
|
uint64_t data_units_written[2];
|
|
|
|
/* For NVM command set, this includes Compare commands. */
|
|
|
|
uint64_t host_read_commands[2];
|
|
|
|
uint64_t host_write_commands[2];
|
|
|
|
/* Controller Busy Time is reported in minutes. */
|
|
|
|
uint64_t controller_busy_time[2];
|
|
|
|
uint64_t power_cycles[2];
|
|
|
|
uint64_t power_on_hours[2];
|
|
|
|
uint64_t unsafe_shutdowns[2];
|
|
|
|
uint64_t media_errors[2];
|
|
|
|
uint64_t num_error_info_log_entries[2];
|
|
|
|
|
|
|
|
uint8_t reserved2[320];
|
|
|
|
};
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_STATIC_ASSERT(sizeof(struct spdk_nvme_health_information_page) == 512, "Incorrect size");
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-01-15 20:01:30 +00:00
|
|
|
/**
|
2016-02-09 18:06:48 +00:00
|
|
|
* Firmware slot information page (\ref SPDK_NVME_LOG_FIRMWARE_SLOT)
|
2016-01-15 20:01:30 +00:00
|
|
|
*/
|
2016-02-09 18:06:48 +00:00
|
|
|
struct spdk_nvme_firmware_page {
|
2015-09-21 15:52:41 +00:00
|
|
|
struct {
|
|
|
|
uint8_t slot : 3; /* slot for current FW */
|
|
|
|
uint8_t reserved : 5;
|
|
|
|
} afi;
|
|
|
|
|
|
|
|
uint8_t reserved[7];
|
|
|
|
uint64_t revision[7]; /* revisions for 7 slots */
|
|
|
|
uint8_t reserved2[448];
|
|
|
|
};
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_STATIC_ASSERT(sizeof(struct spdk_nvme_firmware_page) == 512, "Incorrect size");
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-01-29 06:15:18 +00:00
|
|
|
/**
|
|
|
|
* Namespace attachment Type Encoding
|
|
|
|
*/
|
2016-02-09 18:06:48 +00:00
|
|
|
enum spdk_nvme_ns_attach_type {
|
2016-01-29 06:15:18 +00:00
|
|
|
/* Controller attach */
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_NVME_NS_CTRLR_ATTACH = 0x0,
|
2016-01-29 06:15:18 +00:00
|
|
|
|
|
|
|
/* Controller detach */
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_NVME_NS_CTRLR_DETACH = 0x1,
|
2016-01-29 06:15:18 +00:00
|
|
|
|
|
|
|
/* 0x2-0xF - Reserved */
|
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Namespace management Type Encoding
|
|
|
|
*/
|
2016-02-09 18:06:48 +00:00
|
|
|
enum spdk_nvme_ns_management_type {
|
2016-01-29 06:15:18 +00:00
|
|
|
/* Create */
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_NVME_NS_MANAGEMENT_CREATE = 0x0,
|
2016-01-29 06:15:18 +00:00
|
|
|
|
|
|
|
/* Delete */
|
2016-02-09 18:06:48 +00:00
|
|
|
SPDK_NVME_NS_MANAGEMENT_DELETE = 0x1,
|
2016-01-29 06:15:18 +00:00
|
|
|
|
|
|
|
/* 0x2-0xF - Reserved */
|
|
|
|
};
|
|
|
|
|
2016-02-25 03:44:44 +00:00
|
|
|
struct spdk_nvme_ns_list {
|
|
|
|
uint32_t ns_list[1024];
|
|
|
|
};
|
|
|
|
SPDK_STATIC_ASSERT(sizeof(struct spdk_nvme_ns_list) == 4096, "Incorrect size");
|
|
|
|
|
|
|
|
struct spdk_nvme_ctrlr_list {
|
|
|
|
uint16_t ctrlr_count;
|
|
|
|
uint16_t ctrlr_list[2047];
|
|
|
|
};
|
|
|
|
SPDK_STATIC_ASSERT(sizeof(struct spdk_nvme_ctrlr_list) == 4096, "Incorrect size");
|
|
|
|
|
2016-03-07 06:29:50 +00:00
|
|
|
enum spdk_nvme_secure_erase_setting {
|
|
|
|
SPDK_NVME_FMT_NVM_SES_NO_SECURE_ERASE = 0x0,
|
|
|
|
SPDK_NVME_FMT_NVM_SES_USER_DATA_ERASE = 0x1,
|
|
|
|
SPDK_NVME_FMT_NVM_SES_CRYPTO_ERASE = 0x2,
|
|
|
|
};
|
|
|
|
|
2016-04-12 01:00:48 +00:00
|
|
|
enum spdk_nvme_pi_location {
|
2016-03-07 06:29:50 +00:00
|
|
|
SPDK_NVME_FMT_NVM_PROTECTION_AT_TAIL = 0x0,
|
|
|
|
SPDK_NVME_FMT_NVM_PROTECTION_AT_HEAD = 0x1,
|
|
|
|
};
|
|
|
|
|
2016-04-12 01:00:48 +00:00
|
|
|
enum spdk_nvme_pi_type {
|
2016-03-07 06:29:50 +00:00
|
|
|
SPDK_NVME_FMT_NVM_PROTECTION_DISABLE = 0x0,
|
|
|
|
SPDK_NVME_FMT_NVM_PROTECTION_TYPE1 = 0x1,
|
|
|
|
SPDK_NVME_FMT_NVM_PROTECTION_TYPE2 = 0x2,
|
|
|
|
SPDK_NVME_FMT_NVM_PROTECTION_TYPE3 = 0x3,
|
|
|
|
};
|
|
|
|
|
|
|
|
enum spdk_nvme_metadata_setting {
|
|
|
|
SPDK_NVME_FMT_NVM_METADATA_TRANSFER_AS_BUFFER = 0x0,
|
|
|
|
SPDK_NVME_FMT_NVM_METADATA_TRANSFER_AS_LBA = 0x1,
|
|
|
|
};
|
|
|
|
|
|
|
|
struct spdk_nvme_format {
|
|
|
|
uint32_t lbaf : 4;
|
|
|
|
uint32_t ms : 1;
|
|
|
|
uint32_t pi : 3;
|
|
|
|
uint32_t pil : 1;
|
|
|
|
uint32_t ses : 3;
|
|
|
|
uint32_t reserved : 20;
|
|
|
|
};
|
|
|
|
SPDK_STATIC_ASSERT(sizeof(struct spdk_nvme_format) == 4, "Incorrect size");
|
|
|
|
|
2016-04-07 06:52:43 +00:00
|
|
|
struct spdk_nvme_protection_info {
|
|
|
|
uint16_t guard;
|
|
|
|
uint16_t app_tag;
|
|
|
|
uint32_t ref_tag;
|
|
|
|
};
|
|
|
|
SPDK_STATIC_ASSERT(sizeof(struct spdk_nvme_protection_info) == 8, "Incorrect size");
|
|
|
|
|
2016-05-03 05:18:39 +00:00
|
|
|
/** Parameters for SPDK_NVME_OPC_FIRMWARE_COMMIT cdw10: commit action */
|
|
|
|
enum spdk_nvme_fw_commit_action {
|
|
|
|
/**
|
|
|
|
* Downloaded image replaces the image specified by
|
|
|
|
* the Firmware Slot field. This image is not activated.
|
|
|
|
*/
|
|
|
|
SPDK_NVME_FW_COMMIT_REPLACE_IMG = 0x0,
|
|
|
|
/**
|
|
|
|
* Downloaded image replaces the image specified by
|
|
|
|
* the Firmware Slot field. This image is activated at the next reset.
|
|
|
|
*/
|
|
|
|
SPDK_NVME_FW_COMMIT_REPLACE_AND_ENABLE_IMG = 0x1,
|
|
|
|
/**
|
|
|
|
* The image specified by the Firmware Slot field is
|
|
|
|
* activated at the next reset.
|
|
|
|
*/
|
|
|
|
SPDK_NVME_FW_COMMIT_ENABLE_IMG = 0x2,
|
|
|
|
/**
|
|
|
|
* The image specified by the Firmware Slot field is
|
|
|
|
* requested to be activated immediately without reset.
|
|
|
|
*/
|
|
|
|
SPDK_NVME_FW_COMMIT_RUN_IMG = 0x3,
|
|
|
|
};
|
|
|
|
|
|
|
|
/** Parameters for SPDK_NVME_OPC_FIRMWARE_COMMIT cdw10 */
|
|
|
|
struct spdk_nvme_fw_commit {
|
|
|
|
/**
|
|
|
|
* Firmware Slot. Specifies the firmware slot that shall be used for the
|
|
|
|
* Commit Action. The controller shall choose the firmware slot (slot 1 - 7)
|
|
|
|
* to use for the operation if the value specified is 0h.
|
|
|
|
*/
|
|
|
|
uint32_t fs : 3;
|
|
|
|
/**
|
|
|
|
* Commit Action. Specifies the action that is taken on the image downloaded
|
|
|
|
* with the Firmware Image Download command or on a previously downloaded and
|
|
|
|
* placed image.
|
|
|
|
*/
|
|
|
|
uint32_t ca : 3;
|
|
|
|
uint32_t reserved : 26;
|
|
|
|
};
|
|
|
|
SPDK_STATIC_ASSERT(sizeof(struct spdk_nvme_fw_commit) == 4, "Incorrect size");
|
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
#define spdk_nvme_cpl_is_error(cpl) \
|
2015-09-21 15:52:41 +00:00
|
|
|
((cpl)->status.sc != 0 || (cpl)->status.sct != 0)
|
|
|
|
|
2016-04-07 06:52:43 +00:00
|
|
|
/** Enable protection information checking of the Logical Block Reference Tag field */
|
|
|
|
#define SPDK_NVME_IO_FLAGS_PRCHK_REFTAG (1U << 26)
|
|
|
|
/** Enable protection information checking of the Application Tag field */
|
|
|
|
#define SPDK_NVME_IO_FLAGS_PRCHK_APPTAG (1U << 27)
|
|
|
|
/** Enable protection information checking of the Guard field */
|
|
|
|
#define SPDK_NVME_IO_FLAGS_PRCHK_GUARD (1U << 28)
|
|
|
|
/** The protection information is stripped or inserted when set this bit */
|
|
|
|
#define SPDK_NVME_IO_FLAGS_PRACT (1U << 29)
|
2016-02-09 18:06:48 +00:00
|
|
|
#define SPDK_NVME_IO_FLAGS_FORCE_UNIT_ACCESS (1U << 30)
|
|
|
|
#define SPDK_NVME_IO_FLAGS_LIMITED_RETRY (1U << 31)
|
2015-12-30 22:52:17 +00:00
|
|
|
|
2016-02-12 14:52:35 +00:00
|
|
|
#ifdef __cplusplus
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2015-09-21 15:52:41 +00:00
|
|
|
#endif
|