2015-09-21 15:52:41 +00:00
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/*-
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* BSD LICENSE
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*
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2016-01-26 17:47:22 +00:00
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* Copyright (c) Intel Corporation.
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2015-09-21 15:52:41 +00:00
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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2016-02-03 21:36:26 +00:00
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2015-09-21 15:52:41 +00:00
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#include "nvme_internal.h"
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2016-08-10 17:41:12 +00:00
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#include "spdk/env.h"
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2016-01-27 07:08:53 +00:00
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2016-02-10 18:26:12 +00:00
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static int nvme_ctrlr_construct_and_submit_aer(struct spdk_nvme_ctrlr *ctrlr,
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2015-09-21 15:52:41 +00:00
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struct nvme_async_event_request *aer);
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2016-10-13 00:00:54 +00:00
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static int
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nvme_ctrlr_get_cc(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_cc_register *cc)
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{
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return ctrlr->transport->ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, cc.raw),
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&cc->raw);
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}
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static int
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nvme_ctrlr_get_csts(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_csts_register *csts)
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{
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return ctrlr->transport->ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, csts.raw),
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&csts->raw);
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}
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2016-10-13 23:08:22 +00:00
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int
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2016-10-13 00:00:54 +00:00
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nvme_ctrlr_get_cap(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_cap_register *cap)
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{
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return ctrlr->transport->ctrlr_get_reg_8(ctrlr, offsetof(struct spdk_nvme_registers, cap.raw),
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&cap->raw);
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}
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static int
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nvme_ctrlr_get_vs(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_vs_register *vs)
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{
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return ctrlr->transport->ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, vs.raw),
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&vs->raw);
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}
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static int
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nvme_ctrlr_set_cc(struct spdk_nvme_ctrlr *ctrlr, const union spdk_nvme_cc_register *cc)
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{
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return ctrlr->transport->ctrlr_set_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, cc.raw),
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cc->raw);
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}
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static int
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nvme_ctrlr_set_asq(struct spdk_nvme_ctrlr *ctrlr, uint64_t value)
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{
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return ctrlr->transport->ctrlr_set_reg_8(ctrlr, offsetof(struct spdk_nvme_registers, asq),
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value);
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}
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static int
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nvme_ctrlr_set_acq(struct spdk_nvme_ctrlr *ctrlr, uint64_t value)
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{
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return ctrlr->transport->ctrlr_set_reg_8(ctrlr, offsetof(struct spdk_nvme_registers, acq),
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value);
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}
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static int
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nvme_ctrlr_set_aqa(struct spdk_nvme_ctrlr *ctrlr, const union spdk_nvme_aqa_register *aqa)
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{
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return ctrlr->transport->ctrlr_set_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, aqa.raw),
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aqa->raw);
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}
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2016-03-07 17:36:17 +00:00
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void
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spdk_nvme_ctrlr_opts_set_defaults(struct spdk_nvme_ctrlr_opts *opts)
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{
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opts->num_io_queues = DEFAULT_MAX_IO_QUEUES;
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2016-05-05 01:41:16 +00:00
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opts->use_cmb_sqs = false;
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2016-06-14 07:19:38 +00:00
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opts->arb_mechanism = SPDK_NVME_CC_AMS_RR;
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2016-03-07 17:36:17 +00:00
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}
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2016-02-29 21:19:02 +00:00
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struct spdk_nvme_qpair *
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spdk_nvme_ctrlr_alloc_io_qpair(struct spdk_nvme_ctrlr *ctrlr,
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enum spdk_nvme_qprio qprio)
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{
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2016-10-18 16:49:07 +00:00
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uint32_t qid;
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2016-02-29 21:19:02 +00:00
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struct spdk_nvme_qpair *qpair;
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2016-06-14 07:19:38 +00:00
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union spdk_nvme_cc_register cc;
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2016-10-13 00:00:54 +00:00
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if (nvme_ctrlr_get_cc(ctrlr, &cc)) {
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SPDK_TRACELOG(SPDK_TRACE_NVME, "get_cc failed\n");
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return NULL;
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}
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2016-02-29 21:19:02 +00:00
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/* Only the low 2 bits (values 0, 1, 2, 3) of QPRIO are valid. */
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if ((qprio & 3) != qprio) {
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return NULL;
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}
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2016-06-14 07:19:38 +00:00
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/*
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* Only value SPDK_NVME_QPRIO_URGENT(0) is valid for the
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* default round robin arbitration method.
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*/
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if ((cc.bits.ams == SPDK_NVME_CC_AMS_RR) && (qprio != SPDK_NVME_QPRIO_URGENT)) {
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2016-08-12 16:03:40 +00:00
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SPDK_ERRLOG("invalid queue priority for default round robin arbitration method\n");
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2016-06-14 07:19:38 +00:00
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return NULL;
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}
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2016-08-08 17:03:52 +00:00
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pthread_mutex_lock(&ctrlr->ctrlr_lock);
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2016-02-29 21:19:02 +00:00
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/*
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2016-10-18 16:49:07 +00:00
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* Get the first available I/O queue ID.
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2016-02-29 21:19:02 +00:00
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*/
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2016-10-18 16:49:07 +00:00
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qid = spdk_bit_array_find_first_set(ctrlr->free_io_qids, 1);
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if (qid > ctrlr->opts.num_io_queues) {
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SPDK_TRACELOG(SPDK_TRACE_NVME, "No free I/O queue IDs\n");
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2016-08-08 17:03:52 +00:00
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pthread_mutex_unlock(&ctrlr->ctrlr_lock);
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2016-02-29 21:19:02 +00:00
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return NULL;
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}
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2016-10-18 16:49:07 +00:00
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qpair = ctrlr->transport->ctrlr_create_io_qpair(ctrlr, qid, qprio);
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if (qpair == NULL) {
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SPDK_TRACELOG(SPDK_TRACE_NVME, "transport->ctrlr_create_io_qpair() failed\n");
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2016-08-08 17:03:52 +00:00
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pthread_mutex_unlock(&ctrlr->ctrlr_lock);
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2016-02-29 21:19:02 +00:00
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return NULL;
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}
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2016-10-18 16:49:07 +00:00
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spdk_bit_array_clear(ctrlr->free_io_qids, qid);
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2016-02-29 21:19:02 +00:00
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TAILQ_INSERT_TAIL(&ctrlr->active_io_qpairs, qpair, tailq);
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2016-08-08 17:03:52 +00:00
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pthread_mutex_unlock(&ctrlr->ctrlr_lock);
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2016-02-29 21:19:02 +00:00
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return qpair;
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}
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int
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spdk_nvme_ctrlr_free_io_qpair(struct spdk_nvme_qpair *qpair)
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{
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struct spdk_nvme_ctrlr *ctrlr;
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if (qpair == NULL) {
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return 0;
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}
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ctrlr = qpair->ctrlr;
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2016-08-08 17:03:52 +00:00
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pthread_mutex_lock(&ctrlr->ctrlr_lock);
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2016-02-29 21:19:02 +00:00
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2016-10-18 16:49:07 +00:00
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TAILQ_REMOVE(&ctrlr->active_io_qpairs, qpair, tailq);
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spdk_bit_array_set(ctrlr->free_io_qids, qpair->id);
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2016-10-13 00:33:37 +00:00
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if (ctrlr->transport->ctrlr_delete_io_qpair(ctrlr, qpair)) {
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2016-08-08 17:03:52 +00:00
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pthread_mutex_unlock(&ctrlr->ctrlr_lock);
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2016-02-29 21:19:02 +00:00
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return -1;
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}
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2016-08-08 17:03:52 +00:00
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pthread_mutex_unlock(&ctrlr->ctrlr_lock);
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2016-02-29 21:19:02 +00:00
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return 0;
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}
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2016-01-06 05:43:33 +00:00
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static void
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2016-02-10 18:26:12 +00:00
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nvme_ctrlr_construct_intel_support_log_page_list(struct spdk_nvme_ctrlr *ctrlr,
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2016-02-08 23:06:31 +00:00
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struct spdk_nvme_intel_log_page_directory *log_page_directory)
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2016-01-06 05:43:33 +00:00
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{
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2016-01-27 07:08:53 +00:00
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struct pci_id pci_id;
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2016-10-12 23:18:13 +00:00
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if (log_page_directory == NULL) {
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2016-01-06 05:43:33 +00:00
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return;
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2016-10-12 23:18:13 +00:00
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}
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if (ctrlr->transport->ctrlr_get_pci_id(ctrlr, &pci_id)) {
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return;
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}
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2016-01-06 05:43:33 +00:00
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2016-10-12 23:18:13 +00:00
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if (pci_id.vendor_id != SPDK_PCI_VID_INTEL) {
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return;
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}
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2016-01-27 07:08:53 +00:00
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2016-02-08 23:06:31 +00:00
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ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY] = true;
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2016-01-06 05:43:33 +00:00
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2016-01-27 07:08:53 +00:00
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if (log_page_directory->read_latency_log_len ||
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nvme_intel_has_quirk(&pci_id, NVME_INTEL_QUIRK_READ_LATENCY)) {
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2016-02-08 23:06:31 +00:00
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ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_READ_CMD_LATENCY] = true;
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2016-01-06 05:43:33 +00:00
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}
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2016-01-27 07:08:53 +00:00
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if (log_page_directory->write_latency_log_len ||
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nvme_intel_has_quirk(&pci_id, NVME_INTEL_QUIRK_WRITE_LATENCY)) {
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2016-02-08 23:06:31 +00:00
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ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_WRITE_CMD_LATENCY] = true;
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2016-01-06 05:43:33 +00:00
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}
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if (log_page_directory->temperature_statistics_log_len) {
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2016-02-08 23:06:31 +00:00
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ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_TEMPERATURE] = true;
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2016-01-06 05:43:33 +00:00
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}
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if (log_page_directory->smart_log_len) {
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2016-02-08 23:06:31 +00:00
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ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_SMART] = true;
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2016-01-06 05:43:33 +00:00
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}
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2016-05-04 03:17:59 +00:00
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if (log_page_directory->marketing_description_log_len) {
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ctrlr->log_page_supported[SPDK_NVME_INTEL_MARKETING_DESCRIPTION] = true;
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}
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2016-01-06 05:43:33 +00:00
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}
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2016-02-10 18:26:12 +00:00
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static int nvme_ctrlr_set_intel_support_log_pages(struct spdk_nvme_ctrlr *ctrlr)
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2016-01-06 05:43:33 +00:00
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{
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uint64_t phys_addr = 0;
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struct nvme_completion_poll_status status;
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2016-02-08 23:06:31 +00:00
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struct spdk_nvme_intel_log_page_directory *log_page_directory;
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2016-01-06 05:43:33 +00:00
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2016-08-12 17:24:34 +00:00
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log_page_directory = spdk_zmalloc(sizeof(struct spdk_nvme_intel_log_page_directory),
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64, &phys_addr);
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2016-01-06 05:43:33 +00:00
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if (log_page_directory == NULL) {
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2016-08-12 16:03:40 +00:00
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SPDK_ERRLOG("could not allocate log_page_directory\n");
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2016-06-14 22:17:33 +00:00
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return -ENXIO;
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2016-01-06 05:43:33 +00:00
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}
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status.done = false;
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2016-02-10 18:26:12 +00:00
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spdk_nvme_ctrlr_cmd_get_log_page(ctrlr, SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY, SPDK_NVME_GLOBAL_NS_TAG,
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log_page_directory, sizeof(struct spdk_nvme_intel_log_page_directory),
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nvme_completion_poll_cb,
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&status);
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2016-01-06 05:43:33 +00:00
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while (status.done == false) {
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2016-02-29 21:56:53 +00:00
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spdk_nvme_qpair_process_completions(&ctrlr->adminq, 0);
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2016-01-06 05:43:33 +00:00
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}
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2016-02-09 18:06:48 +00:00
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if (spdk_nvme_cpl_is_error(&status.cpl)) {
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2016-08-12 17:24:34 +00:00
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spdk_free(log_page_directory);
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2016-08-12 16:03:40 +00:00
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SPDK_ERRLOG("nvme_ctrlr_cmd_get_log_page failed!\n");
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2016-06-14 22:17:33 +00:00
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return -ENXIO;
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2016-01-06 05:43:33 +00:00
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}
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nvme_ctrlr_construct_intel_support_log_page_list(ctrlr, log_page_directory);
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2016-08-12 17:24:34 +00:00
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spdk_free(log_page_directory);
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2016-01-06 05:43:33 +00:00
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return 0;
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}
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static void
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2016-02-10 18:26:12 +00:00
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nvme_ctrlr_set_supported_log_pages(struct spdk_nvme_ctrlr *ctrlr)
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2016-01-06 05:43:33 +00:00
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{
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2016-01-15 20:21:18 +00:00
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memset(ctrlr->log_page_supported, 0, sizeof(ctrlr->log_page_supported));
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/* Mandatory pages */
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2016-02-09 18:06:48 +00:00
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ctrlr->log_page_supported[SPDK_NVME_LOG_ERROR] = true;
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ctrlr->log_page_supported[SPDK_NVME_LOG_HEALTH_INFORMATION] = true;
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ctrlr->log_page_supported[SPDK_NVME_LOG_FIRMWARE_SLOT] = true;
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2016-01-06 05:43:33 +00:00
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if (ctrlr->cdata.lpa.celp) {
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2016-02-09 18:06:48 +00:00
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ctrlr->log_page_supported[SPDK_NVME_LOG_COMMAND_EFFECTS_LOG] = true;
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2016-01-06 05:43:33 +00:00
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}
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2016-02-08 21:08:06 +00:00
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if (ctrlr->cdata.vid == SPDK_PCI_VID_INTEL) {
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2016-01-06 05:43:33 +00:00
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nvme_ctrlr_set_intel_support_log_pages(ctrlr);
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}
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}
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2016-01-25 05:04:23 +00:00
|
|
|
static void
|
2016-02-10 18:26:12 +00:00
|
|
|
nvme_ctrlr_set_intel_supported_features(struct spdk_nvme_ctrlr *ctrlr)
|
2016-01-25 05:04:23 +00:00
|
|
|
{
|
2016-02-08 23:06:31 +00:00
|
|
|
ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_MAX_LBA] = true;
|
|
|
|
ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_NATIVE_MAX_LBA] = true;
|
|
|
|
ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_POWER_GOVERNOR_SETTING] = true;
|
|
|
|
ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_SMBUS_ADDRESS] = true;
|
|
|
|
ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_LED_PATTERN] = true;
|
|
|
|
ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_RESET_TIMED_WORKLOAD_COUNTERS] = true;
|
|
|
|
ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_LATENCY_TRACKING] = true;
|
2016-01-25 05:04:23 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2016-02-10 18:26:12 +00:00
|
|
|
nvme_ctrlr_set_supported_features(struct spdk_nvme_ctrlr *ctrlr)
|
2016-01-25 05:04:23 +00:00
|
|
|
{
|
|
|
|
memset(ctrlr->feature_supported, 0, sizeof(ctrlr->feature_supported));
|
|
|
|
/* Mandatory features */
|
2016-02-09 18:06:48 +00:00
|
|
|
ctrlr->feature_supported[SPDK_NVME_FEAT_ARBITRATION] = true;
|
|
|
|
ctrlr->feature_supported[SPDK_NVME_FEAT_POWER_MANAGEMENT] = true;
|
|
|
|
ctrlr->feature_supported[SPDK_NVME_FEAT_TEMPERATURE_THRESHOLD] = true;
|
|
|
|
ctrlr->feature_supported[SPDK_NVME_FEAT_ERROR_RECOVERY] = true;
|
|
|
|
ctrlr->feature_supported[SPDK_NVME_FEAT_NUMBER_OF_QUEUES] = true;
|
|
|
|
ctrlr->feature_supported[SPDK_NVME_FEAT_INTERRUPT_COALESCING] = true;
|
|
|
|
ctrlr->feature_supported[SPDK_NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION] = true;
|
|
|
|
ctrlr->feature_supported[SPDK_NVME_FEAT_WRITE_ATOMICITY] = true;
|
|
|
|
ctrlr->feature_supported[SPDK_NVME_FEAT_ASYNC_EVENT_CONFIGURATION] = true;
|
2016-01-25 05:04:23 +00:00
|
|
|
/* Optional features */
|
|
|
|
if (ctrlr->cdata.vwc.present) {
|
2016-02-09 18:06:48 +00:00
|
|
|
ctrlr->feature_supported[SPDK_NVME_FEAT_VOLATILE_WRITE_CACHE] = true;
|
2016-01-25 05:04:23 +00:00
|
|
|
}
|
|
|
|
if (ctrlr->cdata.apsta.supported) {
|
2016-02-09 18:06:48 +00:00
|
|
|
ctrlr->feature_supported[SPDK_NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION] = true;
|
2016-01-25 05:04:23 +00:00
|
|
|
}
|
|
|
|
if (ctrlr->cdata.hmpre) {
|
2016-02-09 18:06:48 +00:00
|
|
|
ctrlr->feature_supported[SPDK_NVME_FEAT_HOST_MEM_BUFFER] = true;
|
2016-01-25 05:04:23 +00:00
|
|
|
}
|
2016-02-08 21:08:06 +00:00
|
|
|
if (ctrlr->cdata.vid == SPDK_PCI_VID_INTEL) {
|
2016-01-25 05:04:23 +00:00
|
|
|
nvme_ctrlr_set_intel_supported_features(ctrlr);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-09-21 15:52:41 +00:00
|
|
|
static int
|
2016-02-10 18:26:12 +00:00
|
|
|
nvme_ctrlr_construct_admin_qpair(struct spdk_nvme_ctrlr *ctrlr)
|
2015-09-21 15:52:41 +00:00
|
|
|
{
|
2015-09-22 17:12:00 +00:00
|
|
|
return nvme_qpair_construct(&ctrlr->adminq,
|
|
|
|
0, /* qpair ID */
|
|
|
|
NVME_ADMIN_ENTRIES,
|
|
|
|
ctrlr);
|
2015-09-21 15:52:41 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2016-02-10 18:26:12 +00:00
|
|
|
nvme_ctrlr_fail(struct spdk_nvme_ctrlr *ctrlr)
|
2015-09-21 15:52:41 +00:00
|
|
|
{
|
2016-10-18 16:49:07 +00:00
|
|
|
struct spdk_nvme_qpair *qpair;
|
2015-09-21 15:52:41 +00:00
|
|
|
|
|
|
|
ctrlr->is_failed = true;
|
|
|
|
nvme_qpair_fail(&ctrlr->adminq);
|
2016-10-18 16:49:07 +00:00
|
|
|
TAILQ_FOREACH(qpair, &ctrlr->active_io_qpairs, tailq) {
|
|
|
|
nvme_qpair_fail(qpair);
|
2015-09-21 15:52:41 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2016-02-10 18:26:12 +00:00
|
|
|
nvme_ctrlr_shutdown(struct spdk_nvme_ctrlr *ctrlr)
|
2015-09-21 15:52:41 +00:00
|
|
|
{
|
2016-02-09 18:06:48 +00:00
|
|
|
union spdk_nvme_cc_register cc;
|
|
|
|
union spdk_nvme_csts_register csts;
|
2015-09-21 15:52:41 +00:00
|
|
|
int ms_waited = 0;
|
|
|
|
|
2016-10-13 00:00:54 +00:00
|
|
|
if (nvme_ctrlr_get_cc(ctrlr, &cc)) {
|
|
|
|
SPDK_TRACELOG(SPDK_TRACE_NVME, "get_cc() failed\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
cc.bits.shn = SPDK_NVME_SHN_NORMAL;
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-10-13 00:00:54 +00:00
|
|
|
if (nvme_ctrlr_set_cc(ctrlr, &cc)) {
|
|
|
|
SPDK_TRACELOG(SPDK_TRACE_NVME, "set_cc() failed\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2015-09-21 15:52:41 +00:00
|
|
|
/*
|
|
|
|
* The NVMe spec does not define a timeout period
|
|
|
|
* for shutdown notification, so we just pick
|
|
|
|
* 5 seconds as a reasonable amount of time to
|
|
|
|
* wait before proceeding.
|
|
|
|
*/
|
2016-10-13 00:00:54 +00:00
|
|
|
do {
|
|
|
|
if (nvme_ctrlr_get_csts(ctrlr, &csts)) {
|
|
|
|
SPDK_TRACELOG(SPDK_TRACE_NVME, "get_csts() failed\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (csts.bits.shst == SPDK_NVME_SHST_COMPLETE) {
|
|
|
|
SPDK_TRACELOG(SPDK_TRACE_NVME, "shutdown complete\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2015-09-21 15:52:41 +00:00
|
|
|
nvme_delay(1000);
|
2016-10-13 00:00:54 +00:00
|
|
|
ms_waited++;
|
|
|
|
} while (ms_waited < 5000);
|
|
|
|
|
|
|
|
SPDK_ERRLOG("did not shutdown within 5 seconds\n");
|
2015-09-21 15:52:41 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2016-02-10 18:26:12 +00:00
|
|
|
nvme_ctrlr_enable(struct spdk_nvme_ctrlr *ctrlr)
|
2015-09-21 15:52:41 +00:00
|
|
|
{
|
2016-02-09 18:06:48 +00:00
|
|
|
union spdk_nvme_cc_register cc;
|
|
|
|
union spdk_nvme_aqa_register aqa;
|
2016-07-06 22:41:59 +00:00
|
|
|
union spdk_nvme_cap_register cap;
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-10-13 00:00:54 +00:00
|
|
|
if (nvme_ctrlr_get_cap(ctrlr, &cap)) {
|
|
|
|
SPDK_TRACELOG(SPDK_TRACE_NVME, "get_cap() failed\n");
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (nvme_ctrlr_get_cc(ctrlr, &cc)) {
|
|
|
|
SPDK_TRACELOG(SPDK_TRACE_NVME, "get_cc() failed\n");
|
|
|
|
return -EIO;
|
|
|
|
}
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-02-23 23:36:13 +00:00
|
|
|
if (cc.bits.en != 0) {
|
2016-08-12 16:03:40 +00:00
|
|
|
SPDK_ERRLOG("%s called with CC.EN = 1\n", __func__);
|
2016-06-14 22:17:33 +00:00
|
|
|
return -EINVAL;
|
2015-09-21 15:52:41 +00:00
|
|
|
}
|
|
|
|
|
2016-10-13 00:00:54 +00:00
|
|
|
if (nvme_ctrlr_set_asq(ctrlr, ctrlr->adminq.cmd_bus_addr)) {
|
|
|
|
SPDK_TRACELOG(SPDK_TRACE_NVME, "set_asq() failed\n");
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (nvme_ctrlr_set_acq(ctrlr, ctrlr->adminq.cpl_bus_addr)) {
|
|
|
|
SPDK_TRACELOG(SPDK_TRACE_NVME, "set_acq() failed\n");
|
|
|
|
return -EIO;
|
|
|
|
}
|
2015-09-21 15:52:41 +00:00
|
|
|
|
|
|
|
aqa.raw = 0;
|
|
|
|
/* acqs and asqs are 0-based. */
|
|
|
|
aqa.bits.acqs = ctrlr->adminq.num_entries - 1;
|
|
|
|
aqa.bits.asqs = ctrlr->adminq.num_entries - 1;
|
2016-10-13 00:00:54 +00:00
|
|
|
|
|
|
|
if (nvme_ctrlr_set_aqa(ctrlr, &aqa)) {
|
|
|
|
SPDK_TRACELOG(SPDK_TRACE_NVME, "set_aqa() failed\n");
|
|
|
|
return -EIO;
|
|
|
|
}
|
2015-09-21 15:52:41 +00:00
|
|
|
|
|
|
|
cc.bits.en = 1;
|
|
|
|
cc.bits.css = 0;
|
|
|
|
cc.bits.shn = 0;
|
|
|
|
cc.bits.iosqes = 6; /* SQ entry size == 64 == 2^6 */
|
|
|
|
cc.bits.iocqes = 4; /* CQ entry size == 16 == 2^4 */
|
|
|
|
|
|
|
|
/* Page size is 2 ^ (12 + mps). */
|
|
|
|
cc.bits.mps = nvme_u32log2(PAGE_SIZE) - 12;
|
|
|
|
|
2016-06-14 07:19:38 +00:00
|
|
|
switch (ctrlr->opts.arb_mechanism) {
|
|
|
|
case SPDK_NVME_CC_AMS_RR:
|
|
|
|
break;
|
|
|
|
case SPDK_NVME_CC_AMS_WRR:
|
2016-07-06 22:41:59 +00:00
|
|
|
if (SPDK_NVME_CAP_AMS_WRR & cap.bits.ams) {
|
2016-06-14 07:19:38 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
return -EINVAL;
|
|
|
|
case SPDK_NVME_CC_AMS_VS:
|
2016-07-06 22:41:59 +00:00
|
|
|
if (SPDK_NVME_CAP_AMS_VS & cap.bits.ams) {
|
2016-06-14 07:19:38 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
return -EINVAL;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
cc.bits.ams = ctrlr->opts.arb_mechanism;
|
|
|
|
|
2016-10-13 00:00:54 +00:00
|
|
|
if (nvme_ctrlr_set_cc(ctrlr, &cc)) {
|
|
|
|
SPDK_TRACELOG(SPDK_TRACE_NVME, "set_cc() failed\n");
|
|
|
|
return -EIO;
|
|
|
|
}
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-02-23 23:36:13 +00:00
|
|
|
return 0;
|
2015-09-21 15:52:41 +00:00
|
|
|
}
|
|
|
|
|
2016-02-23 23:36:13 +00:00
|
|
|
static void
|
|
|
|
nvme_ctrlr_set_state(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state,
|
|
|
|
uint64_t timeout_in_ms)
|
2015-09-21 15:52:41 +00:00
|
|
|
{
|
2016-02-23 23:36:13 +00:00
|
|
|
ctrlr->state = state;
|
|
|
|
if (timeout_in_ms == NVME_TIMEOUT_INFINITE) {
|
|
|
|
ctrlr->state_timeout_tsc = NVME_TIMEOUT_INFINITE;
|
2015-09-21 15:52:41 +00:00
|
|
|
} else {
|
2016-08-12 17:24:34 +00:00
|
|
|
ctrlr->state_timeout_tsc = spdk_get_ticks() + (timeout_in_ms * spdk_get_ticks_hz()) / 1000;
|
2015-09-21 15:52:41 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
2016-02-10 18:26:12 +00:00
|
|
|
spdk_nvme_ctrlr_reset(struct spdk_nvme_ctrlr *ctrlr)
|
2015-09-21 15:52:41 +00:00
|
|
|
{
|
2016-02-23 23:36:13 +00:00
|
|
|
int rc = 0;
|
2016-02-29 21:19:02 +00:00
|
|
|
struct spdk_nvme_qpair *qpair;
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-08-08 17:03:52 +00:00
|
|
|
pthread_mutex_lock(&ctrlr->ctrlr_lock);
|
2015-09-21 15:52:41 +00:00
|
|
|
|
|
|
|
if (ctrlr->is_resetting || ctrlr->is_failed) {
|
|
|
|
/*
|
|
|
|
* Controller is already resetting or has failed. Return
|
|
|
|
* immediately since there is no need to kick off another
|
|
|
|
* reset in these cases.
|
|
|
|
*/
|
2016-08-08 17:03:52 +00:00
|
|
|
pthread_mutex_unlock(&ctrlr->ctrlr_lock);
|
2015-09-21 15:52:41 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-11-03 00:51:32 +00:00
|
|
|
ctrlr->is_resetting = true;
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-08-12 16:03:40 +00:00
|
|
|
SPDK_NOTICELOG("resetting controller\n");
|
2016-02-23 23:36:13 +00:00
|
|
|
|
|
|
|
/* Disable all queues before disabling the controller hardware. */
|
|
|
|
nvme_qpair_disable(&ctrlr->adminq);
|
2016-10-18 16:49:07 +00:00
|
|
|
TAILQ_FOREACH(qpair, &ctrlr->active_io_qpairs, tailq) {
|
|
|
|
nvme_qpair_disable(qpair);
|
2016-02-23 23:36:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Set the state back to INIT to cause a full hardware reset. */
|
|
|
|
nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, NVME_TIMEOUT_INFINITE);
|
|
|
|
|
|
|
|
while (ctrlr->state != NVME_CTRLR_STATE_READY) {
|
|
|
|
if (nvme_ctrlr_process_init(ctrlr) != 0) {
|
2016-08-12 16:03:40 +00:00
|
|
|
SPDK_ERRLOG("%s: controller reinitialization failed\n", __func__);
|
2016-02-23 23:36:13 +00:00
|
|
|
nvme_ctrlr_fail(ctrlr);
|
|
|
|
rc = -1;
|
|
|
|
break;
|
|
|
|
}
|
2015-09-21 15:52:41 +00:00
|
|
|
}
|
|
|
|
|
2016-02-29 21:19:02 +00:00
|
|
|
if (!ctrlr->is_failed) {
|
|
|
|
/* Reinitialize qpairs */
|
|
|
|
TAILQ_FOREACH(qpair, &ctrlr->active_io_qpairs, tailq) {
|
2016-10-18 16:49:07 +00:00
|
|
|
if (ctrlr->transport->ctrlr_reinit_io_qpair(ctrlr, qpair) != 0) {
|
2016-02-29 21:19:02 +00:00
|
|
|
nvme_ctrlr_fail(ctrlr);
|
|
|
|
rc = -1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-11-03 00:51:32 +00:00
|
|
|
ctrlr->is_resetting = false;
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-08-08 17:03:52 +00:00
|
|
|
pthread_mutex_unlock(&ctrlr->ctrlr_lock);
|
2015-09-21 15:52:41 +00:00
|
|
|
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2016-02-10 18:26:12 +00:00
|
|
|
nvme_ctrlr_identify(struct spdk_nvme_ctrlr *ctrlr)
|
2015-09-21 15:52:41 +00:00
|
|
|
{
|
|
|
|
struct nvme_completion_poll_status status;
|
2016-02-29 21:33:50 +00:00
|
|
|
int rc;
|
2015-09-21 15:52:41 +00:00
|
|
|
|
|
|
|
status.done = false;
|
2016-02-29 21:33:50 +00:00
|
|
|
rc = nvme_ctrlr_cmd_identify_controller(ctrlr, &ctrlr->cdata,
|
|
|
|
nvme_completion_poll_cb, &status);
|
|
|
|
if (rc != 0) {
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
2015-09-21 15:52:41 +00:00
|
|
|
while (status.done == false) {
|
2016-02-29 21:56:53 +00:00
|
|
|
spdk_nvme_qpair_process_completions(&ctrlr->adminq, 0);
|
2015-09-21 15:52:41 +00:00
|
|
|
}
|
2016-02-09 18:06:48 +00:00
|
|
|
if (spdk_nvme_cpl_is_error(&status.cpl)) {
|
2016-08-12 16:03:40 +00:00
|
|
|
SPDK_ERRLOG("nvme_identify_controller failed!\n");
|
2016-06-14 22:17:33 +00:00
|
|
|
return -ENXIO;
|
2015-09-21 15:52:41 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Use MDTS to ensure our default max_xfer_size doesn't exceed what the
|
|
|
|
* controller supports.
|
|
|
|
*/
|
2016-08-26 00:48:15 +00:00
|
|
|
ctrlr->max_xfer_size = NVME_MAX_XFER_SIZE;
|
2015-09-21 15:52:41 +00:00
|
|
|
if (ctrlr->cdata.mdts > 0) {
|
|
|
|
ctrlr->max_xfer_size = nvme_min(ctrlr->max_xfer_size,
|
|
|
|
ctrlr->min_page_size * (1 << (ctrlr->cdata.mdts)));
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2016-02-10 18:26:12 +00:00
|
|
|
nvme_ctrlr_set_num_qpairs(struct spdk_nvme_ctrlr *ctrlr)
|
2015-09-21 15:52:41 +00:00
|
|
|
{
|
|
|
|
struct nvme_completion_poll_status status;
|
|
|
|
int cq_allocated, sq_allocated;
|
2016-02-29 21:33:50 +00:00
|
|
|
int rc;
|
2016-10-18 16:49:07 +00:00
|
|
|
uint32_t i;
|
2015-09-21 15:52:41 +00:00
|
|
|
|
|
|
|
status.done = false;
|
|
|
|
|
2016-03-23 23:33:20 +00:00
|
|
|
if (ctrlr->opts.num_io_queues > SPDK_NVME_MAX_IO_QUEUES) {
|
2016-08-12 16:03:40 +00:00
|
|
|
SPDK_NOTICELOG("Limiting requested num_io_queues %u to max %d\n",
|
|
|
|
ctrlr->opts.num_io_queues, SPDK_NVME_MAX_IO_QUEUES);
|
2016-03-23 23:33:20 +00:00
|
|
|
ctrlr->opts.num_io_queues = SPDK_NVME_MAX_IO_QUEUES;
|
|
|
|
} else if (ctrlr->opts.num_io_queues < 1) {
|
2016-08-12 16:03:40 +00:00
|
|
|
SPDK_NOTICELOG("Requested num_io_queues 0, increasing to 1\n");
|
2016-03-23 23:33:20 +00:00
|
|
|
ctrlr->opts.num_io_queues = 1;
|
|
|
|
}
|
|
|
|
|
2016-03-07 17:36:17 +00:00
|
|
|
rc = nvme_ctrlr_cmd_set_num_queues(ctrlr, ctrlr->opts.num_io_queues,
|
2016-02-29 21:33:50 +00:00
|
|
|
nvme_completion_poll_cb, &status);
|
|
|
|
if (rc != 0) {
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
2015-09-21 15:52:41 +00:00
|
|
|
while (status.done == false) {
|
2016-02-29 21:56:53 +00:00
|
|
|
spdk_nvme_qpair_process_completions(&ctrlr->adminq, 0);
|
2015-09-21 15:52:41 +00:00
|
|
|
}
|
2016-02-09 18:06:48 +00:00
|
|
|
if (spdk_nvme_cpl_is_error(&status.cpl)) {
|
2016-08-12 16:03:40 +00:00
|
|
|
SPDK_ERRLOG("nvme_set_num_queues failed!\n");
|
2016-06-14 22:17:33 +00:00
|
|
|
return -ENXIO;
|
2015-09-21 15:52:41 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Data in cdw0 is 0-based.
|
|
|
|
* Lower 16-bits indicate number of submission queues allocated.
|
|
|
|
* Upper 16-bits indicate number of completion queues allocated.
|
|
|
|
*/
|
|
|
|
sq_allocated = (status.cpl.cdw0 & 0xFFFF) + 1;
|
|
|
|
cq_allocated = (status.cpl.cdw0 >> 16) + 1;
|
|
|
|
|
2016-03-07 17:36:17 +00:00
|
|
|
ctrlr->opts.num_io_queues = nvme_min(sq_allocated, cq_allocated);
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-10-18 16:49:07 +00:00
|
|
|
ctrlr->free_io_qids = spdk_bit_array_create(ctrlr->opts.num_io_queues + 1);
|
|
|
|
if (ctrlr->free_io_qids == NULL) {
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Initialize list of free I/O queue IDs. QID 0 is the admin queue. */
|
|
|
|
spdk_bit_array_clear(ctrlr->free_io_qids, 0);
|
|
|
|
for (i = 1; i <= ctrlr->opts.num_io_queues; i++) {
|
|
|
|
spdk_bit_array_set(ctrlr->free_io_qids, i);
|
|
|
|
}
|
|
|
|
|
2015-09-21 15:52:41 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2016-02-10 18:26:12 +00:00
|
|
|
nvme_ctrlr_destruct_namespaces(struct spdk_nvme_ctrlr *ctrlr)
|
2015-09-21 15:52:41 +00:00
|
|
|
{
|
|
|
|
if (ctrlr->ns) {
|
|
|
|
uint32_t i, num_ns = ctrlr->num_ns;
|
|
|
|
|
|
|
|
for (i = 0; i < num_ns; i++) {
|
|
|
|
nvme_ns_destruct(&ctrlr->ns[i]);
|
|
|
|
}
|
|
|
|
|
2016-08-12 17:24:34 +00:00
|
|
|
spdk_free(ctrlr->ns);
|
2015-09-21 15:52:41 +00:00
|
|
|
ctrlr->ns = NULL;
|
|
|
|
ctrlr->num_ns = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ctrlr->nsdata) {
|
2016-08-12 17:24:34 +00:00
|
|
|
spdk_free(ctrlr->nsdata);
|
2015-09-21 15:52:41 +00:00
|
|
|
ctrlr->nsdata = NULL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2016-02-10 18:26:12 +00:00
|
|
|
nvme_ctrlr_construct_namespaces(struct spdk_nvme_ctrlr *ctrlr)
|
2015-09-21 15:52:41 +00:00
|
|
|
{
|
|
|
|
uint32_t i, nn = ctrlr->cdata.nn;
|
|
|
|
uint64_t phys_addr = 0;
|
|
|
|
|
|
|
|
if (nn == 0) {
|
2016-08-12 16:03:40 +00:00
|
|
|
SPDK_ERRLOG("controller has 0 namespaces\n");
|
2015-09-21 15:52:41 +00:00
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* ctrlr->num_ns may be 0 (startup) or a different number of namespaces (reset),
|
|
|
|
* so check if we need to reallocate.
|
|
|
|
*/
|
|
|
|
if (nn != ctrlr->num_ns) {
|
|
|
|
nvme_ctrlr_destruct_namespaces(ctrlr);
|
|
|
|
|
2016-08-12 17:24:34 +00:00
|
|
|
ctrlr->ns = spdk_zmalloc(nn * sizeof(struct spdk_nvme_ns), 64,
|
|
|
|
&phys_addr);
|
2015-09-21 15:52:41 +00:00
|
|
|
if (ctrlr->ns == NULL) {
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
2016-08-12 17:24:34 +00:00
|
|
|
ctrlr->nsdata = spdk_zmalloc(nn * sizeof(struct spdk_nvme_ns_data), 64,
|
|
|
|
&phys_addr);
|
2015-09-21 15:52:41 +00:00
|
|
|
if (ctrlr->nsdata == NULL) {
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
ctrlr->num_ns = nn;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < nn; i++) {
|
2016-02-10 18:26:12 +00:00
|
|
|
struct spdk_nvme_ns *ns = &ctrlr->ns[i];
|
2015-09-21 15:52:41 +00:00
|
|
|
uint32_t nsid = i + 1;
|
|
|
|
|
|
|
|
if (nvme_ns_construct(ns, nsid, ctrlr) != 0) {
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
fail:
|
|
|
|
nvme_ctrlr_destruct_namespaces(ctrlr);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2016-02-09 18:06:48 +00:00
|
|
|
nvme_ctrlr_async_event_cb(void *arg, const struct spdk_nvme_cpl *cpl)
|
2015-09-21 15:52:41 +00:00
|
|
|
{
|
|
|
|
struct nvme_async_event_request *aer = arg;
|
2016-02-10 18:26:12 +00:00
|
|
|
struct spdk_nvme_ctrlr *ctrlr = aer->ctrlr;
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
if (cpl->status.sc == SPDK_NVME_SC_ABORTED_SQ_DELETION) {
|
2015-09-21 15:52:41 +00:00
|
|
|
/*
|
|
|
|
* This is simulated when controller is being shut down, to
|
|
|
|
* effectively abort outstanding asynchronous event requests
|
|
|
|
* and make sure all memory is freed. Do not repost the
|
|
|
|
* request in this case.
|
|
|
|
*/
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ctrlr->aer_cb_fn != NULL) {
|
|
|
|
ctrlr->aer_cb_fn(ctrlr->aer_cb_arg, cpl);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Repost another asynchronous event request to replace the one
|
|
|
|
* that just completed.
|
|
|
|
*/
|
2016-01-06 20:45:25 +00:00
|
|
|
if (nvme_ctrlr_construct_and_submit_aer(ctrlr, aer)) {
|
|
|
|
/*
|
|
|
|
* We can't do anything to recover from a failure here,
|
|
|
|
* so just print a warning message and leave the AER unsubmitted.
|
|
|
|
*/
|
2016-08-12 16:03:40 +00:00
|
|
|
SPDK_ERRLOG("resubmitting AER failed!\n");
|
2016-01-06 20:45:25 +00:00
|
|
|
}
|
2015-09-21 15:52:41 +00:00
|
|
|
}
|
|
|
|
|
2016-01-06 20:45:25 +00:00
|
|
|
static int
|
2016-02-10 18:26:12 +00:00
|
|
|
nvme_ctrlr_construct_and_submit_aer(struct spdk_nvme_ctrlr *ctrlr,
|
2015-09-21 15:52:41 +00:00
|
|
|
struct nvme_async_event_request *aer)
|
|
|
|
{
|
|
|
|
struct nvme_request *req;
|
|
|
|
|
|
|
|
aer->ctrlr = ctrlr;
|
2016-01-22 23:56:20 +00:00
|
|
|
req = nvme_allocate_request_null(nvme_ctrlr_async_event_cb, aer);
|
2015-09-21 15:52:41 +00:00
|
|
|
aer->req = req;
|
2016-01-06 20:45:25 +00:00
|
|
|
if (req == NULL) {
|
|
|
|
return -1;
|
|
|
|
}
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
req->cmd.opc = SPDK_NVME_OPC_ASYNC_EVENT_REQUEST;
|
2016-03-08 22:16:09 +00:00
|
|
|
return nvme_ctrlr_submit_admin_request(ctrlr, req);
|
2015-09-21 15:52:41 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2016-02-10 18:26:12 +00:00
|
|
|
nvme_ctrlr_configure_aer(struct spdk_nvme_ctrlr *ctrlr)
|
2015-09-21 15:52:41 +00:00
|
|
|
{
|
2016-02-09 18:06:48 +00:00
|
|
|
union spdk_nvme_critical_warning_state state;
|
2015-09-21 15:52:41 +00:00
|
|
|
struct nvme_async_event_request *aer;
|
|
|
|
uint32_t i;
|
|
|
|
struct nvme_completion_poll_status status;
|
2016-02-29 21:33:50 +00:00
|
|
|
int rc;
|
2015-09-21 15:52:41 +00:00
|
|
|
|
|
|
|
status.done = false;
|
|
|
|
|
|
|
|
state.raw = 0xFF;
|
|
|
|
state.bits.reserved = 0;
|
2016-02-29 21:33:50 +00:00
|
|
|
rc = nvme_ctrlr_cmd_set_async_event_config(ctrlr, state, nvme_completion_poll_cb, &status);
|
|
|
|
if (rc != 0) {
|
|
|
|
return rc;
|
|
|
|
}
|
2015-09-21 15:52:41 +00:00
|
|
|
|
|
|
|
while (status.done == false) {
|
2016-02-29 21:56:53 +00:00
|
|
|
spdk_nvme_qpair_process_completions(&ctrlr->adminq, 0);
|
2015-09-21 15:52:41 +00:00
|
|
|
}
|
2016-02-09 18:06:48 +00:00
|
|
|
if (spdk_nvme_cpl_is_error(&status.cpl)) {
|
2016-08-12 16:03:40 +00:00
|
|
|
SPDK_ERRLOG("nvme_ctrlr_cmd_set_async_event_config failed!\n");
|
2016-06-14 22:17:33 +00:00
|
|
|
return -ENXIO;
|
2015-09-21 15:52:41 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* aerl is a zero-based value, so we need to add 1 here. */
|
|
|
|
ctrlr->num_aers = nvme_min(NVME_MAX_ASYNC_EVENTS, (ctrlr->cdata.aerl + 1));
|
|
|
|
|
|
|
|
for (i = 0; i < ctrlr->num_aers; i++) {
|
|
|
|
aer = &ctrlr->aer[i];
|
2016-01-06 20:45:25 +00:00
|
|
|
if (nvme_ctrlr_construct_and_submit_aer(ctrlr, aer)) {
|
2016-08-12 16:03:40 +00:00
|
|
|
SPDK_ERRLOG("nvme_ctrlr_construct_and_submit_aer failed!\n");
|
2016-01-06 20:45:25 +00:00
|
|
|
return -1;
|
|
|
|
}
|
2015-09-21 15:52:41 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-02-23 23:36:13 +00:00
|
|
|
/**
|
|
|
|
* This function will be called repeatedly during initialization until the controller is ready.
|
|
|
|
*/
|
2015-09-21 15:52:41 +00:00
|
|
|
int
|
2016-02-23 23:36:13 +00:00
|
|
|
nvme_ctrlr_process_init(struct spdk_nvme_ctrlr *ctrlr)
|
2015-09-21 15:52:41 +00:00
|
|
|
{
|
2016-02-23 23:36:13 +00:00
|
|
|
union spdk_nvme_cc_register cc;
|
|
|
|
union spdk_nvme_csts_register csts;
|
2016-07-06 22:41:59 +00:00
|
|
|
union spdk_nvme_cap_register cap;
|
2016-02-23 23:36:13 +00:00
|
|
|
uint32_t ready_timeout_in_ms;
|
|
|
|
int rc;
|
|
|
|
|
2016-10-13 00:00:54 +00:00
|
|
|
if (nvme_ctrlr_get_cc(ctrlr, &cc) ||
|
|
|
|
nvme_ctrlr_get_csts(ctrlr, &csts) ||
|
|
|
|
nvme_ctrlr_get_cap(ctrlr, &cap)) {
|
|
|
|
SPDK_TRACELOG(SPDK_TRACE_NVME, "get registers failed\n");
|
|
|
|
nvme_ctrlr_fail(ctrlr);
|
|
|
|
return -EIO;
|
|
|
|
}
|
2016-02-23 23:36:13 +00:00
|
|
|
|
2016-07-06 22:41:59 +00:00
|
|
|
ready_timeout_in_ms = 500 * cap.bits.to;
|
2016-02-23 23:36:13 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Check if the current initialization step is done or has timed out.
|
|
|
|
*/
|
|
|
|
switch (ctrlr->state) {
|
|
|
|
case NVME_CTRLR_STATE_INIT:
|
|
|
|
/* Begin the hardware initialization by making sure the controller is disabled. */
|
|
|
|
if (cc.bits.en) {
|
|
|
|
/*
|
|
|
|
* Controller is currently enabled. We need to disable it to cause a reset.
|
|
|
|
*
|
|
|
|
* If CC.EN = 1 && CSTS.RDY = 0, the controller is in the process of becoming ready.
|
|
|
|
* Wait for the ready bit to be 1 before disabling the controller.
|
|
|
|
*/
|
|
|
|
if (csts.bits.rdy == 0) {
|
|
|
|
nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1, ready_timeout_in_ms);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* CC.EN = 1 && CSTS.RDY == 1, so we can immediately disable the controller. */
|
|
|
|
cc.bits.en = 0;
|
2016-10-13 00:00:54 +00:00
|
|
|
if (nvme_ctrlr_set_cc(ctrlr, &cc)) {
|
|
|
|
SPDK_TRACELOG(SPDK_TRACE_NVME, "set_cc() failed\n");
|
|
|
|
nvme_ctrlr_fail(ctrlr);
|
|
|
|
return -EIO;
|
|
|
|
}
|
2016-02-23 23:36:13 +00:00
|
|
|
nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0, ready_timeout_in_ms);
|
|
|
|
return 0;
|
|
|
|
} else {
|
2016-04-08 16:13:10 +00:00
|
|
|
if (csts.bits.rdy == 1) {
|
|
|
|
/*
|
|
|
|
* Controller is in the process of shutting down.
|
|
|
|
* We need to wait for RDY to become 0.
|
|
|
|
*/
|
|
|
|
nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0, ready_timeout_in_ms);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-02-23 23:36:13 +00:00
|
|
|
/*
|
|
|
|
* Controller is currently disabled. We can jump straight to enabling it.
|
|
|
|
*/
|
2016-06-21 20:37:15 +00:00
|
|
|
rc = nvme_ctrlr_enable(ctrlr);
|
2016-02-23 23:36:13 +00:00
|
|
|
nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1, ready_timeout_in_ms);
|
2016-06-21 20:37:15 +00:00
|
|
|
return rc;
|
2016-02-23 23:36:13 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1:
|
|
|
|
if (csts.bits.rdy == 1) {
|
|
|
|
/* CC.EN = 1 && CSTS.RDY = 1, so we can set CC.EN = 0 now. */
|
|
|
|
cc.bits.en = 0;
|
2016-10-13 00:00:54 +00:00
|
|
|
if (nvme_ctrlr_set_cc(ctrlr, &cc)) {
|
|
|
|
SPDK_TRACELOG(SPDK_TRACE_NVME, "set_cc() failed\n");
|
|
|
|
nvme_ctrlr_fail(ctrlr);
|
|
|
|
return -EIO;
|
|
|
|
}
|
2016-02-23 23:36:13 +00:00
|
|
|
nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0, ready_timeout_in_ms);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0:
|
|
|
|
if (csts.bits.rdy == 0) {
|
|
|
|
/* CC.EN = 0 && CSTS.RDY = 0, so we can enable the controller now. */
|
2016-06-21 20:37:15 +00:00
|
|
|
rc = nvme_ctrlr_enable(ctrlr);
|
2016-02-23 23:36:13 +00:00
|
|
|
nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1, ready_timeout_in_ms);
|
2016-06-21 20:37:15 +00:00
|
|
|
return rc;
|
2016-02-23 23:36:13 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1:
|
|
|
|
if (csts.bits.rdy == 1) {
|
|
|
|
/*
|
|
|
|
* The controller has been enabled.
|
|
|
|
* Perform the rest of initialization in nvme_ctrlr_start() serially.
|
|
|
|
*/
|
|
|
|
rc = nvme_ctrlr_start(ctrlr);
|
|
|
|
nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READY, NVME_TIMEOUT_INFINITE);
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
2016-08-08 20:55:27 +00:00
|
|
|
assert(0);
|
2016-02-23 23:36:13 +00:00
|
|
|
nvme_ctrlr_fail(ctrlr);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ctrlr->state_timeout_tsc != NVME_TIMEOUT_INFINITE &&
|
2016-08-12 17:24:34 +00:00
|
|
|
spdk_get_ticks() > ctrlr->state_timeout_tsc) {
|
2016-08-12 16:03:40 +00:00
|
|
|
SPDK_ERRLOG("Initialization timed out in state %d\n", ctrlr->state);
|
2016-02-23 23:36:13 +00:00
|
|
|
nvme_ctrlr_fail(ctrlr);
|
2015-09-21 15:52:41 +00:00
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2016-02-23 23:36:13 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
nvme_ctrlr_start(struct spdk_nvme_ctrlr *ctrlr)
|
|
|
|
{
|
2016-10-13 22:23:55 +00:00
|
|
|
ctrlr->transport->qpair_reset(&ctrlr->adminq);
|
2015-09-21 15:52:41 +00:00
|
|
|
|
|
|
|
nvme_qpair_enable(&ctrlr->adminq);
|
|
|
|
|
|
|
|
if (nvme_ctrlr_identify(ctrlr) != 0) {
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (nvme_ctrlr_set_num_qpairs(ctrlr) != 0) {
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (nvme_ctrlr_construct_namespaces(ctrlr) != 0) {
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (nvme_ctrlr_configure_aer(ctrlr) != 0) {
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2016-01-06 05:43:33 +00:00
|
|
|
nvme_ctrlr_set_supported_log_pages(ctrlr);
|
2016-01-25 05:04:23 +00:00
|
|
|
nvme_ctrlr_set_supported_features(ctrlr);
|
2016-03-01 02:50:31 +00:00
|
|
|
|
|
|
|
if (ctrlr->cdata.sgls.supported) {
|
|
|
|
ctrlr->flags |= SPDK_NVME_CTRLR_SGL_SUPPORTED;
|
|
|
|
}
|
|
|
|
|
2015-09-21 15:52:41 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-08-08 17:03:52 +00:00
|
|
|
static inline int
|
|
|
|
pthread_mutex_init_recursive(pthread_mutex_t *mtx)
|
|
|
|
{
|
|
|
|
pthread_mutexattr_t attr;
|
|
|
|
int rc = 0;
|
|
|
|
|
|
|
|
if (pthread_mutexattr_init(&attr)) {
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
if (pthread_mutexattr_settype(&attr, PTHREAD_MUTEX_RECURSIVE) ||
|
|
|
|
pthread_mutex_init(mtx, &attr)) {
|
|
|
|
rc = -1;
|
|
|
|
}
|
|
|
|
pthread_mutexattr_destroy(&attr);
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
2015-09-21 15:52:41 +00:00
|
|
|
int
|
2016-10-18 19:50:43 +00:00
|
|
|
nvme_ctrlr_construct(struct spdk_nvme_ctrlr *ctrlr)
|
2015-09-21 15:52:41 +00:00
|
|
|
{
|
2016-07-06 22:41:59 +00:00
|
|
|
union spdk_nvme_cap_register cap;
|
2015-09-21 15:52:41 +00:00
|
|
|
int rc;
|
|
|
|
|
2016-02-23 23:36:13 +00:00
|
|
|
nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, NVME_TIMEOUT_INFINITE);
|
2016-05-05 01:41:16 +00:00
|
|
|
ctrlr->flags = 0;
|
2016-10-18 16:49:07 +00:00
|
|
|
ctrlr->free_io_qids = NULL;
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-10-13 00:00:54 +00:00
|
|
|
if (nvme_ctrlr_get_cap(ctrlr, &cap)) {
|
|
|
|
SPDK_TRACELOG(SPDK_TRACE_NVME, "get_cap() failed\n");
|
|
|
|
return -EIO;
|
|
|
|
}
|
2015-09-21 15:52:41 +00:00
|
|
|
|
2016-07-06 22:41:59 +00:00
|
|
|
ctrlr->min_page_size = 1 << (12 + cap.bits.mpsmin);
|
2015-09-21 15:52:41 +00:00
|
|
|
|
|
|
|
rc = nvme_ctrlr_construct_admin_qpair(ctrlr);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
2015-11-03 00:51:32 +00:00
|
|
|
ctrlr->is_resetting = false;
|
2015-09-21 15:52:41 +00:00
|
|
|
ctrlr->is_failed = false;
|
|
|
|
|
2016-02-29 21:19:02 +00:00
|
|
|
TAILQ_INIT(&ctrlr->active_io_qpairs);
|
|
|
|
|
2016-08-08 17:03:52 +00:00
|
|
|
pthread_mutex_init_recursive(&ctrlr->ctrlr_lock);
|
2015-09-21 15:52:41 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2016-02-10 18:26:12 +00:00
|
|
|
nvme_ctrlr_destruct(struct spdk_nvme_ctrlr *ctrlr)
|
2015-09-21 15:52:41 +00:00
|
|
|
{
|
2016-04-08 22:22:46 +00:00
|
|
|
while (!TAILQ_EMPTY(&ctrlr->active_io_qpairs)) {
|
|
|
|
struct spdk_nvme_qpair *qpair = TAILQ_FIRST(&ctrlr->active_io_qpairs);
|
|
|
|
|
|
|
|
spdk_nvme_ctrlr_free_io_qpair(qpair);
|
2016-10-18 16:49:07 +00:00
|
|
|
nvme_qpair_destroy(qpair);
|
2016-04-08 22:22:46 +00:00
|
|
|
}
|
|
|
|
|
2015-09-21 15:52:41 +00:00
|
|
|
nvme_ctrlr_shutdown(ctrlr);
|
|
|
|
|
|
|
|
nvme_ctrlr_destruct_namespaces(ctrlr);
|
|
|
|
|
2016-10-18 16:49:07 +00:00
|
|
|
spdk_bit_array_free(&ctrlr->free_io_qids);
|
2015-09-21 15:52:41 +00:00
|
|
|
|
|
|
|
nvme_qpair_destroy(&ctrlr->adminq);
|
|
|
|
|
2016-08-08 17:03:52 +00:00
|
|
|
pthread_mutex_destroy(&ctrlr->ctrlr_lock);
|
2016-10-13 23:08:22 +00:00
|
|
|
|
|
|
|
ctrlr->transport->ctrlr_destruct(ctrlr);
|
2015-09-21 15:52:41 +00:00
|
|
|
}
|
|
|
|
|
2016-03-08 22:16:09 +00:00
|
|
|
int
|
2016-02-10 18:26:12 +00:00
|
|
|
nvme_ctrlr_submit_admin_request(struct spdk_nvme_ctrlr *ctrlr,
|
2015-09-21 15:52:41 +00:00
|
|
|
struct nvme_request *req)
|
|
|
|
{
|
2016-03-08 22:16:09 +00:00
|
|
|
return nvme_qpair_submit_request(&ctrlr->adminq, req);
|
2015-09-21 15:52:41 +00:00
|
|
|
}
|
|
|
|
|
2016-01-11 16:10:02 +00:00
|
|
|
int32_t
|
2016-02-10 18:26:12 +00:00
|
|
|
spdk_nvme_ctrlr_process_admin_completions(struct spdk_nvme_ctrlr *ctrlr)
|
2015-09-21 15:52:41 +00:00
|
|
|
{
|
2016-01-11 16:10:02 +00:00
|
|
|
int32_t num_completions;
|
|
|
|
|
2016-08-08 17:03:52 +00:00
|
|
|
pthread_mutex_lock(&ctrlr->ctrlr_lock);
|
2016-02-29 21:56:53 +00:00
|
|
|
num_completions = spdk_nvme_qpair_process_completions(&ctrlr->adminq, 0);
|
2016-08-08 17:03:52 +00:00
|
|
|
pthread_mutex_unlock(&ctrlr->ctrlr_lock);
|
2016-01-11 16:10:02 +00:00
|
|
|
|
|
|
|
return num_completions;
|
2015-09-21 15:52:41 +00:00
|
|
|
}
|
|
|
|
|
2016-02-09 18:06:48 +00:00
|
|
|
const struct spdk_nvme_ctrlr_data *
|
2016-02-10 18:26:12 +00:00
|
|
|
spdk_nvme_ctrlr_get_data(struct spdk_nvme_ctrlr *ctrlr)
|
2015-09-21 15:52:41 +00:00
|
|
|
{
|
|
|
|
return &ctrlr->cdata;
|
|
|
|
}
|
|
|
|
|
2016-07-06 21:55:28 +00:00
|
|
|
union spdk_nvme_cap_register spdk_nvme_ctrlr_get_regs_cap(struct spdk_nvme_ctrlr *ctrlr)
|
|
|
|
{
|
|
|
|
union spdk_nvme_cap_register cap;
|
|
|
|
|
2016-10-13 00:00:54 +00:00
|
|
|
if (nvme_ctrlr_get_cap(ctrlr, &cap)) {
|
|
|
|
cap.raw = 0;
|
|
|
|
}
|
2016-07-06 21:55:28 +00:00
|
|
|
return cap;
|
|
|
|
}
|
|
|
|
|
|
|
|
union spdk_nvme_vs_register spdk_nvme_ctrlr_get_regs_vs(struct spdk_nvme_ctrlr *ctrlr)
|
|
|
|
{
|
|
|
|
union spdk_nvme_vs_register vs;
|
|
|
|
|
2016-10-13 00:00:54 +00:00
|
|
|
if (nvme_ctrlr_get_vs(ctrlr, &vs)) {
|
|
|
|
vs.raw = 0;
|
|
|
|
}
|
2016-07-06 21:55:28 +00:00
|
|
|
return vs;
|
|
|
|
}
|
|
|
|
|
2015-09-21 15:52:41 +00:00
|
|
|
uint32_t
|
2016-02-10 18:26:12 +00:00
|
|
|
spdk_nvme_ctrlr_get_num_ns(struct spdk_nvme_ctrlr *ctrlr)
|
2015-09-21 15:52:41 +00:00
|
|
|
{
|
|
|
|
return ctrlr->num_ns;
|
|
|
|
}
|
|
|
|
|
2016-02-10 18:26:12 +00:00
|
|
|
struct spdk_nvme_ns *
|
|
|
|
spdk_nvme_ctrlr_get_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t ns_id)
|
2015-09-21 15:52:41 +00:00
|
|
|
{
|
|
|
|
if (ns_id < 1 || ns_id > ctrlr->num_ns) {
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return &ctrlr->ns[ns_id - 1];
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2016-02-10 18:26:12 +00:00
|
|
|
spdk_nvme_ctrlr_register_aer_callback(struct spdk_nvme_ctrlr *ctrlr,
|
|
|
|
spdk_nvme_aer_cb aer_cb_fn,
|
|
|
|
void *aer_cb_arg)
|
2015-09-21 15:52:41 +00:00
|
|
|
{
|
|
|
|
ctrlr->aer_cb_fn = aer_cb_fn;
|
|
|
|
ctrlr->aer_cb_arg = aer_cb_arg;
|
|
|
|
}
|
2016-01-06 05:43:33 +00:00
|
|
|
|
|
|
|
bool
|
2016-02-10 18:26:12 +00:00
|
|
|
spdk_nvme_ctrlr_is_log_page_supported(struct spdk_nvme_ctrlr *ctrlr, uint8_t log_page)
|
2016-01-06 05:43:33 +00:00
|
|
|
{
|
2016-01-15 20:21:18 +00:00
|
|
|
/* No bounds check necessary, since log_page is uint8_t and log_page_supported has 256 entries */
|
|
|
|
SPDK_STATIC_ASSERT(sizeof(ctrlr->log_page_supported) == 256, "log_page_supported size mismatch");
|
|
|
|
return ctrlr->log_page_supported[log_page];
|
2016-01-06 05:43:33 +00:00
|
|
|
}
|
2016-01-25 05:04:23 +00:00
|
|
|
|
|
|
|
bool
|
2016-02-10 18:26:12 +00:00
|
|
|
spdk_nvme_ctrlr_is_feature_supported(struct spdk_nvme_ctrlr *ctrlr, uint8_t feature_code)
|
2016-01-25 05:04:23 +00:00
|
|
|
{
|
|
|
|
/* No bounds check necessary, since feature_code is uint8_t and feature_supported has 256 entries */
|
|
|
|
SPDK_STATIC_ASSERT(sizeof(ctrlr->feature_supported) == 256, "feature_supported size mismatch");
|
|
|
|
return ctrlr->feature_supported[feature_code];
|
|
|
|
}
|
2016-02-25 03:44:44 +00:00
|
|
|
|
|
|
|
int
|
|
|
|
spdk_nvme_ctrlr_attach_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid,
|
|
|
|
struct spdk_nvme_ctrlr_list *payload)
|
|
|
|
{
|
|
|
|
struct nvme_completion_poll_status status;
|
|
|
|
int res;
|
|
|
|
|
|
|
|
status.done = false;
|
|
|
|
res = nvme_ctrlr_cmd_attach_ns(ctrlr, nsid, payload,
|
|
|
|
nvme_completion_poll_cb, &status);
|
|
|
|
if (res)
|
|
|
|
return res;
|
|
|
|
while (status.done == false) {
|
2016-08-08 17:03:52 +00:00
|
|
|
pthread_mutex_lock(&ctrlr->ctrlr_lock);
|
2016-02-25 03:44:44 +00:00
|
|
|
spdk_nvme_qpair_process_completions(&ctrlr->adminq, 0);
|
2016-08-08 17:03:52 +00:00
|
|
|
pthread_mutex_unlock(&ctrlr->ctrlr_lock);
|
2016-02-25 03:44:44 +00:00
|
|
|
}
|
|
|
|
if (spdk_nvme_cpl_is_error(&status.cpl)) {
|
2016-08-12 16:03:40 +00:00
|
|
|
SPDK_ERRLOG("spdk_nvme_ctrlr_attach_ns failed!\n");
|
2016-06-14 22:17:33 +00:00
|
|
|
return -ENXIO;
|
2016-02-25 03:44:44 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return spdk_nvme_ctrlr_reset(ctrlr);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
spdk_nvme_ctrlr_detach_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid,
|
|
|
|
struct spdk_nvme_ctrlr_list *payload)
|
|
|
|
{
|
|
|
|
struct nvme_completion_poll_status status;
|
|
|
|
int res;
|
|
|
|
|
|
|
|
status.done = false;
|
|
|
|
res = nvme_ctrlr_cmd_detach_ns(ctrlr, nsid, payload,
|
|
|
|
nvme_completion_poll_cb, &status);
|
|
|
|
if (res)
|
|
|
|
return res;
|
|
|
|
while (status.done == false) {
|
2016-08-08 17:03:52 +00:00
|
|
|
pthread_mutex_lock(&ctrlr->ctrlr_lock);
|
2016-02-25 03:44:44 +00:00
|
|
|
spdk_nvme_qpair_process_completions(&ctrlr->adminq, 0);
|
2016-08-08 17:03:52 +00:00
|
|
|
pthread_mutex_unlock(&ctrlr->ctrlr_lock);
|
2016-02-25 03:44:44 +00:00
|
|
|
}
|
|
|
|
if (spdk_nvme_cpl_is_error(&status.cpl)) {
|
2016-08-12 16:03:40 +00:00
|
|
|
SPDK_ERRLOG("spdk_nvme_ctrlr_detach_ns failed!\n");
|
2016-06-14 22:17:33 +00:00
|
|
|
return -ENXIO;
|
2016-02-25 03:44:44 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return spdk_nvme_ctrlr_reset(ctrlr);
|
|
|
|
}
|
|
|
|
|
2016-05-19 00:05:38 +00:00
|
|
|
uint32_t
|
2016-02-25 03:44:44 +00:00
|
|
|
spdk_nvme_ctrlr_create_ns(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_ns_data *payload)
|
|
|
|
{
|
|
|
|
struct nvme_completion_poll_status status;
|
|
|
|
int res;
|
|
|
|
|
|
|
|
status.done = false;
|
|
|
|
res = nvme_ctrlr_cmd_create_ns(ctrlr, payload, nvme_completion_poll_cb, &status);
|
|
|
|
if (res)
|
2016-05-19 00:05:38 +00:00
|
|
|
return 0;
|
2016-02-25 03:44:44 +00:00
|
|
|
while (status.done == false) {
|
2016-08-08 17:03:52 +00:00
|
|
|
pthread_mutex_lock(&ctrlr->ctrlr_lock);
|
2016-02-25 03:44:44 +00:00
|
|
|
spdk_nvme_qpair_process_completions(&ctrlr->adminq, 0);
|
2016-08-08 17:03:52 +00:00
|
|
|
pthread_mutex_unlock(&ctrlr->ctrlr_lock);
|
2016-02-25 03:44:44 +00:00
|
|
|
}
|
|
|
|
if (spdk_nvme_cpl_is_error(&status.cpl)) {
|
2016-08-12 16:03:40 +00:00
|
|
|
SPDK_ERRLOG("spdk_nvme_ctrlr_create_ns failed!\n");
|
2016-05-19 00:05:38 +00:00
|
|
|
return 0;
|
2016-02-25 03:44:44 +00:00
|
|
|
}
|
|
|
|
|
2016-05-19 00:05:38 +00:00
|
|
|
res = spdk_nvme_ctrlr_reset(ctrlr);
|
|
|
|
if (res) {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Return the namespace ID that was created */
|
|
|
|
return status.cpl.cdw0;
|
2016-02-25 03:44:44 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
spdk_nvme_ctrlr_delete_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid)
|
|
|
|
{
|
|
|
|
struct nvme_completion_poll_status status;
|
|
|
|
int res;
|
|
|
|
|
|
|
|
status.done = false;
|
|
|
|
res = nvme_ctrlr_cmd_delete_ns(ctrlr, nsid, nvme_completion_poll_cb, &status);
|
|
|
|
if (res)
|
|
|
|
return res;
|
|
|
|
while (status.done == false) {
|
2016-08-08 17:03:52 +00:00
|
|
|
pthread_mutex_lock(&ctrlr->ctrlr_lock);
|
2016-02-25 03:44:44 +00:00
|
|
|
spdk_nvme_qpair_process_completions(&ctrlr->adminq, 0);
|
2016-08-08 17:03:52 +00:00
|
|
|
pthread_mutex_unlock(&ctrlr->ctrlr_lock);
|
2016-02-25 03:44:44 +00:00
|
|
|
}
|
|
|
|
if (spdk_nvme_cpl_is_error(&status.cpl)) {
|
2016-08-12 16:03:40 +00:00
|
|
|
SPDK_ERRLOG("spdk_nvme_ctrlr_delete_ns failed!\n");
|
2016-06-14 22:17:33 +00:00
|
|
|
return -ENXIO;
|
2016-02-25 03:44:44 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return spdk_nvme_ctrlr_reset(ctrlr);
|
|
|
|
}
|
2016-03-07 06:29:50 +00:00
|
|
|
|
|
|
|
int
|
|
|
|
spdk_nvme_ctrlr_format(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid,
|
|
|
|
struct spdk_nvme_format *format)
|
|
|
|
{
|
|
|
|
struct nvme_completion_poll_status status;
|
|
|
|
int res;
|
|
|
|
|
|
|
|
status.done = false;
|
|
|
|
res = nvme_ctrlr_cmd_format(ctrlr, nsid, format, nvme_completion_poll_cb,
|
|
|
|
&status);
|
|
|
|
if (res)
|
|
|
|
return res;
|
|
|
|
while (status.done == false) {
|
2016-08-08 17:03:52 +00:00
|
|
|
pthread_mutex_lock(&ctrlr->ctrlr_lock);
|
2016-03-07 06:29:50 +00:00
|
|
|
spdk_nvme_qpair_process_completions(&ctrlr->adminq, 0);
|
2016-08-08 17:03:52 +00:00
|
|
|
pthread_mutex_unlock(&ctrlr->ctrlr_lock);
|
2016-03-07 06:29:50 +00:00
|
|
|
}
|
|
|
|
if (spdk_nvme_cpl_is_error(&status.cpl)) {
|
2016-08-12 16:03:40 +00:00
|
|
|
SPDK_ERRLOG("spdk_nvme_ctrlr_format failed!\n");
|
2016-06-14 22:17:33 +00:00
|
|
|
return -ENXIO;
|
2016-03-07 06:29:50 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return spdk_nvme_ctrlr_reset(ctrlr);
|
|
|
|
}
|
2016-05-03 05:18:39 +00:00
|
|
|
|
|
|
|
int
|
|
|
|
spdk_nvme_ctrlr_update_firmware(struct spdk_nvme_ctrlr *ctrlr, void *payload, uint32_t size,
|
|
|
|
int slot)
|
|
|
|
{
|
|
|
|
struct spdk_nvme_fw_commit fw_commit;
|
|
|
|
struct nvme_completion_poll_status status;
|
|
|
|
int res;
|
|
|
|
unsigned int size_remaining;
|
|
|
|
unsigned int offset;
|
|
|
|
unsigned int transfer;
|
|
|
|
void *p;
|
|
|
|
|
|
|
|
if (size % 4) {
|
2016-08-12 16:03:40 +00:00
|
|
|
SPDK_ERRLOG("spdk_nvme_ctrlr_update_firmware invalid size!\n");
|
2016-05-03 05:18:39 +00:00
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Firmware download */
|
|
|
|
size_remaining = size;
|
|
|
|
offset = 0;
|
|
|
|
p = payload;
|
|
|
|
|
|
|
|
while (size_remaining > 0) {
|
|
|
|
transfer = nvme_min(size_remaining, ctrlr->min_page_size);
|
|
|
|
status.done = false;
|
|
|
|
|
|
|
|
res = nvme_ctrlr_cmd_fw_image_download(ctrlr, transfer, offset, p,
|
|
|
|
nvme_completion_poll_cb,
|
|
|
|
&status);
|
|
|
|
if (res)
|
|
|
|
return res;
|
|
|
|
|
|
|
|
while (status.done == false) {
|
2016-08-08 17:03:52 +00:00
|
|
|
pthread_mutex_lock(&ctrlr->ctrlr_lock);
|
2016-05-03 05:18:39 +00:00
|
|
|
spdk_nvme_qpair_process_completions(&ctrlr->adminq, 0);
|
2016-08-08 17:03:52 +00:00
|
|
|
pthread_mutex_unlock(&ctrlr->ctrlr_lock);
|
2016-05-03 05:18:39 +00:00
|
|
|
}
|
|
|
|
if (spdk_nvme_cpl_is_error(&status.cpl)) {
|
2016-08-12 16:03:40 +00:00
|
|
|
SPDK_ERRLOG("spdk_nvme_ctrlr_fw_image_download failed!\n");
|
2016-06-14 22:17:33 +00:00
|
|
|
return -ENXIO;
|
2016-05-03 05:18:39 +00:00
|
|
|
}
|
|
|
|
p += transfer;
|
|
|
|
offset += transfer;
|
|
|
|
size_remaining -= transfer;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Firmware commit */
|
|
|
|
memset(&fw_commit, 0, sizeof(struct spdk_nvme_fw_commit));
|
|
|
|
fw_commit.fs = slot;
|
|
|
|
fw_commit.ca = SPDK_NVME_FW_COMMIT_REPLACE_IMG;
|
|
|
|
|
|
|
|
status.done = false;
|
|
|
|
|
|
|
|
res = nvme_ctrlr_cmd_fw_commit(ctrlr, &fw_commit, nvme_completion_poll_cb,
|
|
|
|
&status);
|
|
|
|
if (res)
|
|
|
|
return res;
|
|
|
|
|
|
|
|
while (status.done == false) {
|
2016-08-08 17:03:52 +00:00
|
|
|
pthread_mutex_lock(&ctrlr->ctrlr_lock);
|
2016-05-03 05:18:39 +00:00
|
|
|
spdk_nvme_qpair_process_completions(&ctrlr->adminq, 0);
|
2016-08-08 17:03:52 +00:00
|
|
|
pthread_mutex_unlock(&ctrlr->ctrlr_lock);
|
2016-05-03 05:18:39 +00:00
|
|
|
}
|
|
|
|
if (spdk_nvme_cpl_is_error(&status.cpl)) {
|
2016-08-12 16:03:40 +00:00
|
|
|
SPDK_ERRLOG("nvme_ctrlr_cmd_fw_commit failed!\n");
|
2016-06-14 22:17:33 +00:00
|
|
|
return -ENXIO;
|
2016-05-03 05:18:39 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return spdk_nvme_ctrlr_reset(ctrlr);
|
|
|
|
}
|