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barrier.h: fix load fence on armv8

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the weak memory ordering on armv8 can be implemented using

dsb ld

see
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0802b/DMB.html

Change-Id: I4db34b87fa659967109adc688cad784018cedaae
Signed-off-by: Kefu Chai <tchaikov@gmail.com>
Reviewed-on: https://review.gerrithub.io/430767
Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
Chandler-Test-Pool: SPDK Automated Test System <sys_sgsw@intel.com>
Reviewed-by: Jim Harris <james.r.harris@intel.com>
Reviewed-by: Ben Walker <benjamin.walker@intel.com>
Reviewed-on: https://review.gerrithub.io/435672
Reviewed-by: Shuhei Matsumoto <shuhei.matsumoto.xt@hitachi.com>
This commit is contained in:
Kefu Chai 2018-10-26 20:53:21 +08:00 committed by Jim Harris
parent f14c7b3b06
commit 2aa7396d82
1 changed files with 1 additions and 1 deletions
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2
include/spdk/barrier.h
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@ -64,7 +64,7 @@ extern "C" {
#ifdef __PPC64__
#define spdk_rmb() __asm volatile("sync" ::: "memory")
#elif defined(__aarch64__)
#define spdk_rmb() __asm volatile("dsb lt" ::: "memory")
#define spdk_rmb() __asm volatile("dsb ld" ::: "memory")
#elif defined(__i386__) || defined(__x86_64__)
#define spdk_rmb() __asm volatile("lfence" ::: "memory")
#else