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nvme/pcie: add memory barrier process completions

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Because ppc64 has less strict memory ordering behaviour
than x86 we need to introduce a memory barrier when
polling for completions due to possible reordering
of tracker and cpl access.

Change-Id: Id17116c38b2ba69154c175c539fc97c60897deb0
Signed-off-by: Jonas Pfefferle <jpf@zurich.ibm.com>
Reviewed-on: https://review.gerrithub.io/383728
Tested-by: SPDK Automated Test System <sys_sgsw@intel.com>
Reviewed-by: Jim Harris <james.r.harris@intel.com>
Reviewed-by: Daniel Verkamp <daniel.verkamp@intel.com>
This commit is contained in:
PepperJo 2017-10-12 15:07:23 +02:00 committed by Jim Harris
parent 7bcb08c02b
commit 4382434855
1 changed files with 8 additions and 0 deletions
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8
lib/nvme/nvme_pcie.c
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@ -1907,6 +1907,14 @@ nvme_pcie_qpair_process_completions(struct spdk_nvme_qpair *qpair, uint32_t max_
if (cpl->status.p != pqpair->phase)
break;
#ifdef __PPC64__
/*
* This memory barrier prevents reordering of:
* - load after store from/to tr
* - load after load cpl phase and cpl cid
*/
spdk_mb();
#endif
tr = &pqpair->tr[cpl->cid];