ioat, nvme: factor out MMIO helper functions
NVMe doesn't require the specific 64-bit MMIO ordering on 32-bit platforms performed in spdk_mmio_read_8(), but it doesn't hurt. We have to pick one of the two possible orderings, so pick the one required by I/OAT. Change-Id: I2b909d64d0c077b797d0f64a11d78d1ecc55eec7 Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com>
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Daniel Verkamp
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25cad6ffcf
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91
include/spdk/mmio.h
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91
include/spdk/mmio.h
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@ -0,0 +1,91 @@
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/*-
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* BSD LICENSE
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*
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* Copyright(c) 2015 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef SPDK_MMIO_H
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#define SPDK_MMIO_H
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#include <inttypes.h>
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#ifdef __x86_64__
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#define SPDK_MMIO_64BIT 1 /* Can do atomic 64-bit memory read/write (over PCIe) */
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#else
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#define SPDK_MMIO_64BIT 0
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#endif
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static inline uint32_t
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spdk_mmio_read_4(const volatile uint32_t *addr)
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{
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return *addr;
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}
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static inline void
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spdk_mmio_write_4(volatile uint32_t *addr, uint32_t val)
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{
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*addr = val;
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}
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static inline uint64_t
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spdk_mmio_read_8(volatile uint64_t *addr)
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{
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uint64_t val;
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volatile uint32_t *addr32 = (volatile uint32_t *)addr;
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if (SPDK_MMIO_64BIT) {
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val = *addr;
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} else {
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/*
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* Read lower 4 bytes before upper 4 bytes.
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* This particular order is required by I/OAT.
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* If the other order is required, use a pair of spdk_mmio_read_4() calls.
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*/
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val = addr32[0];
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val |= (uint64_t)addr32[1] << 32;
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}
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return val;
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}
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static inline void
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spdk_mmio_write_8(volatile uint64_t *addr, uint64_t val)
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{
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volatile uint32_t *addr32 = (volatile uint32_t *)addr;
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if (SPDK_MMIO_64BIT) {
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*addr = val;
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} else {
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addr32[0] = (uint32_t)val;
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addr32[1] = (uint32_t)(val >> 32);
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}
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}
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#endif
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@ -116,53 +116,22 @@ ioat_pci_device_match_id(uint16_t vendor_id, uint16_t device_id)
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return false;
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}
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static uint64_t
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ioat_mmio_read_8(volatile uint64_t *addr)
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{
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uint64_t val;
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volatile uint32_t *addr32 = (volatile uint32_t *)addr;
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if (IOAT_64BIT_IO) {
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val = *addr;
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} else {
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/* Must read lower 4 bytes before upper 4 bytes. */
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val = addr32[0];
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val |= (uint64_t)addr32[1] << 32;
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}
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return val;
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}
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static void
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ioat_mmio_write_8(volatile uint64_t *addr, uint64_t val)
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{
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volatile uint32_t *addr32 = (volatile uint32_t *)addr;
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if (IOAT_64BIT_IO) {
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*addr = val;
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} else {
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addr32[0] = (uint32_t)val;
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addr32[1] = (uint32_t)(val >> 32);
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}
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}
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static uint64_t
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ioat_get_chansts(struct ioat_channel *ioat)
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{
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return ioat_mmio_read_8(&ioat->regs->chansts);
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return spdk_mmio_read_8(&ioat->regs->chansts);
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}
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static void
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ioat_write_chancmp(struct ioat_channel *ioat, uint64_t addr)
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{
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ioat_mmio_write_8(&ioat->regs->chancmp, addr);
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spdk_mmio_write_8(&ioat->regs->chancmp, addr);
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}
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static void
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ioat_write_chainaddr(struct ioat_channel *ioat, uint64_t addr)
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{
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ioat_mmio_write_8(&ioat->regs->chainaddr, addr);
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spdk_mmio_write_8(&ioat->regs->chainaddr, addr);
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}
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static inline void
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@ -44,16 +44,11 @@
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#include <inttypes.h>
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#include "spdk/queue.h"
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#include "spdk/mmio.h"
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/* Allocate 2 << 15 (32K) descriptors per channel by default. */
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#define IOAT_DEFAULT_ORDER 15
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#ifdef __x86_64__
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#define IOAT_64BIT_IO 1 /* Can do atomic 64-bit memory read/write (over PCIe) */
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#else
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#define IOAT_64BIT_IO 0
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#endif
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struct ioat_descriptor {
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ioat_callback_t callback_fn;
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void *callback_arg;
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@ -51,6 +51,7 @@
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#include "spdk/queue.h"
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#include "spdk/barrier.h"
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#include "spdk/mmio.h"
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#define NVME_MAX_PRP_LIST_ENTRIES (32)
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@ -304,32 +305,14 @@ extern struct nvme_driver g_nvme_driver;
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#define INTEL_DC_P3X00_DEVID 0x09538086
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static inline uint32_t
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_nvme_mmio_read_4(const volatile uint32_t *addr)
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{
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return *addr;
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}
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static inline void
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_nvme_mmio_write_4(volatile uint32_t *addr, uint32_t val)
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{
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*addr = val;
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}
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static inline void
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_nvme_mmio_write_8(volatile uint64_t *addr, uint64_t val)
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{
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*addr = val;
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}
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#define nvme_mmio_read_4(sc, reg) \
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_nvme_mmio_read_4(&(sc)->regs->reg)
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spdk_mmio_read_4(&(sc)->regs->reg)
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#define nvme_mmio_write_4(sc, reg, val) \
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_nvme_mmio_write_4(&(sc)->regs->reg, val)
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spdk_mmio_write_4(&(sc)->regs->reg, val)
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#define nvme_mmio_write_8(sc, reg, val) \
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_nvme_mmio_write_8(&(sc)->regs->reg, val)
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spdk_mmio_write_8(&(sc)->regs->reg, val)
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#define nvme_delay usleep
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@ -480,7 +480,7 @@ nvme_qpair_process_completions(struct nvme_qpair *qpair, uint32_t max_completion
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qpair->phase = !qpair->phase;
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}
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_nvme_mmio_write_4(qpair->cq_hdbl, qpair->cq_head);
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spdk_mmio_write_4(qpair->cq_hdbl, qpair->cq_head);
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if (max_completions > 0 && --max_completions == 0) {
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break;
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@ -635,7 +635,7 @@ nvme_qpair_submit_tracker(struct nvme_qpair *qpair, struct nvme_tracker *tr)
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}
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wmb();
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_nvme_mmio_write_4(qpair->sq_tdbl, qpair->sq_tail);
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spdk_mmio_write_4(qpair->sq_tdbl, qpair->sq_tail);
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}
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static void
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