lib/nvme: Adding support for PMR Identification
Identify application prints the PMR details if it is supported Signed-off-by: Krishna Kanth Reddy <krish.reddy@samsung.com> Change-Id: Iaba4c15e18e1402035b11a34b2defe8078855751 Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/6209 Community-CI: Broadcom CI Reviewed-by: Aleksey Marchuk <alexeymar@mellanox.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
This commit is contained in:
Krishna Kanth Reddy
Tomasz Zawadzki
parent
9529803fe0
commit
48aed8a578
@ -137,6 +137,8 @@ Change the return type of function `spdk_nbd_stop` from void to int. And update
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### nvme
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Added a new function `spdk_nvme_ctrlr_get_regs_pmrcap` to get the PMR capabilities.
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Directives support was added to the NVMe driver.
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Two async APIs `spdk_nvme_ctrlr_cmd_directive_receive` and `spdk_nvme_ctrlr_cmd_directive_send`
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@ -1074,6 +1074,7 @@ print_controller(struct spdk_nvme_ctrlr *ctrlr, const struct spdk_nvme_transport
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union spdk_nvme_cap_register cap;
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union spdk_nvme_vs_register vs;
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union spdk_nvme_cmbsz_register cmbsz;
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union spdk_nvme_pmrcap_register pmrcap;
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uint8_t str[512];
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uint32_t i, j;
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struct spdk_nvme_error_information_entry *error_entry;
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@ -1086,6 +1087,7 @@ print_controller(struct spdk_nvme_ctrlr *ctrlr, const struct spdk_nvme_transport
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cap = spdk_nvme_ctrlr_get_regs_cap(ctrlr);
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vs = spdk_nvme_ctrlr_get_regs_vs(ctrlr);
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cmbsz = spdk_nvme_ctrlr_get_regs_cmbsz(ctrlr);
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pmrcap = spdk_nvme_ctrlr_get_regs_pmrcap(ctrlr);
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if (!spdk_nvme_ctrlr_is_discovery(ctrlr)) {
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/*
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@ -1198,6 +1200,9 @@ print_controller(struct spdk_nvme_ctrlr *ctrlr, const struct spdk_nvme_transport
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(uint64_t)1 << (12 + cap.bits.mpsmin));
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printf("Memory Page Size Maximum: %" PRIu64 " bytes\n",
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(uint64_t)1 << (12 + cap.bits.mpsmax));
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printf("Persistent Memory Region: %s\n",
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cap.bits.pmrs ? "Supported" : "Not Supported");
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printf("Optional Asynchronous Events Supported\n");
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printf(" Namespace Attribute Notices: %s\n",
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cdata->oaes.ns_attribute_notices ? "Supported" : "Not Supported");
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@ -1233,6 +1238,19 @@ print_controller(struct spdk_nvme_ctrlr *ctrlr, const struct spdk_nvme_transport
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}
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printf("\n");
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printf("Persistent Memory Region Support\n");
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printf("================================\n");
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if (cap.bits.pmrs != 0) {
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printf("Supported: Yes\n");
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printf("Read data and metadata in PMR %s\n",
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pmrcap.bits.rds ? "Supported" : "Not Supported");
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printf("Write data and metadata in PMR: %s\n",
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pmrcap.bits.wds ? "Supported" : "Not Supported");
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} else {
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printf("Supported: No\n");
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}
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printf("\n");
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printf("Admin Command Set Attributes\n");
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printf("============================\n");
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printf("Security Send/Receive: %s\n",
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@ -1017,6 +1017,15 @@ union spdk_nvme_vs_register spdk_nvme_ctrlr_get_regs_vs(struct spdk_nvme_ctrlr *
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*/
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union spdk_nvme_cmbsz_register spdk_nvme_ctrlr_get_regs_cmbsz(struct spdk_nvme_ctrlr *ctrlr);
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/**
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* Get the NVMe controller PMRCAP (Persistent Memory Region Capabilities) register.
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*
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* \param ctrlr Opaque handle to NVMe controller.
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*
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* \return the NVMe controller PMRCAP (Persistent Memory Region Capabilities) register.
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*/
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union spdk_nvme_pmrcap_register spdk_nvme_ctrlr_get_regs_pmrcap(struct spdk_nvme_ctrlr *ctrlr);
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/**
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* Get the number of namespaces for the given NVMe controller.
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*
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@ -109,7 +109,10 @@ union spdk_nvme_cap_register {
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/** memory page size maximum */
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uint32_t mpsmax : 4;
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uint32_t reserved3 : 8;
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/** persistent memory region supported */
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uint32_t pmrs : 1;
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uint32_t reserved3 : 7;
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} bits;
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};
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SPDK_STATIC_ASSERT(sizeof(union spdk_nvme_cap_register) == 8, "Incorrect size");
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@ -299,6 +302,139 @@ union spdk_nvme_cmbsts_register {
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};
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SPDK_STATIC_ASSERT(sizeof(union spdk_nvme_cmbsts_register) == 4, "Incorrect size");
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union spdk_nvme_pmrcap_register {
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uint32_t raw;
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struct {
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uint32_t reserved1 : 3;
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/** read data support */
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uint32_t rds : 1;
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/** write data support */
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uint32_t wds : 1;
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/** base indicator register */
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uint32_t bir : 3;
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/**
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* persistent memory region time units
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* 00b: 500 milliseconds
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* 01b: minutes
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*/
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uint32_t pmrtu : 2;
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/** persistent memory region write barrier mechanisms */
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uint32_t pmrwbm : 4;
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uint32_t reserved2 : 2;
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/** persistent memory region timeout */
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uint32_t pmrto : 8;
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/** controller memory space supported */
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uint32_t cmss : 1;
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uint32_t reserved3 : 7;
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} bits;
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};
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SPDK_STATIC_ASSERT(sizeof(union spdk_nvme_pmrcap_register) == 4, "Incorrect size");
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union spdk_nvme_pmrctl_register {
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uint32_t raw;
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struct {
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/** enable */
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uint32_t en : 1;
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uint32_t reserved : 31;
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} bits;
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};
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SPDK_STATIC_ASSERT(sizeof(union spdk_nvme_pmrctl_register) == 4, "Incorrect size");
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union spdk_nvme_pmrsts_register {
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uint32_t raw;
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struct {
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/** err */
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uint32_t err : 8;
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/** not ready */
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uint32_t nrdy : 1;
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/**
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* health status
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* 000b: Normal Operation
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* 001b: Restore Error
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* 010b: Read Only
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* 011b: Unreliable
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*/
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uint32_t hsts : 3;
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/** controller base address invalid */
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uint32_t cbai : 1;
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uint32_t reserved : 19;
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} bits;
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};
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SPDK_STATIC_ASSERT(sizeof(union spdk_nvme_pmrsts_register) == 4, "Incorrect size");
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union spdk_nvme_pmrebs_register {
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uint32_t raw;
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struct {
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/**
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* pmr elasicity buffer size units
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* 0h: Bytes
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* 1h: 1 KiB
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* 2h: 1 MiB
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* 3h: 1 GiB
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*/
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uint32_t pmrszu : 4;
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/** read bypass behavior */
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uint32_t rbb : 1;
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uint32_t reserved : 3;
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/** pmr elasticity buffer size base */
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uint32_t pmrwbz : 24;
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} bits;
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};
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SPDK_STATIC_ASSERT(sizeof(union spdk_nvme_pmrebs_register) == 4, "Incorrect size");
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union spdk_nvme_pmrswtp_register {
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uint32_t raw;
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struct {
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/**
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* pmr sustained write throughput units
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* 0h: Bytes per second
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* 1h: 1 KiB / s
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* 2h: 1 MiB / s
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* 3h: 1 GiB / s
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*/
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uint32_t pmrswtu : 4;
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uint32_t reserved : 4;
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/** pmr sustained write throughput */
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uint32_t pmrswtv : 24;
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} bits;
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};
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SPDK_STATIC_ASSERT(sizeof(union spdk_nvme_pmrswtp_register) == 4, "Incorrect size");
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union spdk_nvme_pmrmscl_register {
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uint32_t raw;
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struct {
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uint32_t reserved1 : 1;
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/** controller memory space enable */
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uint32_t cmse : 1;
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uint32_t reserved2 : 10;
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/** controller base address */
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uint32_t cba : 20;
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} bits;
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};
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SPDK_STATIC_ASSERT(sizeof(union spdk_nvme_pmrmscl_register) == 4, "Incorrect size");
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/** Boot partition information */
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union spdk_nvme_bpinfo_register {
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uint32_t raw;
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@ -387,7 +523,29 @@ struct spdk_nvme_registers {
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/** controller memory buffer status */
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union spdk_nvme_cmbsts_register cmbsts;
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uint32_t reserved3[0x3e9];
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uint32_t reserved2[0x369];
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/** persistent memory region capabilities */
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union spdk_nvme_pmrcap_register pmrcap;
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/** persistent memory region control */
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union spdk_nvme_pmrctl_register pmrctl;
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/** persistent memory region status */
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union spdk_nvme_pmrsts_register pmrsts;
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/** persistent memory region elasticity buffer size */
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union spdk_nvme_pmrebs_register pmrebs;
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/** persistent memory region sustained write throughput */
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union spdk_nvme_pmrswtp_register pmrswtp;
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/** persistent memory region memory space control lower */
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union spdk_nvme_pmrmscl_register pmrmscl;
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uint32_t pmrmscu; /* persistent memory region memory space control upper */
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uint32_t reserved3[0x79];
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struct {
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uint32_t sq_tdbl; /* submission queue tail doorbell */
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@ -423,6 +581,20 @@ SPDK_STATIC_ASSERT(0x50 == offsetof(struct spdk_nvme_registers, cmbmsc),
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"Incorrect register offset");
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SPDK_STATIC_ASSERT(0x58 == offsetof(struct spdk_nvme_registers, cmbsts),
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"Incorrect register offset");
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SPDK_STATIC_ASSERT(0xE00 == offsetof(struct spdk_nvme_registers, pmrcap),
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"Incorrect register offset");
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SPDK_STATIC_ASSERT(0xE04 == offsetof(struct spdk_nvme_registers, pmrctl),
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"Incorrect register offset");
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SPDK_STATIC_ASSERT(0xE08 == offsetof(struct spdk_nvme_registers, pmrsts),
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"Incorrect register offset");
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SPDK_STATIC_ASSERT(0xE0C == offsetof(struct spdk_nvme_registers, pmrebs),
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"Incorrect register offset");
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SPDK_STATIC_ASSERT(0xE10 == offsetof(struct spdk_nvme_registers, pmrswtp),
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"Incorrect register offset");
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SPDK_STATIC_ASSERT(0xE14 == offsetof(struct spdk_nvme_registers, pmrmscl),
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"Incorrect register offset");
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SPDK_STATIC_ASSERT(0xE18 == offsetof(struct spdk_nvme_registers, pmrmscu),
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"Incorrect register offset");
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enum spdk_nvme_sgl_descriptor_type {
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SPDK_NVME_SGL_TYPE_DATA_BLOCK = 0x0,
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@ -91,6 +91,13 @@ nvme_ctrlr_get_cmbsz(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_cmbsz_regist
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&cmbsz->raw);
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}
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int
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nvme_ctrlr_get_pmrcap(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_pmrcap_register *pmrcap)
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{
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return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, pmrcap.raw),
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&pmrcap->raw);
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}
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static int
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nvme_ctrlr_set_nssr(struct spdk_nvme_ctrlr *ctrlr, uint32_t nssr_value)
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{
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@ -3539,6 +3546,17 @@ union spdk_nvme_cmbsz_register spdk_nvme_ctrlr_get_regs_cmbsz(struct spdk_nvme_c
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return cmbsz;
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}
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union spdk_nvme_pmrcap_register spdk_nvme_ctrlr_get_regs_pmrcap(struct spdk_nvme_ctrlr *ctrlr)
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{
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union spdk_nvme_pmrcap_register pmrcap;
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if (nvme_ctrlr_get_pmrcap(ctrlr, &pmrcap)) {
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pmrcap.raw = 0;
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}
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return pmrcap;
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}
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uint32_t
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spdk_nvme_ctrlr_get_num_ns(struct spdk_nvme_ctrlr *ctrlr)
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{
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@ -1019,6 +1019,7 @@ int nvme_ctrlr_submit_admin_request(struct spdk_nvme_ctrlr *ctrlr,
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int nvme_ctrlr_get_cap(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_cap_register *cap);
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int nvme_ctrlr_get_vs(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_vs_register *vs);
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int nvme_ctrlr_get_cmbsz(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_cmbsz_register *cmbsz);
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int nvme_ctrlr_get_pmrcap(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_pmrcap_register *pmrcap);
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bool nvme_ctrlr_multi_iocs_enabled(struct spdk_nvme_ctrlr *ctrlr);
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void nvme_ctrlr_init_cap(struct spdk_nvme_ctrlr *ctrlr, const union spdk_nvme_cap_register *cap,
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const union spdk_nvme_vs_register *vs);
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@ -41,6 +41,7 @@
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spdk_nvme_ctrlr_get_regs_cap;
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spdk_nvme_ctrlr_get_regs_vs;
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spdk_nvme_ctrlr_get_regs_cmbsz;
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spdk_nvme_ctrlr_get_regs_pmrcap;
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spdk_nvme_ctrlr_get_num_ns;
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spdk_nvme_ctrlr_get_pci_device;
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spdk_nvme_ctrlr_get_max_xfer_size;
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