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nvme: add security send/receive quirk for Intel 900P SSDs

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These SSDs set the oacs.security bit but do not actually
support OPAL.  So do not set the controller flag indicating
SECURITY_SEND_RECV support in this case.

Signed-off-by: Jim Harris <james.r.harris@intel.com>
Change-Id: I7fcfeafcc8d9439a1c53c60a1aea1801923a2ce5

Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/3156
Community-CI: Broadcom CI
Community-CI: Mellanox Build Bot
Reviewed-by: Changpeng Liu <changpeng.liu@intel.com>
Reviewed-by: Ben Walker <benjamin.walker@intel.com>
Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
This commit is contained in:
Jim Harris 2020-07-01 12:33:23 -07:00 committed by Tomasz Zawadzki
parent cd8b9455ad
commit 7ff9609f3d
3 changed files with 9 additions and 1 deletions
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2
lib/nvme/nvme_ctrlr.c
View File

@ -1355,7 +1355,7 @@ nvme_ctrlr_identify_done(void *arg, const struct spdk_nvme_cpl *cpl)
SPDK_DEBUGLOG(SPDK_LOG_NVME, "transport max_sges %u\n", ctrlr->max_sges);
}
if (ctrlr->cdata.oacs.security) {
if (ctrlr->cdata.oacs.security && !(ctrlr->quirks & NVME_QUIRK_OACS_SECURITY)) {
ctrlr->flags |= SPDK_NVME_CTRLR_SECURITY_SEND_RECV_SUPPORTED;
}

5
lib/nvme/nvme_internal.h
View File

@ -145,6 +145,11 @@ extern pid_t g_spdk_nvme_pid;
*/
#define NVME_QUIRK_MAXIMUM_PCI_ACCESS_WIDTH 0x1000
/**
* The SSD does not support OPAL even through it sets the security bit in OACS.
*/
#define NVME_QUIRK_OACS_SECURITY 0x2000
#define NVME_MAX_ASYNC_EVENTS (8)
#define NVME_MAX_ADMIN_TIMEOUT_IN_SECS (30)

3
lib/nvme/nvme_quirks.c
View File

@ -93,6 +93,9 @@ static const struct nvme_quirk nvme_quirks[] = {
{ {SPDK_PCI_VID_VMWARE, 0x07f0, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
NVME_QUIRK_SHST_COMPLETE
},
{ {SPDK_PCI_VID_INTEL, 0x2700, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
NVME_QUIRK_OACS_SECURITY
},
{ {0x0000, 0x0000, 0x0000, 0x0000}, 0}
};