nvme: read the capability (CAP) register asynchronously
Signed-off-by: Jim Harris <james.r.harris@intel.com> Signed-off-by: Konrad Sztyber <konrad.sztyber@intel.com> Change-Id: I685e0ca772ff7e485db42a2179a84c483ec49cdc Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/8616 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Community-CI: Broadcom CI <spdk-ci.pdl@broadcom.com> Community-CI: Mellanox Build Bot Reviewed-by: Shuhei Matsumoto <shuhei.matsumoto.xt@hitachi.com> Reviewed-by: Aleksey Marchuk <alexeymar@mellanox.com>
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@ -81,6 +81,9 @@ static void nvme_ctrlr_set_state(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_
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nvme_transport_ctrlr_get_reg_ ## sz ## _async(ctrlr, \
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offsetof(struct spdk_nvme_registers, reg), cb_fn, cb_arg)
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#define nvme_ctrlr_get_cap_async(ctrlr, cb_fn, cb_arg) \
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nvme_ctrlr_get_reg_async(ctrlr, cap, 8, cb_fn, cb_arg)
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#define nvme_ctrlr_get_vs_async(ctrlr, cb_fn, cb_arg) \
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nvme_ctrlr_get_reg_async(ctrlr, vs, 4, cb_fn, cb_arg)
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@ -1244,6 +1247,8 @@ nvme_ctrlr_state_string(enum nvme_ctrlr_state state)
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return "read vs wait for vs";
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case NVME_CTRLR_STATE_READ_CAP:
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return "read cap";
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case NVME_CTRLR_STATE_READ_CAP_WAIT_FOR_CAP:
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return "read cap wait for cap";
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case NVME_CTRLR_STATE_CHECK_EN:
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return "check en";
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case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1:
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@ -3387,6 +3392,22 @@ nvme_ctrlr_process_init_vs_done(void *ctx, uint64_t value, const struct spdk_nvm
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nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READ_CAP, NVME_TIMEOUT_INFINITE);
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}
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static void
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nvme_ctrlr_process_init_cap_done(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
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{
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struct spdk_nvme_ctrlr *ctrlr = ctx;
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if (spdk_nvme_cpl_is_error(cpl)) {
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NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CAP register\n");
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nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
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return;
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}
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ctrlr->cap.raw = value;
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nvme_ctrlr_init_cap(ctrlr);
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nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CHECK_EN, NVME_TIMEOUT_INFINITE);
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}
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/**
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* This function will be called repeatedly during initialization until the controller is ready.
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*/
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@ -3483,8 +3504,8 @@ nvme_ctrlr_process_init(struct spdk_nvme_ctrlr *ctrlr)
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break;
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case NVME_CTRLR_STATE_READ_CAP:
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nvme_ctrlr_init_cap(ctrlr);
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nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CHECK_EN, NVME_TIMEOUT_INFINITE);
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nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READ_CAP_WAIT_FOR_CAP, NVME_TIMEOUT_INFINITE);
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rc = nvme_ctrlr_get_cap_async(ctrlr, nvme_ctrlr_process_init_cap_done, ctrlr);
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break;
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case NVME_CTRLR_STATE_CHECK_EN:
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@ -3641,6 +3662,7 @@ nvme_ctrlr_process_init(struct spdk_nvme_ctrlr *ctrlr)
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return -1;
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case NVME_CTRLR_STATE_READ_VS_WAIT_FOR_VS:
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case NVME_CTRLR_STATE_READ_CAP_WAIT_FOR_CAP:
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case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY:
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case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_IOCS_SPECIFIC:
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case NVME_CTRLR_STATE_WAIT_FOR_GET_ZNS_CMD_EFFECTS_LOG:
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@ -3750,8 +3772,6 @@ nvme_ctrlr_construct(struct spdk_nvme_ctrlr *ctrlr)
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static void
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nvme_ctrlr_init_cap(struct spdk_nvme_ctrlr *ctrlr)
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{
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nvme_ctrlr_get_cap(ctrlr, &ctrlr->cap);
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if (ctrlr->cap.bits.ams & SPDK_NVME_CAP_AMS_WRR) {
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ctrlr->flags |= SPDK_NVME_CTRLR_WRR_SUPPORTED;
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}
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@ -573,6 +573,11 @@ enum nvme_ctrlr_state {
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*/
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NVME_CTRLR_STATE_READ_CAP,
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/**
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* Waiting for Capabilities (CAP) register to be read.
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*/
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NVME_CTRLR_STATE_READ_CAP_WAIT_FOR_CAP,
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/**
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* Check EN to prepare for controller initialization.
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*/
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