nvme: add quirk to delay checking device readiness (#56)
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@ -46,6 +46,7 @@ extern "C" {
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#define SPDK_PCI_ANY_ID 0xffff
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#define SPDK_PCI_VID_INTEL 0x8086
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#define SPDK_PCI_VID_MEMBLAZE 0x1c5f
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/**
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* PCI class code for NVMe devices.
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@ -731,6 +731,17 @@ nvme_ctrlr_process_init(struct spdk_nvme_ctrlr *ctrlr)
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uint32_t ready_timeout_in_ms;
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int rc;
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/*
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* May need to avoid accessing any register on the target controller
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* for a while. Return early without touching the FSM.
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* Check sleep_timeout_tsc > 0 for unit test.
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*/
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if ((ctrlr->sleep_timeout_tsc > 0) &&
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(spdk_get_ticks() <= ctrlr->sleep_timeout_tsc)) {
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return 0;
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}
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ctrlr->sleep_timeout_tsc = 0;
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if (nvme_ctrlr_get_cc(ctrlr, &cc) ||
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nvme_ctrlr_get_csts(ctrlr, &csts)) {
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SPDK_TRACELOG(SPDK_TRACE_NVME, "get registers failed\n");
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@ -766,6 +777,14 @@ nvme_ctrlr_process_init(struct spdk_nvme_ctrlr *ctrlr)
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return -EIO;
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}
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nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0, ready_timeout_in_ms);
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/*
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* Wait 2 secsonds before accessing PCI registers.
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* Not using sleep() to avoid blocking other controller's initialization.
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*/
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if (ctrlr->quirks & NVME_QUIRK_DELAY_BEFORE_CHK_RDY) {
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ctrlr->sleep_timeout_tsc = spdk_get_ticks() + 2 * spdk_get_ticks_hz();
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}
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return 0;
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} else {
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if (csts.bits.rdy == 1) {
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@ -70,6 +70,12 @@
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*/
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#define NVME_INTEL_QUIRK_WRITE_LATENCY 0x2
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/*
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* The controller needs a delay before starts checking the device
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* readiness, which is done by reading the NVME_CSTS_RDY bit.
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*/
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#define NVME_QUIRK_DELAY_BEFORE_CHK_RDY 0x4
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#define NVME_MAX_ASYNC_EVENTS (8)
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#define NVME_MIN_TIMEOUT_PERIOD (5)
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@ -390,6 +396,9 @@ struct spdk_nvme_ctrlr {
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struct spdk_pci_addr pci_addr;
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uint64_t quirks;
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/* Extra sleep time during controller initialization */
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uint64_t sleep_timeout_tsc;
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};
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struct nvme_driver {
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@ -45,6 +45,7 @@ static const struct nvme_quirk nvme_quirks[] = {
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{{SPDK_PCI_VID_INTEL, 0x0953, SPDK_PCI_VID_INTEL, 0x3705}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY },
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{{SPDK_PCI_VID_INTEL, 0x0953, SPDK_PCI_VID_INTEL, 0x3709}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY },
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{{SPDK_PCI_VID_INTEL, 0x0953, SPDK_PCI_VID_INTEL, 0x370a}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY },
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{{SPDK_PCI_VID_MEMBLAZE, 0x0540, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID}, NVME_QUIRK_DELAY_BEFORE_CHK_RDY },
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{{0x0000, 0x0000, 0x0000, 0x0000}, 0 }
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};
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