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barrier: add proper barrier instructions for ARM 64

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Add code to implement the write memory barrier and read/write memory
barrier for ARM 64 platforms.

Change-Id: I8b63db25ba1f70a729874ca143db13501d976676
Signed-off-by: Barry Spinney <spinney@mellanox.com>
Reviewed-on: https://review.gerrithub.io/386534
Reviewed-by: Daniel Verkamp <daniel.verkamp@intel.com>
Tested-by: SPDK Automated Test System <sys_sgsw@intel.com>
Reviewed-by: Jim Harris <james.r.harris@intel.com>
Reviewed-by: Ben Walker <benjamin.walker@intel.com>
This commit is contained in:
Barry Spinney 2017-11-09 22:18:00 +02:00 committed by Daniel Verkamp
parent 0c06e1ea89
commit dcfbafeb77
1 changed files with 4 additions and 0 deletions
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4
include/spdk/barrier.h
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@ -51,6 +51,8 @@ extern "C" {
/** Write memory barrier */
#ifdef __PPC64__
#define spdk_wmb() __asm volatile("sync" ::: "memory")
#elif defined(__aarch64__)
#define spdk_wmb() __asm volatile("dsb st" ::: "memory")
#elif defined(__i386__) || defined(__x86_64__)
#define spdk_wmb() __asm volatile("sfence" ::: "memory")
#else
@ -61,6 +63,8 @@ extern "C" {
/** Full read/write memory barrier */
#ifdef __PPC64__
#define spdk_mb() __asm volatile("sync" ::: "memory")
#elif defined(__aarch64__)
#define spdk_mb() __asm volatile("dsb sy" ::: "memory")
#elif defined(__i386__) || defined(__x86_64__)
#define spdk_mb() __asm volatile("mfence" ::: "memory")
#else