6b1e4e732d
This patch also drops support for automatically unbinding devices from the kernel - run scripts/setup.sh first. Our generic pci interface is now hidden behind include/spdk/pci.h and implemented in lib/util/pci.c. We no longer wrap the calls in nvme_impl.h or ioat_impl.h. The implementation now only uses DPDK and the libpciaccess dependency has been removed. If using a version of DPDK earlier than 16.07, enumerating devices by class code isn't available and only Intel SSDs will be discovered. DPDK 16.07 adds enumeration by class code and all NVMe devices will be correctly discovered. Change-Id: I0e8bac36b5ca57df604a2b310c47342c67dc9f3c Signed-off-by: Ben Walker <benjamin.walker@intel.com>
117 lines
4.2 KiB
C
117 lines
4.2 KiB
C
/*-
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* BSD LICENSE
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*
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* Copyright (c) Intel Corporation.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/** \file
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* PCI device ID list
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*/
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#ifndef SPDK_PCI_IDS
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#define SPDK_PCI_IDS
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#define SPDK_PCI_VID_INTEL 0x8086
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/**
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* PCI class code for NVMe devices.
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*
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* Base class code 01h: mass storage
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* Subclass code 08h: non-volatile memory
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* Programming interface 02h: NVM Express
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*/
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#define SPDK_PCI_CLASS_NVME 0x010802
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#define PCI_DEVICE_ID_INTEL_IOAT_SNB0 0x3c20
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#define PCI_DEVICE_ID_INTEL_IOAT_SNB1 0x3c21
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#define PCI_DEVICE_ID_INTEL_IOAT_SNB2 0x3c22
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#define PCI_DEVICE_ID_INTEL_IOAT_SNB3 0x3c23
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#define PCI_DEVICE_ID_INTEL_IOAT_SNB4 0x3c24
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#define PCI_DEVICE_ID_INTEL_IOAT_SNB5 0x3c25
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#define PCI_DEVICE_ID_INTEL_IOAT_SNB6 0x3c26
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#define PCI_DEVICE_ID_INTEL_IOAT_SNB7 0x3c27
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#define PCI_DEVICE_ID_INTEL_IOAT_SNB8 0x3c2e
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#define PCI_DEVICE_ID_INTEL_IOAT_SNB9 0x3c2f
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#define PCI_DEVICE_ID_INTEL_IOAT_IVB0 0x0e20
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#define PCI_DEVICE_ID_INTEL_IOAT_IVB1 0x0e21
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#define PCI_DEVICE_ID_INTEL_IOAT_IVB2 0x0e22
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#define PCI_DEVICE_ID_INTEL_IOAT_IVB3 0x0e23
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#define PCI_DEVICE_ID_INTEL_IOAT_IVB4 0x0e24
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#define PCI_DEVICE_ID_INTEL_IOAT_IVB5 0x0e25
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#define PCI_DEVICE_ID_INTEL_IOAT_IVB6 0x0e26
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#define PCI_DEVICE_ID_INTEL_IOAT_IVB7 0x0e27
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#define PCI_DEVICE_ID_INTEL_IOAT_IVB8 0x0e2e
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#define PCI_DEVICE_ID_INTEL_IOAT_IVB9 0x0e2f
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#define PCI_DEVICE_ID_INTEL_IOAT_HSW0 0x2f20
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#define PCI_DEVICE_ID_INTEL_IOAT_HSW1 0x2f21
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#define PCI_DEVICE_ID_INTEL_IOAT_HSW2 0x2f22
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#define PCI_DEVICE_ID_INTEL_IOAT_HSW3 0x2f23
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#define PCI_DEVICE_ID_INTEL_IOAT_HSW4 0x2f24
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#define PCI_DEVICE_ID_INTEL_IOAT_HSW5 0x2f25
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#define PCI_DEVICE_ID_INTEL_IOAT_HSW6 0x2f26
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#define PCI_DEVICE_ID_INTEL_IOAT_HSW7 0x2f27
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#define PCI_DEVICE_ID_INTEL_IOAT_HSW8 0x2f2e
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#define PCI_DEVICE_ID_INTEL_IOAT_HSW9 0x2f2f
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#define PCI_DEVICE_ID_INTEL_IOAT_BWD0 0x0C50
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#define PCI_DEVICE_ID_INTEL_IOAT_BWD1 0x0C51
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#define PCI_DEVICE_ID_INTEL_IOAT_BWD2 0x0C52
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#define PCI_DEVICE_ID_INTEL_IOAT_BWD3 0x0C53
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#define PCI_DEVICE_ID_INTEL_IOAT_BDXDE0 0x6f50
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#define PCI_DEVICE_ID_INTEL_IOAT_BDXDE1 0x6f51
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#define PCI_DEVICE_ID_INTEL_IOAT_BDXDE2 0x6f52
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#define PCI_DEVICE_ID_INTEL_IOAT_BDXDE3 0x6f53
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#define PCI_DEVICE_ID_INTEL_IOAT_BDX0 0x6f20
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#define PCI_DEVICE_ID_INTEL_IOAT_BDX1 0x6f21
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#define PCI_DEVICE_ID_INTEL_IOAT_BDX2 0x6f22
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#define PCI_DEVICE_ID_INTEL_IOAT_BDX3 0x6f23
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#define PCI_DEVICE_ID_INTEL_IOAT_BDX4 0x6f24
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#define PCI_DEVICE_ID_INTEL_IOAT_BDX5 0x6f25
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#define PCI_DEVICE_ID_INTEL_IOAT_BDX6 0x6f26
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#define PCI_DEVICE_ID_INTEL_IOAT_BDX7 0x6f27
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#define PCI_DEVICE_ID_INTEL_IOAT_BDX8 0x6f2e
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#define PCI_DEVICE_ID_INTEL_IOAT_BDX9 0x6f2f
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#ifdef __cplusplus
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}
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#endif
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#endif /* SPDK_PCI_IDS */
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