32e22643ef
Currently we *always* wait 2 seconds before starting controller initialization during attach. This works around an issue where some older Intel NVMe SSDs could not handle MMIO writes too soon after a PCIe FLR (which would be triggered when VFIO was enabled). After further discussion with Intel experts, we know the SSD models that exhibit this issue. So we can quirk this so that only the older SSDs incur the extra delay. Signed-off-by: Jim Harris <james.r.harris@intel.com> Change-Id: Ieb408c24f6afd5bd5147d1c87239aa20f2d13511 Reviewed-on: https://review.gerrithub.io/c/spdk/spdk/+/466064 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Reviewed-by: Shuhei Matsumoto <shuhei.matsumoto.xt@hitachi.com> Reviewed-by: Broadcom SPDK FC-NVMe CI <spdk-ci.pdl@broadcom.com>
147 lines
5.1 KiB
C
147 lines
5.1 KiB
C
/*-
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* BSD LICENSE
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*
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* Copyright (c) Intel Corporation.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "nvme_internal.h"
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struct nvme_quirk {
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struct spdk_pci_id id;
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uint64_t flags;
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};
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static const struct nvme_quirk nvme_quirks[] = {
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{ {SPDK_PCI_VID_INTEL, 0x0953, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_INTEL_QUIRK_READ_LATENCY |
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NVME_INTEL_QUIRK_WRITE_LATENCY |
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NVME_INTEL_QUIRK_STRIPING |
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NVME_QUIRK_READ_ZERO_AFTER_DEALLOCATE |
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NVME_QUIRK_DELAY_BEFORE_INIT
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},
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{ {SPDK_PCI_VID_INTEL, 0x0A53, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_INTEL_QUIRK_READ_LATENCY |
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NVME_INTEL_QUIRK_WRITE_LATENCY |
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NVME_INTEL_QUIRK_STRIPING |
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NVME_QUIRK_READ_ZERO_AFTER_DEALLOCATE |
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NVME_QUIRK_DELAY_BEFORE_INIT
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},
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{ {SPDK_PCI_VID_INTEL, 0x0A54, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_INTEL_QUIRK_READ_LATENCY |
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NVME_INTEL_QUIRK_WRITE_LATENCY |
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NVME_INTEL_QUIRK_STRIPING |
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NVME_QUIRK_READ_ZERO_AFTER_DEALLOCATE
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},
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{ {SPDK_PCI_VID_INTEL, 0x0A55, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_INTEL_QUIRK_READ_LATENCY |
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NVME_INTEL_QUIRK_WRITE_LATENCY |
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NVME_INTEL_QUIRK_STRIPING |
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NVME_QUIRK_READ_ZERO_AFTER_DEALLOCATE
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},
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{ {SPDK_PCI_VID_MEMBLAZE, 0x0540, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_QUIRK_DELAY_BEFORE_CHK_RDY
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},
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{ {SPDK_PCI_VID_SAMSUNG, 0xa821, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_QUIRK_DELAY_BEFORE_CHK_RDY
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},
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{ {SPDK_PCI_VID_SAMSUNG, 0xa822, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_QUIRK_DELAY_BEFORE_CHK_RDY
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},
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{ {SPDK_PCI_VID_VIRTUALBOX, 0x4e56, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_QUIRK_DELAY_AFTER_QUEUE_ALLOC
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},
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{ {SPDK_PCI_VID_INTEL, 0x5845, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_QUIRK_IDENTIFY_CNS |
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NVME_INTEL_QUIRK_NO_LOG_PAGES
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},
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{ {SPDK_PCI_VID_CNEXLABS, 0x1f1f, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_QUIRK_IDENTIFY_CNS |
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NVME_QUIRK_OCSSD
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},
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{ {SPDK_PCI_VID_VMWARE, 0x07f0, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_QUIRK_SHST_COMPLETE
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},
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{ {0x0000, 0x0000, 0x0000, 0x0000}, 0}
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};
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/* Compare each field. SPDK_PCI_ANY_ID in s1 matches everything */
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static bool
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pci_id_match(const struct spdk_pci_id *s1, const struct spdk_pci_id *s2)
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{
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if ((s1->vendor_id == SPDK_PCI_ANY_ID || s1->vendor_id == s2->vendor_id) &&
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(s1->device_id == SPDK_PCI_ANY_ID || s1->device_id == s2->device_id) &&
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(s1->subvendor_id == SPDK_PCI_ANY_ID || s1->subvendor_id == s2->subvendor_id) &&
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(s1->subdevice_id == SPDK_PCI_ANY_ID || s1->subdevice_id == s2->subdevice_id)) {
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return true;
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}
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return false;
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}
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uint64_t
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nvme_get_quirks(const struct spdk_pci_id *id)
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{
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const struct nvme_quirk *quirk = nvme_quirks;
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SPDK_DEBUGLOG(SPDK_LOG_NVME, "Searching for %04x:%04x [%04x:%04x]...\n",
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id->vendor_id, id->device_id,
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id->subvendor_id, id->subdevice_id);
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while (quirk->id.vendor_id) {
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if (pci_id_match(&quirk->id, id)) {
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SPDK_DEBUGLOG(SPDK_LOG_NVME, "Matched quirk %04x:%04x [%04x:%04x]:\n",
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quirk->id.vendor_id, quirk->id.device_id,
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quirk->id.subvendor_id, quirk->id.subdevice_id);
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#define PRINT_QUIRK(quirk_flag) \
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do { \
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if (quirk->flags & (quirk_flag)) { \
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SPDK_DEBUGLOG(SPDK_LOG_NVME, "Quirk enabled: %s\n", #quirk_flag); \
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} \
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} while (0)
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PRINT_QUIRK(NVME_INTEL_QUIRK_READ_LATENCY);
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PRINT_QUIRK(NVME_INTEL_QUIRK_WRITE_LATENCY);
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PRINT_QUIRK(NVME_QUIRK_DELAY_BEFORE_CHK_RDY);
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PRINT_QUIRK(NVME_INTEL_QUIRK_STRIPING);
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PRINT_QUIRK(NVME_QUIRK_DELAY_AFTER_QUEUE_ALLOC);
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PRINT_QUIRK(NVME_QUIRK_READ_ZERO_AFTER_DEALLOCATE);
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PRINT_QUIRK(NVME_QUIRK_IDENTIFY_CNS);
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PRINT_QUIRK(NVME_QUIRK_OCSSD);
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return quirk->flags;
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}
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quirk++;
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}
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SPDK_DEBUGLOG(SPDK_LOG_NVME, "No quirks found.\n");
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return 0;
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}
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