443 lines
13 KiB
C
443 lines
13 KiB
C
/*-
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* BSD LICENSE
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*
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* Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __NVME_INTERNAL_H__
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#define __NVME_INTERNAL_H__
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#include <errno.h>
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#include <stddef.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdbool.h>
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#include <string.h>
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#include <time.h>
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#include <unistd.h>
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#include <x86intrin.h>
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#include <sys/user.h>
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#include "spdk/nvme.h"
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#include "spdk/queue.h"
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#include "spdk/barrier.h"
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#define NVME_MAX_PRP_LIST_ENTRIES (32)
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/*
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* For commands requiring more than 2 PRP entries, one PRP will be
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* embedded in the command (prp1), and the rest of the PRP entries
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* will be in a list pointed to by the command (prp2). This means
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* that real max number of PRP entries we support is 32+1, which
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* results in a max xfer size of 32*PAGE_SIZE.
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*/
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#define NVME_MAX_XFER_SIZE NVME_MAX_PRP_LIST_ENTRIES * PAGE_SIZE
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#define NVME_ADMIN_TRACKERS (16)
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#define NVME_ADMIN_ENTRIES (128)
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/* min and max are defined in admin queue attributes section of spec */
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#define NVME_MIN_ADMIN_ENTRIES (2)
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#define NVME_MAX_ADMIN_ENTRIES (4096)
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/*
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* NVME_IO_ENTRIES defines the size of an I/O qpair's submission and completion
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* queues, while NVME_IO_TRACKERS defines the maximum number of I/O that we
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* will allow outstanding on an I/O qpair at any time. The only advantage in
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* having IO_ENTRIES > IO_TRACKERS is for debugging purposes - when dumping
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* the contents of the submission and completion queues, it will show a longer
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* history of data.
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*/
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#define NVME_IO_ENTRIES (256)
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#define NVME_IO_TRACKERS (128)
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#define NVME_MIN_IO_TRACKERS (4)
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#define NVME_MAX_IO_TRACKERS (1024)
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/*
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* NVME_MAX_IO_ENTRIES is not defined, since it is specified in CC.MQES
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* for each controller.
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*/
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#define NVME_MAX_ASYNC_EVENTS (8)
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#define NVME_MIN_TIMEOUT_PERIOD (5)
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#define NVME_MAX_TIMEOUT_PERIOD (120)
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/* Maximum log page size to fetch for AERs. */
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#define NVME_MAX_AER_LOG_SIZE (4096)
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struct nvme_request {
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struct nvme_command cmd;
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/**
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* Points to a parent request if part of a split request,
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* NULL otherwise.
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*/
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struct nvme_request *parent;
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union {
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void *payload;
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} u;
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uint8_t timeout;
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uint8_t retries;
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/**
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* Number of children requests still outstanding for this
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* request which was split into multiple child requests.
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*/
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uint8_t num_children;
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uint32_t payload_size;
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nvme_cb_fn_t cb_fn;
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void *cb_arg;
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STAILQ_ENTRY(nvme_request) stailq;
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/**
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* The following members should not be reordered with members
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* above. These members are only needed when splitting
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* requests which is done rarely, and the driver is careful
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* to not touch the following fields until a split operation is
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* needed, to avoid touching an extra cacheline.
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*/
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/**
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* Points to the outstanding child requests for a parent request.
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* Only valid if a request was split into multiple children
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* requests, and is not initialized for non-split requests.
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*/
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TAILQ_HEAD(, nvme_request) children;
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/**
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* Linked-list pointers for a child request in its parent's list.
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*/
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TAILQ_ENTRY(nvme_request) child_tailq;
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/**
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* Completion status for a parent request. Initialized to all 0's
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* (SUCCESS) before child requests are submitted. If a child
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* request completes with error, the error status is copied here,
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* to ensure that the parent request is also completed with error
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* status once all child requests are completed.
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*/
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struct nvme_completion parent_status;
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};
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struct nvme_completion_poll_status {
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struct nvme_completion cpl;
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bool done;
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};
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struct nvme_async_event_request {
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struct nvme_controller *ctrlr;
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struct nvme_request *req;
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struct nvme_completion cpl;
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};
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struct nvme_tracker {
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LIST_ENTRY(nvme_tracker) list;
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struct nvme_request *req;
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uint16_t cid;
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uint64_t prp_bus_addr;
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uint64_t prp[NVME_MAX_PRP_LIST_ENTRIES];
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};
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struct nvme_qpair {
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volatile uint32_t *sq_tdbl;
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volatile uint32_t *cq_hdbl;
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/**
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* Submission queue
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*/
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struct nvme_command *cmd;
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/**
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* Completion queue
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*/
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struct nvme_completion *cpl;
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LIST_HEAD(, nvme_tracker) free_tr;
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LIST_HEAD(, nvme_tracker) outstanding_tr;
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STAILQ_HEAD(, nvme_request) queued_req;
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struct nvme_tracker **act_tr;
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uint16_t id;
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uint16_t num_entries;
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uint16_t sq_tail;
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uint16_t cq_head;
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uint8_t phase;
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bool is_enabled;
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/*
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* Fields below this point should not be touched on the normal I/O happy path.
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*/
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struct nvme_controller *ctrlr;
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uint64_t cmd_bus_addr;
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uint64_t cpl_bus_addr;
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};
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struct nvme_namespace {
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struct nvme_controller *ctrlr;
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uint32_t stripe_size;
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uint32_t sector_size;
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uint32_t sectors_per_max_io;
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uint32_t sectors_per_stripe;
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uint16_t id;
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uint16_t flags;
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};
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/*
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* One of these per allocated PCI device.
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*/
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struct nvme_controller {
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/* Hot data (accessed in I/O path) starts here. */
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/** NVMe MMIO register space */
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volatile struct nvme_registers *regs;
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/** I/O queue pairs */
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struct nvme_qpair *ioq;
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uint32_t is_resetting;
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uint32_t num_ns;
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/** Array of namespaces indexed by nsid - 1 */
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struct nvme_namespace *ns;
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/* Cold data (not accessed in normal I/O path) is after this point. */
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/* Opaque handle to associated PCI device. */
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void *devhandle;
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uint32_t num_io_queues;
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/** maximum i/o size in bytes */
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uint32_t max_xfer_size;
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/** minimum page size supported by this controller in bytes */
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uint32_t min_page_size;
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/** stride in uint32_t units between doorbell registers (1 = 4 bytes, 2 = 8 bytes, ...) */
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uint32_t doorbell_stride_u32;
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uint32_t num_aers;
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struct nvme_async_event_request aer[NVME_MAX_ASYNC_EVENTS];
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nvme_aer_cb_fn_t aer_cb_fn;
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void *aer_cb_arg;
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bool is_failed;
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/** guards access to the controller itself, including admin queues */
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nvme_mutex_t ctrlr_lock;
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struct nvme_qpair adminq;
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/**
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* Identify Controller data.
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*/
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struct nvme_controller_data cdata;
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/**
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* Array of Identify Namespace data.
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*
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* Stored separately from ns since nsdata should not normally be accessed during I/O.
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*/
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struct nvme_namespace_data *nsdata;
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};
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extern int __thread nvme_thread_ioq_index;
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struct nvme_driver {
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nvme_mutex_t lock;
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uint16_t *ioq_index_pool;
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uint32_t max_io_queues;
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uint16_t ioq_index_pool_next;
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};
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extern struct nvme_driver g_nvme_driver;
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#define nvme_min(a,b) (((a)<(b))?(a):(b))
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#define INTEL_DC_P3X00_DEVID 0x09538086
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static inline uint32_t
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_nvme_mmio_read_4(const volatile uint32_t *addr)
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{
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return *addr;
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}
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static inline void
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_nvme_mmio_write_4(volatile uint32_t *addr, uint32_t val)
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{
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*addr = val;
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}
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static inline void
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_nvme_mmio_write_8(volatile uint64_t *addr, uint64_t val)
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{
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*addr = val;
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}
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#define nvme_mmio_read_4(sc, reg) \
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_nvme_mmio_read_4(&(sc)->regs->reg)
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#define nvme_mmio_write_4(sc, reg, val) \
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_nvme_mmio_write_4(&(sc)->regs->reg, val)
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#define nvme_mmio_write_8(sc, reg, val) \
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_nvme_mmio_write_8(&(sc)->regs->reg, val)
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#define nvme_delay usleep
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static inline uint32_t
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nvme_u32log2(uint32_t x)
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{
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if (x == 0) {
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/* __builtin_clz(0) is undefined, so just bail */
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return 0;
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}
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return 31u - __builtin_clz(x);
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}
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static inline uint32_t
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nvme_align32pow2(uint32_t x)
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{
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return 1u << (1 + nvme_u32log2(x - 1));
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}
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/* Admin functions */
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void nvme_ctrlr_cmd_set_feature(struct nvme_controller *ctrlr,
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uint8_t feature, uint32_t cdw11,
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void *payload, uint32_t payload_size,
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nvme_cb_fn_t cb_fn, void *cb_arg);
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void nvme_ctrlr_cmd_get_feature(struct nvme_controller *ctrlr,
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uint8_t feature, uint32_t cdw11,
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void *payload, uint32_t payload_size,
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nvme_cb_fn_t cb_fn, void *cb_arg);
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void nvme_ctrlr_cmd_get_log_page(struct nvme_controller *ctrlr,
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uint8_t log_page, uint32_t nsid,
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void *payload, uint32_t payload_size,
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nvme_cb_fn_t cb_fn, void *cb_arg);
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void nvme_ctrlr_cmd_identify_controller(struct nvme_controller *ctrlr,
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void *payload,
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nvme_cb_fn_t cb_fn, void *cb_arg);
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void nvme_ctrlr_cmd_identify_namespace(struct nvme_controller *ctrlr,
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uint16_t nsid, void *payload,
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nvme_cb_fn_t cb_fn, void *cb_arg);
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void nvme_ctrlr_cmd_get_error_page(struct nvme_controller *ctrlr,
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struct nvme_error_information_entry *payload,
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uint32_t num_entries, /* 0 = max */
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nvme_cb_fn_t cb_fn,
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void *cb_arg);
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void nvme_ctrlr_cmd_get_health_information_page(struct nvme_controller *ctrlr,
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uint32_t nsid,
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struct nvme_health_information_page *payload,
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nvme_cb_fn_t cb_fn,
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void *cb_arg);
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void nvme_ctrlr_cmd_get_firmware_page(struct nvme_controller *ctrlr,
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struct nvme_firmware_page *payload,
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nvme_cb_fn_t cb_fn,
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void *cb_arg);
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void nvme_ctrlr_cmd_create_io_cq(struct nvme_controller *ctrlr,
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struct nvme_qpair *io_que,
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nvme_cb_fn_t cb_fn, void *cb_arg);
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void nvme_ctrlr_cmd_create_io_sq(struct nvme_controller *ctrlr,
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struct nvme_qpair *io_que,
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nvme_cb_fn_t cb_fn, void *cb_arg);
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void nvme_ctrlr_cmd_set_num_queues(struct nvme_controller *ctrlr,
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uint32_t num_queues, nvme_cb_fn_t cb_fn,
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void *cb_arg);
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void nvme_ctrlr_cmd_set_async_event_config(struct nvme_controller *ctrlr,
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union nvme_critical_warning_state state,
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nvme_cb_fn_t cb_fn, void *cb_arg);
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void nvme_ctrlr_cmd_abort(struct nvme_controller *ctrlr, uint16_t cid,
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uint16_t sqid, nvme_cb_fn_t cb_fn, void *cb_arg);
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void nvme_completion_poll_cb(void *arg, const struct nvme_completion *cpl);
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int nvme_ctrlr_construct(struct nvme_controller *ctrlr, void *devhandle);
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void nvme_ctrlr_destruct(struct nvme_controller *ctrlr);
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int nvme_ctrlr_start(struct nvme_controller *ctrlr);
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int nvme_ctrlr_hw_reset(struct nvme_controller *ctrlr);
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void nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr,
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struct nvme_request *req);
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void nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr,
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struct nvme_request *req);
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void nvme_ctrlr_post_failed_request(struct nvme_controller *ctrlr,
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struct nvme_request *req);
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int nvme_qpair_construct(struct nvme_qpair *qpair, uint16_t id,
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uint16_t num_entries,
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uint16_t num_trackers,
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struct nvme_controller *ctrlr);
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void nvme_qpair_destroy(struct nvme_qpair *qpair);
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void nvme_qpair_enable(struct nvme_qpair *qpair);
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void nvme_qpair_disable(struct nvme_qpair *qpair);
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void nvme_qpair_submit_tracker(struct nvme_qpair *qpair,
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struct nvme_tracker *tr);
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void nvme_qpair_process_completions(struct nvme_qpair *qpair);
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void nvme_qpair_submit_request(struct nvme_qpair *qpair,
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struct nvme_request *req);
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void nvme_qpair_reset(struct nvme_qpair *qpair);
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void nvme_qpair_fail(struct nvme_qpair *qpair);
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void nvme_qpair_manual_complete_request(struct nvme_qpair *qpair,
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struct nvme_request *req,
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uint32_t sct, uint32_t sc,
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bool print_on_error);
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int nvme_ns_construct(struct nvme_namespace *ns, uint16_t id,
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struct nvme_controller *ctrlr);
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void nvme_ns_destruct(struct nvme_namespace *ns);
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void nvme_dump_command(struct nvme_command *cmd);
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void nvme_dump_completion(struct nvme_completion *cpl);
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struct nvme_request *
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nvme_allocate_request(void *payload, uint32_t payload_size,
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nvme_cb_fn_t cb_fn, void *cb_arg);
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void nvme_cb_complete_child(void *child, const struct nvme_completion *cpl);
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void nvme_request_add_child(struct nvme_request *parent, struct nvme_request *child);
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#endif /* __NVME_INTERNAL_H__ */
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