a15573c47c
In nvme_ctrlr_hw_reset(), if we encounter a controller whose CC.EN bit is already 0 (controller is disabled), the previous code would enable the controller just so that it could be disabled to get a full reset (transition from CC.EN = 1 to CC.EN = 0). However, it is a safe assumption that if CC.EN is already 0, the controller has just been reset, so we don't need to reset it again. This saves a significant amount of time (2+ seconds per controller with Intel SSD DC P3700) during initialization for devices that were disabled on startup. Change-Id: I552b1f0f185a84a8a0ce57a93b012d9d5fe096f3 Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com>
927 lines
24 KiB
C
927 lines
24 KiB
C
/*-
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* BSD LICENSE
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*
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* Copyright (c) Intel Corporation.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "nvme_internal.h"
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#include "spdk/pci.h"
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/**
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* \file
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*
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*/
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static int nvme_ctrlr_construct_and_submit_aer(struct spdk_nvme_ctrlr *ctrlr,
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struct nvme_async_event_request *aer);
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static void
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nvme_ctrlr_construct_intel_support_log_page_list(struct spdk_nvme_ctrlr *ctrlr,
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struct spdk_nvme_intel_log_page_directory *log_page_directory)
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{
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struct spdk_pci_device *dev;
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struct pci_id pci_id;
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if (ctrlr->cdata.vid != SPDK_PCI_VID_INTEL || log_page_directory == NULL)
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return;
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dev = ctrlr->devhandle;
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pci_id.vendor_id = spdk_pci_device_get_vendor_id(dev);
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pci_id.dev_id = spdk_pci_device_get_device_id(dev);
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pci_id.sub_vendor_id = spdk_pci_device_get_subvendor_id(dev);
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pci_id.sub_dev_id = spdk_pci_device_get_subdevice_id(dev);
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ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY] = true;
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if (log_page_directory->read_latency_log_len ||
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nvme_intel_has_quirk(&pci_id, NVME_INTEL_QUIRK_READ_LATENCY)) {
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ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_READ_CMD_LATENCY] = true;
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}
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if (log_page_directory->write_latency_log_len ||
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nvme_intel_has_quirk(&pci_id, NVME_INTEL_QUIRK_WRITE_LATENCY)) {
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ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_WRITE_CMD_LATENCY] = true;
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}
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if (log_page_directory->temperature_statistics_log_len) {
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ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_TEMPERATURE] = true;
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}
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if (log_page_directory->smart_log_len) {
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ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_SMART] = true;
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}
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}
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static int nvme_ctrlr_set_intel_support_log_pages(struct spdk_nvme_ctrlr *ctrlr)
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{
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uint64_t phys_addr = 0;
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struct nvme_completion_poll_status status;
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struct spdk_nvme_intel_log_page_directory *log_page_directory;
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log_page_directory = nvme_malloc("nvme_log_page_directory",
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sizeof(struct spdk_nvme_intel_log_page_directory),
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64, &phys_addr);
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if (log_page_directory == NULL) {
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nvme_printf(NULL, "could not allocate log_page_directory\n");
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return ENXIO;
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}
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status.done = false;
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spdk_nvme_ctrlr_cmd_get_log_page(ctrlr, SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY, SPDK_NVME_GLOBAL_NS_TAG,
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log_page_directory, sizeof(struct spdk_nvme_intel_log_page_directory),
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nvme_completion_poll_cb,
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&status);
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while (status.done == false) {
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nvme_qpair_process_completions(&ctrlr->adminq, 0);
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}
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if (spdk_nvme_cpl_is_error(&status.cpl)) {
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nvme_free(log_page_directory);
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nvme_printf(ctrlr, "nvme_ctrlr_cmd_get_log_page failed!\n");
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return ENXIO;
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}
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nvme_ctrlr_construct_intel_support_log_page_list(ctrlr, log_page_directory);
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nvme_free(log_page_directory);
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return 0;
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}
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static void
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nvme_ctrlr_set_supported_log_pages(struct spdk_nvme_ctrlr *ctrlr)
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{
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memset(ctrlr->log_page_supported, 0, sizeof(ctrlr->log_page_supported));
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/* Mandatory pages */
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ctrlr->log_page_supported[SPDK_NVME_LOG_ERROR] = true;
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ctrlr->log_page_supported[SPDK_NVME_LOG_HEALTH_INFORMATION] = true;
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ctrlr->log_page_supported[SPDK_NVME_LOG_FIRMWARE_SLOT] = true;
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if (ctrlr->cdata.lpa.celp) {
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ctrlr->log_page_supported[SPDK_NVME_LOG_COMMAND_EFFECTS_LOG] = true;
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}
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if (ctrlr->cdata.vid == SPDK_PCI_VID_INTEL) {
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nvme_ctrlr_set_intel_support_log_pages(ctrlr);
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}
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}
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static void
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nvme_ctrlr_set_intel_supported_features(struct spdk_nvme_ctrlr *ctrlr)
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{
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ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_MAX_LBA] = true;
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ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_NATIVE_MAX_LBA] = true;
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ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_POWER_GOVERNOR_SETTING] = true;
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ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_SMBUS_ADDRESS] = true;
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ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_LED_PATTERN] = true;
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ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_RESET_TIMED_WORKLOAD_COUNTERS] = true;
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ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_LATENCY_TRACKING] = true;
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}
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static void
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nvme_ctrlr_set_supported_features(struct spdk_nvme_ctrlr *ctrlr)
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{
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memset(ctrlr->feature_supported, 0, sizeof(ctrlr->feature_supported));
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/* Mandatory features */
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ctrlr->feature_supported[SPDK_NVME_FEAT_ARBITRATION] = true;
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ctrlr->feature_supported[SPDK_NVME_FEAT_POWER_MANAGEMENT] = true;
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ctrlr->feature_supported[SPDK_NVME_FEAT_TEMPERATURE_THRESHOLD] = true;
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ctrlr->feature_supported[SPDK_NVME_FEAT_ERROR_RECOVERY] = true;
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ctrlr->feature_supported[SPDK_NVME_FEAT_NUMBER_OF_QUEUES] = true;
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ctrlr->feature_supported[SPDK_NVME_FEAT_INTERRUPT_COALESCING] = true;
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ctrlr->feature_supported[SPDK_NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION] = true;
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ctrlr->feature_supported[SPDK_NVME_FEAT_WRITE_ATOMICITY] = true;
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ctrlr->feature_supported[SPDK_NVME_FEAT_ASYNC_EVENT_CONFIGURATION] = true;
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/* Optional features */
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if (ctrlr->cdata.vwc.present) {
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ctrlr->feature_supported[SPDK_NVME_FEAT_VOLATILE_WRITE_CACHE] = true;
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}
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if (ctrlr->cdata.apsta.supported) {
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ctrlr->feature_supported[SPDK_NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION] = true;
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}
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if (ctrlr->cdata.hmpre) {
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ctrlr->feature_supported[SPDK_NVME_FEAT_HOST_MEM_BUFFER] = true;
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}
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if (ctrlr->cdata.vid == SPDK_PCI_VID_INTEL) {
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nvme_ctrlr_set_intel_supported_features(ctrlr);
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}
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}
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static int
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nvme_ctrlr_construct_admin_qpair(struct spdk_nvme_ctrlr *ctrlr)
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{
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return nvme_qpair_construct(&ctrlr->adminq,
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0, /* qpair ID */
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NVME_ADMIN_ENTRIES,
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NVME_ADMIN_TRACKERS,
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ctrlr);
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}
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static int
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nvme_ctrlr_construct_io_qpairs(struct spdk_nvme_ctrlr *ctrlr)
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{
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struct nvme_qpair *qpair;
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union spdk_nvme_cap_lo_register cap_lo;
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uint32_t i, num_entries, num_trackers;
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int rc;
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if (ctrlr->ioq != NULL) {
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/*
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* io_qpairs were already constructed, so just return.
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* This typically happens when the controller is
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* initialized a second (or subsequent) time after a
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* controller reset.
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*/
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return 0;
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}
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/*
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* NVMe spec sets a hard limit of 64K max entries, but
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* devices may specify a smaller limit, so we need to check
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* the MQES field in the capabilities register.
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*/
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cap_lo.raw = nvme_mmio_read_4(ctrlr, cap_lo.raw);
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num_entries = nvme_min(NVME_IO_ENTRIES, cap_lo.bits.mqes + 1);
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/*
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* No need to have more trackers than entries in the submit queue.
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* Note also that for a queue size of N, we can only have (N-1)
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* commands outstanding, hence the "-1" here.
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*/
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num_trackers = nvme_min(NVME_IO_TRACKERS, (num_entries - 1));
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ctrlr->max_xfer_size = NVME_MAX_XFER_SIZE;
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ctrlr->ioq = calloc(ctrlr->num_io_queues, sizeof(struct nvme_qpair));
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if (ctrlr->ioq == NULL)
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return -1;
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for (i = 0; i < ctrlr->num_io_queues; i++) {
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qpair = &ctrlr->ioq[i];
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/*
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* Admin queue has ID=0. IO queues start at ID=1 -
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* hence the 'i+1' here.
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*/
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rc = nvme_qpair_construct(qpair,
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i + 1, /* qpair ID */
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num_entries,
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num_trackers,
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ctrlr);
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if (rc)
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return -1;
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}
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return 0;
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}
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static void
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nvme_ctrlr_fail(struct spdk_nvme_ctrlr *ctrlr)
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{
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uint32_t i;
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ctrlr->is_failed = true;
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nvme_qpair_fail(&ctrlr->adminq);
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for (i = 0; i < ctrlr->num_io_queues; i++) {
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nvme_qpair_fail(&ctrlr->ioq[i]);
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}
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}
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static int
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_nvme_ctrlr_wait_for_ready(struct spdk_nvme_ctrlr *ctrlr, int desired_ready_value)
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{
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int ms_waited, ready_timeout_in_ms;
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union spdk_nvme_csts_register csts;
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union spdk_nvme_cap_lo_register cap_lo;
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/* Get ready timeout value from controller, in units of 500ms. */
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cap_lo.raw = nvme_mmio_read_4(ctrlr, cap_lo.raw);
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ready_timeout_in_ms = cap_lo.bits.to * 500;
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csts.raw = nvme_mmio_read_4(ctrlr, csts);
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ms_waited = 0;
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while (csts.bits.rdy != desired_ready_value) {
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nvme_delay(1000);
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if (ms_waited++ > ready_timeout_in_ms) {
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nvme_printf(ctrlr, "controller ready did not become %d "
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"within %d ms\n", desired_ready_value, ready_timeout_in_ms);
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return ENXIO;
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}
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csts.raw = nvme_mmio_read_4(ctrlr, csts);
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}
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return 0;
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}
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static int
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nvme_ctrlr_wait_for_ready(struct spdk_nvme_ctrlr *ctrlr)
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{
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union spdk_nvme_cc_register cc;
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cc.raw = nvme_mmio_read_4(ctrlr, cc.raw);
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if (!cc.bits.en) {
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nvme_printf(ctrlr, "%s called with cc.en = 0\n", __func__);
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return ENXIO;
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}
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return _nvme_ctrlr_wait_for_ready(ctrlr, 1);
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}
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static void
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nvme_ctrlr_disable(struct spdk_nvme_ctrlr *ctrlr)
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{
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union spdk_nvme_cc_register cc;
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union spdk_nvme_csts_register csts;
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cc.raw = nvme_mmio_read_4(ctrlr, cc.raw);
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csts.raw = nvme_mmio_read_4(ctrlr, csts);
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if (cc.bits.en == 1 && csts.bits.rdy == 0) {
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_nvme_ctrlr_wait_for_ready(ctrlr, 1);
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}
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cc.bits.en = 0;
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nvme_mmio_write_4(ctrlr, cc.raw, cc.raw);
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_nvme_ctrlr_wait_for_ready(ctrlr, 0);
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}
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static void
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nvme_ctrlr_shutdown(struct spdk_nvme_ctrlr *ctrlr)
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{
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union spdk_nvme_cc_register cc;
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union spdk_nvme_csts_register csts;
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int ms_waited = 0;
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cc.raw = nvme_mmio_read_4(ctrlr, cc.raw);
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cc.bits.shn = SPDK_NVME_SHN_NORMAL;
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nvme_mmio_write_4(ctrlr, cc.raw, cc.raw);
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csts.raw = nvme_mmio_read_4(ctrlr, csts);
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/*
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* The NVMe spec does not define a timeout period
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* for shutdown notification, so we just pick
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* 5 seconds as a reasonable amount of time to
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* wait before proceeding.
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*/
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while (csts.bits.shst != SPDK_NVME_SHST_COMPLETE) {
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nvme_delay(1000);
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csts.raw = nvme_mmio_read_4(ctrlr, csts);
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if (ms_waited++ >= 5000)
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break;
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}
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if (csts.bits.shst != SPDK_NVME_SHST_COMPLETE)
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nvme_printf(ctrlr, "did not shutdown within 5 seconds\n");
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}
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static int
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nvme_ctrlr_enable(struct spdk_nvme_ctrlr *ctrlr)
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{
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union spdk_nvme_cc_register cc;
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union spdk_nvme_csts_register csts;
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union spdk_nvme_aqa_register aqa;
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cc.raw = nvme_mmio_read_4(ctrlr, cc.raw);
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csts.raw = nvme_mmio_read_4(ctrlr, csts);
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if (cc.bits.en == 1) {
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if (csts.bits.rdy == 1) {
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return 0;
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} else {
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return nvme_ctrlr_wait_for_ready(ctrlr);
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}
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}
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nvme_mmio_write_8(ctrlr, asq, ctrlr->adminq.cmd_bus_addr);
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nvme_mmio_write_8(ctrlr, acq, ctrlr->adminq.cpl_bus_addr);
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aqa.raw = 0;
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/* acqs and asqs are 0-based. */
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aqa.bits.acqs = ctrlr->adminq.num_entries - 1;
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aqa.bits.asqs = ctrlr->adminq.num_entries - 1;
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nvme_mmio_write_4(ctrlr, aqa.raw, aqa.raw);
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cc.bits.en = 1;
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cc.bits.css = 0;
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cc.bits.ams = 0;
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cc.bits.shn = 0;
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cc.bits.iosqes = 6; /* SQ entry size == 64 == 2^6 */
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cc.bits.iocqes = 4; /* CQ entry size == 16 == 2^4 */
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/* Page size is 2 ^ (12 + mps). */
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cc.bits.mps = nvme_u32log2(PAGE_SIZE) - 12;
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nvme_mmio_write_4(ctrlr, cc.raw, cc.raw);
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return nvme_ctrlr_wait_for_ready(ctrlr);
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}
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static int
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nvme_ctrlr_hw_reset(struct spdk_nvme_ctrlr *ctrlr)
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{
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uint32_t i;
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int rc;
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union spdk_nvme_cc_register cc;
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cc.raw = nvme_mmio_read_4(ctrlr, cc.raw);
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if (cc.bits.en) {
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nvme_qpair_disable(&ctrlr->adminq);
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for (i = 0; i < ctrlr->num_io_queues; i++) {
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nvme_qpair_disable(&ctrlr->ioq[i]);
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}
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} else {
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/*
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* The controller was already disabled. We will assume that nothing
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* has been changed since cc.en was set to 0,
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* meaning that we don't need to do an extra reset, and we can just
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* re-enable the controller.
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*/
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}
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nvme_ctrlr_disable(ctrlr);
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rc = nvme_ctrlr_enable(ctrlr);
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return rc;
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}
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int
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spdk_nvme_ctrlr_reset(struct spdk_nvme_ctrlr *ctrlr)
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{
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int rc;
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nvme_mutex_lock(&ctrlr->ctrlr_lock);
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if (ctrlr->is_resetting || ctrlr->is_failed) {
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/*
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* Controller is already resetting or has failed. Return
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* immediately since there is no need to kick off another
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* reset in these cases.
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*/
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nvme_mutex_unlock(&ctrlr->ctrlr_lock);
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return 0;
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}
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ctrlr->is_resetting = true;
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nvme_printf(ctrlr, "resetting controller\n");
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/* nvme_ctrlr_start() issues a reset as its first step */
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rc = nvme_ctrlr_start(ctrlr);
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if (rc) {
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nvme_ctrlr_fail(ctrlr);
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}
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ctrlr->is_resetting = false;
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nvme_mutex_unlock(&ctrlr->ctrlr_lock);
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return rc;
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}
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static int
|
|
nvme_ctrlr_identify(struct spdk_nvme_ctrlr *ctrlr)
|
|
{
|
|
struct nvme_completion_poll_status status;
|
|
|
|
status.done = false;
|
|
nvme_ctrlr_cmd_identify_controller(ctrlr, &ctrlr->cdata,
|
|
nvme_completion_poll_cb, &status);
|
|
while (status.done == false) {
|
|
nvme_qpair_process_completions(&ctrlr->adminq, 0);
|
|
}
|
|
if (spdk_nvme_cpl_is_error(&status.cpl)) {
|
|
nvme_printf(ctrlr, "nvme_identify_controller failed!\n");
|
|
return ENXIO;
|
|
}
|
|
|
|
/*
|
|
* Use MDTS to ensure our default max_xfer_size doesn't exceed what the
|
|
* controller supports.
|
|
*/
|
|
if (ctrlr->cdata.mdts > 0) {
|
|
ctrlr->max_xfer_size = nvme_min(ctrlr->max_xfer_size,
|
|
ctrlr->min_page_size * (1 << (ctrlr->cdata.mdts)));
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
nvme_ctrlr_set_num_qpairs(struct spdk_nvme_ctrlr *ctrlr)
|
|
{
|
|
struct nvme_driver *driver = &g_nvme_driver;
|
|
struct nvme_completion_poll_status status;
|
|
int cq_allocated, sq_allocated;
|
|
uint32_t max_io_queues;
|
|
|
|
status.done = false;
|
|
|
|
nvme_mutex_lock(&driver->lock);
|
|
max_io_queues = driver->max_io_queues;
|
|
nvme_mutex_unlock(&driver->lock);
|
|
|
|
nvme_ctrlr_cmd_set_num_queues(ctrlr, max_io_queues,
|
|
nvme_completion_poll_cb, &status);
|
|
while (status.done == false) {
|
|
nvme_qpair_process_completions(&ctrlr->adminq, 0);
|
|
}
|
|
if (spdk_nvme_cpl_is_error(&status.cpl)) {
|
|
nvme_printf(ctrlr, "nvme_set_num_queues failed!\n");
|
|
return ENXIO;
|
|
}
|
|
|
|
/*
|
|
* Data in cdw0 is 0-based.
|
|
* Lower 16-bits indicate number of submission queues allocated.
|
|
* Upper 16-bits indicate number of completion queues allocated.
|
|
*/
|
|
sq_allocated = (status.cpl.cdw0 & 0xFFFF) + 1;
|
|
cq_allocated = (status.cpl.cdw0 >> 16) + 1;
|
|
|
|
ctrlr->num_io_queues = nvme_min(sq_allocated, cq_allocated);
|
|
|
|
nvme_mutex_lock(&driver->lock);
|
|
driver->max_io_queues = nvme_min(driver->max_io_queues, ctrlr->num_io_queues);
|
|
nvme_mutex_unlock(&driver->lock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
nvme_ctrlr_create_qpairs(struct spdk_nvme_ctrlr *ctrlr)
|
|
{
|
|
struct nvme_completion_poll_status status;
|
|
struct nvme_qpair *qpair;
|
|
uint32_t i;
|
|
|
|
if (nvme_ctrlr_construct_io_qpairs(ctrlr)) {
|
|
nvme_printf(ctrlr, "nvme_ctrlr_construct_io_qpairs failed!\n");
|
|
return ENXIO;
|
|
}
|
|
|
|
for (i = 0; i < ctrlr->num_io_queues; i++) {
|
|
qpair = &ctrlr->ioq[i];
|
|
|
|
status.done = false;
|
|
nvme_ctrlr_cmd_create_io_cq(ctrlr, qpair,
|
|
nvme_completion_poll_cb, &status);
|
|
while (status.done == false) {
|
|
nvme_qpair_process_completions(&ctrlr->adminq, 0);
|
|
}
|
|
if (spdk_nvme_cpl_is_error(&status.cpl)) {
|
|
nvme_printf(ctrlr, "nvme_create_io_cq failed!\n");
|
|
return ENXIO;
|
|
}
|
|
|
|
status.done = false;
|
|
nvme_ctrlr_cmd_create_io_sq(qpair->ctrlr, qpair,
|
|
nvme_completion_poll_cb, &status);
|
|
while (status.done == false) {
|
|
nvme_qpair_process_completions(&ctrlr->adminq, 0);
|
|
}
|
|
if (spdk_nvme_cpl_is_error(&status.cpl)) {
|
|
nvme_printf(ctrlr, "nvme_create_io_sq failed!\n");
|
|
return ENXIO;
|
|
}
|
|
|
|
nvme_qpair_reset(qpair);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
nvme_ctrlr_destruct_namespaces(struct spdk_nvme_ctrlr *ctrlr)
|
|
{
|
|
if (ctrlr->ns) {
|
|
uint32_t i, num_ns = ctrlr->num_ns;
|
|
|
|
for (i = 0; i < num_ns; i++) {
|
|
nvme_ns_destruct(&ctrlr->ns[i]);
|
|
}
|
|
|
|
free(ctrlr->ns);
|
|
ctrlr->ns = NULL;
|
|
ctrlr->num_ns = 0;
|
|
}
|
|
|
|
if (ctrlr->nsdata) {
|
|
nvme_free(ctrlr->nsdata);
|
|
ctrlr->nsdata = NULL;
|
|
}
|
|
}
|
|
|
|
static int
|
|
nvme_ctrlr_construct_namespaces(struct spdk_nvme_ctrlr *ctrlr)
|
|
{
|
|
uint32_t i, nn = ctrlr->cdata.nn;
|
|
uint64_t phys_addr = 0;
|
|
|
|
if (nn == 0) {
|
|
nvme_printf(ctrlr, "controller has 0 namespaces\n");
|
|
return -1;
|
|
}
|
|
|
|
/* ctrlr->num_ns may be 0 (startup) or a different number of namespaces (reset),
|
|
* so check if we need to reallocate.
|
|
*/
|
|
if (nn != ctrlr->num_ns) {
|
|
nvme_ctrlr_destruct_namespaces(ctrlr);
|
|
|
|
ctrlr->ns = calloc(nn, sizeof(struct spdk_nvme_ns));
|
|
if (ctrlr->ns == NULL) {
|
|
goto fail;
|
|
}
|
|
|
|
ctrlr->nsdata = nvme_malloc("nvme_namespaces",
|
|
nn * sizeof(struct spdk_nvme_ns_data), 64,
|
|
&phys_addr);
|
|
if (ctrlr->nsdata == NULL) {
|
|
goto fail;
|
|
}
|
|
|
|
ctrlr->num_ns = nn;
|
|
}
|
|
|
|
for (i = 0; i < nn; i++) {
|
|
struct spdk_nvme_ns *ns = &ctrlr->ns[i];
|
|
uint32_t nsid = i + 1;
|
|
|
|
if (nvme_ns_construct(ns, nsid, ctrlr) != 0) {
|
|
goto fail;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
|
|
fail:
|
|
nvme_ctrlr_destruct_namespaces(ctrlr);
|
|
return -1;
|
|
}
|
|
|
|
static void
|
|
nvme_ctrlr_async_event_cb(void *arg, const struct spdk_nvme_cpl *cpl)
|
|
{
|
|
struct nvme_async_event_request *aer = arg;
|
|
struct spdk_nvme_ctrlr *ctrlr = aer->ctrlr;
|
|
|
|
if (cpl->status.sc == SPDK_NVME_SC_ABORTED_SQ_DELETION) {
|
|
/*
|
|
* This is simulated when controller is being shut down, to
|
|
* effectively abort outstanding asynchronous event requests
|
|
* and make sure all memory is freed. Do not repost the
|
|
* request in this case.
|
|
*/
|
|
return;
|
|
}
|
|
|
|
if (ctrlr->aer_cb_fn != NULL) {
|
|
ctrlr->aer_cb_fn(ctrlr->aer_cb_arg, cpl);
|
|
}
|
|
|
|
/*
|
|
* Repost another asynchronous event request to replace the one
|
|
* that just completed.
|
|
*/
|
|
if (nvme_ctrlr_construct_and_submit_aer(ctrlr, aer)) {
|
|
/*
|
|
* We can't do anything to recover from a failure here,
|
|
* so just print a warning message and leave the AER unsubmitted.
|
|
*/
|
|
nvme_printf(ctrlr, "resubmitting AER failed!\n");
|
|
}
|
|
}
|
|
|
|
static int
|
|
nvme_ctrlr_construct_and_submit_aer(struct spdk_nvme_ctrlr *ctrlr,
|
|
struct nvme_async_event_request *aer)
|
|
{
|
|
struct nvme_request *req;
|
|
|
|
aer->ctrlr = ctrlr;
|
|
req = nvme_allocate_request_null(nvme_ctrlr_async_event_cb, aer);
|
|
aer->req = req;
|
|
if (req == NULL) {
|
|
return -1;
|
|
}
|
|
|
|
/*
|
|
* Disable timeout here, since asynchronous event requests should by
|
|
* nature never be timed out.
|
|
*/
|
|
req->timeout = false;
|
|
req->cmd.opc = SPDK_NVME_OPC_ASYNC_EVENT_REQUEST;
|
|
nvme_ctrlr_submit_admin_request(ctrlr, req);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
nvme_ctrlr_configure_aer(struct spdk_nvme_ctrlr *ctrlr)
|
|
{
|
|
union spdk_nvme_critical_warning_state state;
|
|
struct nvme_async_event_request *aer;
|
|
uint32_t i;
|
|
struct nvme_completion_poll_status status;
|
|
|
|
status.done = false;
|
|
|
|
state.raw = 0xFF;
|
|
state.bits.reserved = 0;
|
|
nvme_ctrlr_cmd_set_async_event_config(ctrlr, state, nvme_completion_poll_cb, &status);
|
|
|
|
while (status.done == false) {
|
|
nvme_qpair_process_completions(&ctrlr->adminq, 0);
|
|
}
|
|
if (spdk_nvme_cpl_is_error(&status.cpl)) {
|
|
nvme_printf(ctrlr, "nvme_ctrlr_cmd_set_async_event_config failed!\n");
|
|
return ENXIO;
|
|
}
|
|
|
|
/* aerl is a zero-based value, so we need to add 1 here. */
|
|
ctrlr->num_aers = nvme_min(NVME_MAX_ASYNC_EVENTS, (ctrlr->cdata.aerl + 1));
|
|
|
|
for (i = 0; i < ctrlr->num_aers; i++) {
|
|
aer = &ctrlr->aer[i];
|
|
if (nvme_ctrlr_construct_and_submit_aer(ctrlr, aer)) {
|
|
nvme_printf(ctrlr, "nvme_ctrlr_construct_and_submit_aer failed!\n");
|
|
return -1;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
nvme_ctrlr_start(struct spdk_nvme_ctrlr *ctrlr)
|
|
{
|
|
if (nvme_ctrlr_hw_reset(ctrlr) != 0) {
|
|
return -1;
|
|
}
|
|
|
|
nvme_qpair_reset(&ctrlr->adminq);
|
|
|
|
nvme_qpair_enable(&ctrlr->adminq);
|
|
|
|
if (nvme_ctrlr_identify(ctrlr) != 0) {
|
|
return -1;
|
|
}
|
|
|
|
if (nvme_ctrlr_set_num_qpairs(ctrlr) != 0) {
|
|
return -1;
|
|
}
|
|
|
|
if (nvme_ctrlr_create_qpairs(ctrlr) != 0) {
|
|
return -1;
|
|
}
|
|
|
|
if (nvme_ctrlr_construct_namespaces(ctrlr) != 0) {
|
|
return -1;
|
|
}
|
|
|
|
if (nvme_ctrlr_configure_aer(ctrlr) != 0) {
|
|
return -1;
|
|
}
|
|
|
|
nvme_ctrlr_set_supported_log_pages(ctrlr);
|
|
nvme_ctrlr_set_supported_features(ctrlr);
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
nvme_ctrlr_allocate_bars(struct spdk_nvme_ctrlr *ctrlr)
|
|
{
|
|
int rc;
|
|
void *addr;
|
|
|
|
rc = nvme_pcicfg_map_bar(ctrlr->devhandle, 0, 0 /* writable */, &addr);
|
|
ctrlr->regs = (volatile struct spdk_nvme_registers *)addr;
|
|
if ((ctrlr->regs == NULL) || (rc != 0)) {
|
|
nvme_printf(ctrlr, "pci_device_map_range failed with error code %d\n", rc);
|
|
return -1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
nvme_ctrlr_free_bars(struct spdk_nvme_ctrlr *ctrlr)
|
|
{
|
|
int rc = 0;
|
|
void *addr = (void *)ctrlr->regs;
|
|
|
|
if (addr) {
|
|
rc = nvme_pcicfg_unmap_bar(ctrlr->devhandle, 0, addr);
|
|
}
|
|
return rc;
|
|
}
|
|
|
|
int
|
|
nvme_ctrlr_construct(struct spdk_nvme_ctrlr *ctrlr, void *devhandle)
|
|
{
|
|
union spdk_nvme_cap_hi_register cap_hi;
|
|
uint32_t cmd_reg;
|
|
int status;
|
|
int rc;
|
|
|
|
ctrlr->devhandle = devhandle;
|
|
|
|
status = nvme_ctrlr_allocate_bars(ctrlr);
|
|
if (status != 0) {
|
|
return status;
|
|
}
|
|
|
|
/* Enable PCI busmaster. */
|
|
nvme_pcicfg_read32(devhandle, &cmd_reg, 4);
|
|
cmd_reg |= 0x4;
|
|
nvme_pcicfg_write32(devhandle, cmd_reg, 4);
|
|
|
|
cap_hi.raw = nvme_mmio_read_4(ctrlr, cap_hi.raw);
|
|
|
|
/* Doorbell stride is 2 ^ (dstrd + 2),
|
|
* but we want multiples of 4, so drop the + 2 */
|
|
ctrlr->doorbell_stride_u32 = 1 << cap_hi.bits.dstrd;
|
|
|
|
ctrlr->min_page_size = 1 << (12 + cap_hi.bits.mpsmin);
|
|
|
|
rc = nvme_ctrlr_construct_admin_qpair(ctrlr);
|
|
if (rc)
|
|
return rc;
|
|
|
|
ctrlr->is_resetting = false;
|
|
ctrlr->is_failed = false;
|
|
|
|
nvme_mutex_init_recursive(&ctrlr->ctrlr_lock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
nvme_ctrlr_destruct(struct spdk_nvme_ctrlr *ctrlr)
|
|
{
|
|
uint32_t i;
|
|
|
|
nvme_ctrlr_disable(ctrlr);
|
|
nvme_ctrlr_shutdown(ctrlr);
|
|
|
|
nvme_ctrlr_destruct_namespaces(ctrlr);
|
|
|
|
for (i = 0; i < ctrlr->num_io_queues; i++) {
|
|
nvme_qpair_destroy(&ctrlr->ioq[i]);
|
|
}
|
|
|
|
free(ctrlr->ioq);
|
|
|
|
nvme_qpair_destroy(&ctrlr->adminq);
|
|
|
|
nvme_ctrlr_free_bars(ctrlr);
|
|
nvme_mutex_destroy(&ctrlr->ctrlr_lock);
|
|
}
|
|
|
|
void
|
|
nvme_ctrlr_submit_admin_request(struct spdk_nvme_ctrlr *ctrlr,
|
|
struct nvme_request *req)
|
|
{
|
|
nvme_qpair_submit_request(&ctrlr->adminq, req);
|
|
}
|
|
|
|
void
|
|
nvme_ctrlr_submit_io_request(struct spdk_nvme_ctrlr *ctrlr,
|
|
struct nvme_request *req)
|
|
{
|
|
struct nvme_qpair *qpair;
|
|
|
|
nvme_assert(nvme_thread_ioq_index >= 0, ("no ioq_index assigned for thread\n"));
|
|
qpair = &ctrlr->ioq[nvme_thread_ioq_index];
|
|
|
|
nvme_qpair_submit_request(qpair, req);
|
|
}
|
|
|
|
int32_t
|
|
spdk_nvme_ctrlr_process_io_completions(struct spdk_nvme_ctrlr *ctrlr, uint32_t max_completions)
|
|
{
|
|
nvme_assert(nvme_thread_ioq_index >= 0, ("no ioq_index assigned for thread\n"));
|
|
return nvme_qpair_process_completions(&ctrlr->ioq[nvme_thread_ioq_index], max_completions);
|
|
}
|
|
|
|
int32_t
|
|
spdk_nvme_ctrlr_process_admin_completions(struct spdk_nvme_ctrlr *ctrlr)
|
|
{
|
|
int32_t num_completions;
|
|
|
|
nvme_mutex_lock(&ctrlr->ctrlr_lock);
|
|
num_completions = nvme_qpair_process_completions(&ctrlr->adminq, 0);
|
|
nvme_mutex_unlock(&ctrlr->ctrlr_lock);
|
|
|
|
return num_completions;
|
|
}
|
|
|
|
const struct spdk_nvme_ctrlr_data *
|
|
spdk_nvme_ctrlr_get_data(struct spdk_nvme_ctrlr *ctrlr)
|
|
{
|
|
return &ctrlr->cdata;
|
|
}
|
|
|
|
uint32_t
|
|
spdk_nvme_ctrlr_get_num_ns(struct spdk_nvme_ctrlr *ctrlr)
|
|
{
|
|
return ctrlr->num_ns;
|
|
}
|
|
|
|
struct spdk_nvme_ns *
|
|
spdk_nvme_ctrlr_get_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t ns_id)
|
|
{
|
|
if (ns_id < 1 || ns_id > ctrlr->num_ns) {
|
|
return NULL;
|
|
}
|
|
|
|
return &ctrlr->ns[ns_id - 1];
|
|
}
|
|
|
|
void
|
|
spdk_nvme_ctrlr_register_aer_callback(struct spdk_nvme_ctrlr *ctrlr,
|
|
spdk_nvme_aer_cb aer_cb_fn,
|
|
void *aer_cb_arg)
|
|
{
|
|
ctrlr->aer_cb_fn = aer_cb_fn;
|
|
ctrlr->aer_cb_arg = aer_cb_arg;
|
|
}
|
|
|
|
bool
|
|
spdk_nvme_ctrlr_is_log_page_supported(struct spdk_nvme_ctrlr *ctrlr, uint8_t log_page)
|
|
{
|
|
/* No bounds check necessary, since log_page is uint8_t and log_page_supported has 256 entries */
|
|
SPDK_STATIC_ASSERT(sizeof(ctrlr->log_page_supported) == 256, "log_page_supported size mismatch");
|
|
return ctrlr->log_page_supported[log_page];
|
|
}
|
|
|
|
bool
|
|
spdk_nvme_ctrlr_is_feature_supported(struct spdk_nvme_ctrlr *ctrlr, uint8_t feature_code)
|
|
{
|
|
/* No bounds check necessary, since feature_code is uint8_t and feature_supported has 256 entries */
|
|
SPDK_STATIC_ASSERT(sizeof(ctrlr->feature_supported) == 256, "feature_supported size mismatch");
|
|
return ctrlr->feature_supported[feature_code];
|
|
}
|