6fd1cc3716
The IDENTIFY_CNS quirk was applied as part of QEMU
OCSSD handling in commit 6442451b. But it was applied
not only to the OCSSD dev ID, but also the dev ID
for non-OCSSD NVMe controllers.
Starting with QEMU 5.2, QEMU will allocate a default
256 namespaces, but only some are active (associated
with the backing disks specified by the user). QEMU
supports IDENTIFY_CNS, but since this quirk was set,
we wouldn't send a real IDENTIFY_CNS and instead
would just populate a fake list where all namespaces
were considered active. This causes breakage in
a few places - mainly where we iterate through
the active namespaces, and then are surprised that
calling spdk_nvme_ns_is_active() returns false.
It was also breaking bdev_nvme_attach_controller RPC,
since by default we can only support returning 128
names, but since all of the namespaces were deemed
active, it was trying to return 256.
Fixes #1916.
Signed-off-by: Jim Harris <james.r.harris@intel.com>
Change-Id: I4fdd27e0e36f0ac07a95f9f29aa83357e8505a45
Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/7658
Community-CI: Mellanox Build Bot
Reviewed-by: Ben Walker <benjamin.walker@intel.com>
Reviewed-by: Shuhei Matsumoto <shuhei.matsumoto.xt@hitachi.com>
Reviewed-by: Changpeng Liu <changpeng.liu@intel.com>
Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
165 lines
6.0 KiB
C
165 lines
6.0 KiB
C
/*-
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* BSD LICENSE
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*
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* Copyright (c) Intel Corporation.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "nvme_internal.h"
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struct nvme_quirk {
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struct spdk_pci_id id;
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uint64_t flags;
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};
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static const struct nvme_quirk nvme_quirks[] = {
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{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_INTEL, 0x0953, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_INTEL_QUIRK_READ_LATENCY |
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NVME_INTEL_QUIRK_WRITE_LATENCY |
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NVME_INTEL_QUIRK_STRIPING |
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NVME_QUIRK_READ_ZERO_AFTER_DEALLOCATE |
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NVME_QUIRK_DELAY_BEFORE_INIT |
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NVME_QUIRK_MINIMUM_IO_QUEUE_SIZE
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},
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{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_INTEL, 0x0A53, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_INTEL_QUIRK_READ_LATENCY |
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NVME_INTEL_QUIRK_WRITE_LATENCY |
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NVME_INTEL_QUIRK_STRIPING |
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NVME_QUIRK_READ_ZERO_AFTER_DEALLOCATE |
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NVME_QUIRK_DELAY_BEFORE_INIT |
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NVME_QUIRK_MINIMUM_IO_QUEUE_SIZE
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},
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{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_INTEL, 0x0A54, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_INTEL_QUIRK_READ_LATENCY |
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NVME_INTEL_QUIRK_WRITE_LATENCY |
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NVME_INTEL_QUIRK_STRIPING |
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NVME_QUIRK_READ_ZERO_AFTER_DEALLOCATE |
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NVME_QUIRK_MINIMUM_IO_QUEUE_SIZE
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},
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{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_INTEL, 0x0A55, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_INTEL_QUIRK_READ_LATENCY |
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NVME_INTEL_QUIRK_WRITE_LATENCY |
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NVME_INTEL_QUIRK_STRIPING |
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NVME_QUIRK_READ_ZERO_AFTER_DEALLOCATE |
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NVME_QUIRK_MINIMUM_IO_QUEUE_SIZE
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},
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{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_INTEL, 0x0B60, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_INTEL_QUIRK_READ_LATENCY |
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NVME_INTEL_QUIRK_WRITE_LATENCY |
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NVME_INTEL_QUIRK_STRIPING |
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NVME_QUIRK_MINIMUM_IO_QUEUE_SIZE |
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NVME_QUIRK_NO_SGL_FOR_DSM
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},
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{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_MEMBLAZE, 0x0540, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_QUIRK_DELAY_BEFORE_CHK_RDY
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},
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{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_SAMSUNG, 0xa821, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_QUIRK_DELAY_BEFORE_CHK_RDY
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},
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{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_SAMSUNG, 0xa822, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_QUIRK_DELAY_BEFORE_CHK_RDY
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},
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{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_VIRTUALBOX, 0x4e56, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_QUIRK_DELAY_AFTER_QUEUE_ALLOC
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},
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{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_INTEL, 0x5845, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_INTEL_QUIRK_NO_LOG_PAGES |
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NVME_QUIRK_MAXIMUM_PCI_ACCESS_WIDTH
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},
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{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_CNEXLABS, 0x1f1f, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_QUIRK_IDENTIFY_CNS |
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NVME_QUIRK_OCSSD
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},
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{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_VMWARE, 0x07f0, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_QUIRK_SHST_COMPLETE
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},
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{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_INTEL, 0x2700, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_QUIRK_OACS_SECURITY
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},
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{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_INTEL, 0x4140, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_QUIRK_MDTS_EXCLUDE_MD
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},
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{ {0x000000, 0x0000, 0x0000, 0x0000, 0x0000}, 0}
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};
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/* Compare each field. SPDK_PCI_ANY_ID in s1 matches everything */
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static bool
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pci_id_match(const struct spdk_pci_id *s1, const struct spdk_pci_id *s2)
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{
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if ((s1->class_id == SPDK_PCI_CLASS_ANY_ID || s1->class_id == s2->class_id) &&
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(s1->vendor_id == SPDK_PCI_ANY_ID || s1->vendor_id == s2->vendor_id) &&
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(s1->device_id == SPDK_PCI_ANY_ID || s1->device_id == s2->device_id) &&
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(s1->subvendor_id == SPDK_PCI_ANY_ID || s1->subvendor_id == s2->subvendor_id) &&
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(s1->subdevice_id == SPDK_PCI_ANY_ID || s1->subdevice_id == s2->subdevice_id)) {
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return true;
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}
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return false;
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}
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uint64_t
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nvme_get_quirks(const struct spdk_pci_id *id)
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{
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const struct nvme_quirk *quirk = nvme_quirks;
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SPDK_DEBUGLOG(nvme, "Searching for %04x:%04x [%04x:%04x]...\n",
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id->vendor_id, id->device_id,
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id->subvendor_id, id->subdevice_id);
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while (quirk->id.vendor_id) {
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if (pci_id_match(&quirk->id, id)) {
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SPDK_DEBUGLOG(nvme, "Matched quirk %04x:%04x [%04x:%04x]:\n",
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quirk->id.vendor_id, quirk->id.device_id,
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quirk->id.subvendor_id, quirk->id.subdevice_id);
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#define PRINT_QUIRK(quirk_flag) \
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do { \
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if (quirk->flags & (quirk_flag)) { \
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SPDK_DEBUGLOG(nvme, "Quirk enabled: %s\n", #quirk_flag); \
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} \
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} while (0)
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PRINT_QUIRK(NVME_INTEL_QUIRK_READ_LATENCY);
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PRINT_QUIRK(NVME_INTEL_QUIRK_WRITE_LATENCY);
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PRINT_QUIRK(NVME_QUIRK_DELAY_BEFORE_CHK_RDY);
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PRINT_QUIRK(NVME_INTEL_QUIRK_STRIPING);
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PRINT_QUIRK(NVME_QUIRK_DELAY_AFTER_QUEUE_ALLOC);
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PRINT_QUIRK(NVME_QUIRK_READ_ZERO_AFTER_DEALLOCATE);
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PRINT_QUIRK(NVME_QUIRK_IDENTIFY_CNS);
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PRINT_QUIRK(NVME_QUIRK_OCSSD);
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return quirk->flags;
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}
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quirk++;
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}
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SPDK_DEBUGLOG(nvme, "No quirks found.\n");
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return 0;
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}
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