391 lines
12 KiB
C
391 lines
12 KiB
C
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/*
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* Copyright (c) 2001-2003
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* Fraunhofer Institute for Open Communication Systems (FhG Fokus).
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Author: Hartmut Brandt <harti@freebsd.org>
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*
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* $FreeBSD$
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*
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* Fore PCA200E driver definitions.
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*/
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/*
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* Debug statistics of the PCA200 driver
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*/
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struct istats {
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uint32_t cmd_queue_full;
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uint32_t get_stat_errors;
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uint32_t clr_stat_errors;
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uint32_t get_prom_errors;
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uint32_t suni_reg_errors;
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uint32_t tx_queue_full;
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uint32_t tx_queue_almost_full;
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uint32_t tx_pdu2big;
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uint32_t tx_too_many_segs;
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uint32_t tx_retry;
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uint32_t fix_empty;
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uint32_t fix_addr_copy;
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uint32_t fix_addr_noext;
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uint32_t fix_addr_ext;
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uint32_t fix_len_noext;
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uint32_t fix_len_copy;
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uint32_t fix_len;
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uint32_t rx_badvc;
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uint32_t rx_closed;
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};
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/*
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* Addresses on the on-board RAM are expressed as offsets to the
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* start of that RAM.
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*/
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typedef uint32_t cardoff_t;
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/*
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* The card uses a number of queues for communication with the host.
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* Parts of the queue are located on the card (pointers to the status
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* word and the ioblk and the command blocks), the rest in host memory.
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* Each of these queues forms a ring, where the head and tail pointers are
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* managed * either by the card or the host. For the receive queue the
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* head is managed by the card (and not used altogether by the host) and the
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* tail by the host - for all other queues its the other way around.
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* The host resident parts of the queue entries contain pointers to
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* the host resident status and the host resident ioblk (the latter not for
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* the command queue) as well as DMA addresses for supply to the card.
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*/
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struct fqelem {
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cardoff_t card; /* corresponding element on card */
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bus_addr_t card_ioblk; /* ioblk address to supply to card */
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volatile uint32_t *statp; /* host status pointer */
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void *ioblk; /* host ioblk (not for commands) */
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};
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struct fqueue {
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struct fqelem *chunk; /* pointer to the element array */
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int head; /* queue head */
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int tail; /* queue tail */
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};
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/*
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* Queue manipulation macros
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*/
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#define NEXT_QUEUE_ENTRY(HEAD,LEN) ((HEAD) = ((HEAD) + 1) % LEN)
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#define GET_QUEUE(Q,TYPE,IDX) (&((TYPE *)(Q).chunk)[(IDX)])
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/*
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* Now define structures for the different queues. Each of these structures
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* must start with a struct fqelem.
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*/
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struct txqueue { /* transmit queue element */
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struct fqelem q;
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struct mbuf *m; /* the chain we are transmitting */
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bus_dmamap_t map; /* map for the packet */
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};
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struct rxqueue { /* receive queue element */
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struct fqelem q;
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};
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struct supqueue { /* supply queue element */
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struct fqelem q;
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};
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struct cmdqueue;
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struct fatm_softc;
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typedef void (*completion_cb)(struct fatm_softc *, struct cmdqueue *);
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struct cmdqueue { /* command queue element */
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struct fqelem q;
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completion_cb cb; /* call on command completion */
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int error; /* set if error occured */
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};
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/*
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* Card-DMA-able memory is managed by means of the bus_dma* functions.
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* To allocate a chunk of memory with a specific size and alignment one
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* has to:
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* 1. create a DMA tag
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* 2. allocate the memory
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* 3. load the memory into a map.
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* This finally gives the physical address that can be given to the card.
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* The card can DMA the entire 32-bit space without boundaries. We assume,
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* that all the allocations can be mapped in one contiguous segment. This
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* may be wrong in the future if we have more than 32 bit addresses.
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* Allocation is done at attach time and managed by the following structure.
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*
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* This could be done easier with the NetBSD bus_dma* functions. They appear
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* to be more useful and consistent.
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*/
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struct fatm_mem {
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u_int size; /* size */
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u_int align; /* alignment */
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bus_dma_tag_t dmat; /* DMA tag */
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void *mem; /* memory block */
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bus_addr_t paddr; /* pysical address */
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bus_dmamap_t map; /* map */
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};
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/*
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* Each of these structures describes one receive buffer while the buffer
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* is on the card or in the receive return queue. These structures are
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* allocated at initialisation time together with the DMA maps. The handle that
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* is given to the card is the index into the array of these structures.
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*/
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struct rbuf {
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struct mbuf *m; /* the mbuf while we are on the card */
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bus_dmamap_t map; /* the map */
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LIST_ENTRY(rbuf) link; /* the free list link */
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};
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LIST_HEAD(rbuf_list, rbuf);
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/*
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* The driver maintains a list of all open VCCs. Because we
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* use only VPI=0 and a maximum VCI of 1024, the list is rather an array
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* than a list. We also store the atm pseudoheader flags here and the
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* rxhand (aka. protocol block).
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*/
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struct card_vcc {
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void *rxhand;
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uint32_t pcr;
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uint32_t flags;
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uint8_t aal;
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uint8_t traffic;
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};
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#define FATM_VCC_OPEN 0x00010000 /* is open */
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#define FATM_VCC_TRY_OPEN 0x00020000 /* is currently opening */
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#define FATM_VCC_TRY_CLOSE 0x00040000 /* is currently closing */
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#define FATM_VCC_BUSY 0x00070000 /* one of the above */
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/*
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* Finally the softc structure
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*/
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struct fatm_softc {
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struct ifatm ifatm; /* common part */
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struct mtx mtx; /* lock this structure */
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struct ifmedia media; /* media */
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int init_state; /* initialisation step */
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int memid; /* resource id for card memory */
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struct resource *memres; /* resource for card memory */
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bus_space_handle_t memh; /* handle for card memory */
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bus_space_tag_t memt; /* tag for card memory */
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int irqid; /* resource id for interrupt */
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struct resource *irqres; /* resource for interrupt */
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void *ih; /* interrupt handler */
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bus_dma_tag_t parent_dmat; /* parent DMA tag */
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struct fatm_mem stat_mem; /* memory for status blocks */
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struct fatm_mem txq_mem; /* TX descriptor queue */
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struct fatm_mem rxq_mem; /* RX descriptor queue */
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struct fatm_mem s1q_mem; /* Small buffer 1 queue */
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struct fatm_mem l1q_mem; /* Large buffer 1 queue */
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struct fatm_mem prom_mem; /* PROM memory */
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struct fqueue txqueue; /* transmission queue */
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struct fqueue rxqueue; /* receive queue */
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struct fqueue s1queue; /* SMALL S1 queue */
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struct fqueue l1queue; /* LARGE S1 queue */
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struct fqueue cmdqueue; /* command queue */
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/* fields for access to the SUNI registers */
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struct fatm_mem reg_mem; /* DMAable memory for readregs */
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struct cv cv_regs; /* to serialize access to reg_mem */
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/* fields for access to statistics */
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struct fatm_mem sadi_mem; /* sadistics memory */
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struct cv cv_stat; /* to serialize access to sadi_mem */
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u_int flags;
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#define FATM_STAT_INUSE 0x0001
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#define FATM_REGS_INUSE 0x0002
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u_int txcnt; /* number of used transmit desc */
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int retry_tx; /* keep mbufs in queue if full */
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struct card_vcc *vccs; /* table of vccs */
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int open_vccs; /* number of vccs in use */
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int small_cnt; /* number of buffers owned by card */
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int large_cnt; /* number of buffers owned by card */
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/* receiving */
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struct rbuf *rbufs; /* rbuf array */
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struct rbuf_list rbuf_free; /* free rbufs list */
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struct rbuf_list rbuf_used; /* used rbufs list */
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u_int rbuf_total; /* total number of buffs */
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bus_dma_tag_t rbuf_tag; /* tag for rbuf mapping */
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/* transmission */
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bus_dma_tag_t tx_tag; /* transmission tag */
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uint32_t heartbeat; /* last heartbeat */
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u_int stop_cnt; /* how many times checked */
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struct istats istats; /* internal statistics */
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/* SUNI state */
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struct utopia utopia;
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/* sysctl support */
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struct sysctl_ctx_list sysctl_ctx;
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struct sysctl_oid *sysctl_tree;
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#ifdef FATM_DEBUG
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/* debugging */
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u_int debug;
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#endif
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};
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#ifndef FATM_DEBUG
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#define FATM_LOCK(SC) mtx_lock(&(SC)->mtx)
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#define FATM_UNLOCK(SC) mtx_unlock(&(SC)->mtx)
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#else
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#define FATM_LOCK(SC) do { \
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DBG(SC, LOCK, ("locking in line %d", __LINE__)); \
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mtx_lock(&(SC)->mtx); \
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} while (0)
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#define FATM_UNLOCK(SC) do { \
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DBG(SC, LOCK, ("unlocking in line %d", __LINE__)); \
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mtx_unlock(&(SC)->mtx); \
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} while (0)
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#endif
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#define FATM_CHECKLOCK(SC) mtx_assert(&sc->mtx, MA_OWNED)
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/*
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* Macros to access host memory fields that are also access by the card.
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* These fields need to little-endian always.
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*/
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#define H_GETSTAT(STATP) (le32toh(*(STATP)))
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#define H_SETSTAT(STATP, S) do { *(STATP) = htole32(S); } while (0)
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#define H_SETDESC(DESC, D) do { (DESC) = htole32(D); } while (0)
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#ifdef notyet
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#define H_SYNCSTAT_POSTREAD(SC, P) \
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bus_dmamap_sync_size((SC)->stat_mem.dmat, \
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(SC)->stat_mem.map, \
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(volatile char *)(P) - (volatile char *)(SC)->stat_mem.mem, \
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sizeof(volatile uint32_t), BUS_DMASYNC_POSTREAD)
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#define H_SYNCSTAT_PREWRITE(SC, P) \
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bus_dmamap_sync_size((SC)->stat_mem.dmat, \
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(SC)->stat_mem.map, \
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(volatile char *)(P) - (volatile char *)(SC)->stat_mem.mem, \
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sizeof(volatile uint32_t), BUS_DMASYNC_PREWRITE)
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#define H_SYNCQ_PREWRITE(M, P, SZ) \
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bus_dmamap_sync_size((M)->dmat, (M)->map, \
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(volatile char *)(P) - (volatile char *)(M)->mem, (SZ), \
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BUS_DMASYNC_PREWRITE)
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#define H_SYNCQ_POSTREAD(M, P, SZ) \
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bus_dmamap_sync_size((M)->dmat, (M)->map, \
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(volatile char *)(P) - (volatile char *)(M)->mem, (SZ), \
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BUS_DMASYNC_POSTREAD)
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#else
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#define H_SYNCSTAT_POSTREAD(SC, P) do { } while (0)
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#define H_SYNCSTAT_PREWRITE(SC, P) do { } while (0)
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#define H_SYNCQ_PREWRITE(M, P, SZ) do { } while (0)
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#define H_SYNCQ_POSTREAD(M, P, SZ) do { } while (0)
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#endif
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/*
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* Macros to manipulate VPVCs
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*/
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#define MKVPVC(VPI,VCI) (((VPI) << 16) | (VCI))
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#define GETVPI(VPVC) (((VPVC) >> 16) & 0xff)
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#define GETVCI(VPVC) ((VPVC) & 0xffff)
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/*
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* These macros encapsulate the bus_space functions for better readabiliy.
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*/
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#define WRITE4(SC, OFF, VAL) bus_space_write_4(SC->memt, SC->memh, OFF, VAL)
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#define WRITE1(SC, OFF, VAL) bus_space_write_1(SC->memt, SC->memh, OFF, VAL)
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#define READ4(SC, OFF) bus_space_read_4(SC->memt, SC->memh, OFF)
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#define READ1(SC, OFF) bus_space_read_1(SC->memt, SC->memh, OFF)
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#define BARRIER_R(SC) \
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bus_space_barrier(SC->memt, SC->memh, 0, FATMO_END, \
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BUS_SPACE_BARRIER_READ)
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#define BARRIER_W(SC) \
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bus_space_barrier(SC->memt, SC->memh, 0, FATMO_END, \
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BUS_SPACE_BARRIER_WRITE)
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#define BARRIER_RW(SC) \
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bus_space_barrier(SC->memt, SC->memh, 0, FATMO_END, \
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BUS_SPACE_BARRIER_WRITE|BUS_SPACE_BARRIER_READ)
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#ifdef FATM_DEBUG
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#define DBG(SC, FL, PRINT) do { \
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if ((SC)->debug & DBG_##FL) { \
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if_printf(&(SC)->ifatm.ifnet, "%s: ", __func__); \
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printf PRINT; \
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printf("\n"); \
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} \
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} while (0)
|
||
|
|
#define DBGC(SC, FL, PRINT) do { \
|
||
|
|
if ((SC)->debug & DBG_##FL) \
|
||
|
|
printf PRINT; \
|
||
|
|
} while (0)
|
||
|
|
|
||
|
|
enum {
|
||
|
|
DBG_RCV = 0x0001,
|
||
|
|
DBG_XMIT = 0x0002,
|
||
|
|
DBG_VCC = 0x0004,
|
||
|
|
DBG_IOCTL = 0x0008,
|
||
|
|
DBG_ATTACH = 0x0010,
|
||
|
|
DBG_INIT = 0x0020,
|
||
|
|
DBG_DMA = 0x0040,
|
||
|
|
DBG_BEAT = 0x0080,
|
||
|
|
DBG_UART = 0x0100,
|
||
|
|
DBG_LOCK = 0x0200,
|
||
|
|
|
||
|
|
DBG_ALL = 0xffff
|
||
|
|
};
|
||
|
|
|
||
|
|
#else
|
||
|
|
#define DBG(SC, FL, PRINT)
|
||
|
|
#define DBGC(SC, FL, PRINT)
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Configuration.
|
||
|
|
*
|
||
|
|
* This section contains tunable parameters and dependend defines.
|
||
|
|
*/
|
||
|
|
#define FATM_CMD_QLEN 16 /* command queue length */
|
||
|
|
#ifndef TEST_DMA_SYNC
|
||
|
|
#define FATM_TX_QLEN 128 /* transmit queue length */
|
||
|
|
#define FATM_RX_QLEN 64 /* receive queue length */
|
||
|
|
#else
|
||
|
|
#define FATM_TX_QLEN 8 /* transmit queue length */
|
||
|
|
#define FATM_RX_QLEN 8 /* receive queue length */
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#define SMALL_SUPPLY_QLEN 16
|
||
|
|
#define SMALL_POOL_SIZE 256
|
||
|
|
#define SMALL_SUPPLY_BLKSIZE 8
|
||
|
|
|
||
|
|
#define LARGE_SUPPLY_QLEN 16
|
||
|
|
#define LARGE_POOL_SIZE 128
|
||
|
|
#define LARGE_SUPPLY_BLKSIZE 8
|