2015-03-23 11:54:56 +00:00
|
|
|
/*-
|
|
|
|
* Copyright (c) 1999 Luoqi Chen <luoqi@freebsd.org>
|
|
|
|
* All rights reserved.
|
|
|
|
*
|
|
|
|
* Redistribution and use in source and binary forms, with or without
|
|
|
|
* modification, are permitted provided that the following conditions
|
|
|
|
* are met:
|
|
|
|
* 1. Redistributions of source code must retain the above copyright
|
|
|
|
* notice, this list of conditions and the following disclaimer.
|
|
|
|
* 2. Redistributions in binary form must reproduce the above copyright
|
|
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
|
|
* documentation and/or other materials provided with the distribution.
|
|
|
|
*
|
|
|
|
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
|
|
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
|
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
|
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
|
|
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
|
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
|
|
|
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
|
|
|
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
|
|
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
|
|
|
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
|
|
|
* SUCH DAMAGE.
|
|
|
|
*
|
|
|
|
* from: FreeBSD: src/sys/i386/include/globaldata.h,v 1.27 2001/04/27
|
|
|
|
* $FreeBSD$
|
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef _MACHINE_PCPU_H_
|
|
|
|
#define _MACHINE_PCPU_H_
|
|
|
|
|
|
|
|
#include <machine/cpu.h>
|
|
|
|
#include <machine/cpufunc.h>
|
|
|
|
|
|
|
|
#define ALT_STACK_SIZE 128
|
|
|
|
|
2018-01-12 14:01:38 +00:00
|
|
|
typedef int (*pcpu_bp_harden)(void);
|
2018-07-31 15:08:02 +00:00
|
|
|
typedef int (*pcpu_ssbd)(int);
|
2019-10-30 10:51:24 +00:00
|
|
|
struct debug_monitor_state;
|
2018-01-12 14:01:38 +00:00
|
|
|
|
2015-03-23 11:54:56 +00:00
|
|
|
#define PCPU_MD_FIELDS \
|
Utilize ASIDs to reduce both the direct and indirect costs of context
switching. The indirect costs being unnecessary TLB misses that are
incurred when ASIDs are not used. In fact, currently, when we perform a
context switch on one processor, we issue a broadcast TLB invalidation that
flushes the TLB contents on every processor.
Mark all user-space ("ttbr0") page table entries with the non-global flag so
that they are cached in the TLB under their ASID.
Correct an error in pmap_pinit0(). The pointer to the root of the page
table was being initialized to the root of the kernel-space page table
rather than a user-space page table. However, the root of the page table
that was being cached in process 0's md_l0addr field correctly pointed to a
user-space page table. As long as ASIDs weren't being used, this was
harmless, except that it led to some unnecessary page table switches in
pmap_switch(). Specifically, other kernel processes besides process 0 would
have their md_l0addr field set to the root of the kernel-space page table,
and so pmap_switch() would actually change page tables when switching
between process 0 and other kernel processes.
Implement a workaround for Cavium erratum 27456 affecting ThunderX machines.
(I would like to thank andrew@ for providing the code to detect the affected
machines.)
Address integer overflow in the definition of TCR_ASID_16.
Setup TCR according to the PARange and ASIDBits fields from
ID_AA64MMFR0_EL1. Previously, TCR_ASID_16 was unconditionally set.
Modify build_l1_block_pagetable so that lower attributes, such as ATTR_nG,
can be specified as a parameter.
Eliminate some unused code.
Earlier versions were tested to varying degrees by: andrew, emaste, markj
MFC after: 3 weeks
Differential Revision: https://reviews.freebsd.org/D21922
2019-11-03 17:45:30 +00:00
|
|
|
u_int pc_acpi_id; /* ACPI CPU id */ \
|
|
|
|
u_int pc_midr; /* stored MIDR value */ \
|
2016-09-02 10:13:51 +00:00
|
|
|
uint64_t pc_clock; \
|
2018-01-12 14:01:38 +00:00
|
|
|
pcpu_bp_harden pc_bp_harden; \
|
2018-07-31 12:53:27 +00:00
|
|
|
pcpu_ssbd pc_ssbd; \
|
Utilize ASIDs to reduce both the direct and indirect costs of context
switching. The indirect costs being unnecessary TLB misses that are
incurred when ASIDs are not used. In fact, currently, when we perform a
context switch on one processor, we issue a broadcast TLB invalidation that
flushes the TLB contents on every processor.
Mark all user-space ("ttbr0") page table entries with the non-global flag so
that they are cached in the TLB under their ASID.
Correct an error in pmap_pinit0(). The pointer to the root of the page
table was being initialized to the root of the kernel-space page table
rather than a user-space page table. However, the root of the page table
that was being cached in process 0's md_l0addr field correctly pointed to a
user-space page table. As long as ASIDs weren't being used, this was
harmless, except that it led to some unnecessary page table switches in
pmap_switch(). Specifically, other kernel processes besides process 0 would
have their md_l0addr field set to the root of the kernel-space page table,
and so pmap_switch() would actually change page tables when switching
between process 0 and other kernel processes.
Implement a workaround for Cavium erratum 27456 affecting ThunderX machines.
(I would like to thank andrew@ for providing the code to detect the affected
machines.)
Address integer overflow in the definition of TCR_ASID_16.
Setup TCR according to the PARange and ASIDBits fields from
ID_AA64MMFR0_EL1. Previously, TCR_ASID_16 was unconditionally set.
Modify build_l1_block_pagetable so that lower attributes, such as ATTR_nG,
can be specified as a parameter.
Eliminate some unused code.
Earlier versions were tested to varying degrees by: andrew, emaste, markj
MFC after: 3 weeks
Differential Revision: https://reviews.freebsd.org/D21922
2019-11-03 17:45:30 +00:00
|
|
|
struct pmap *pc_curpmap; \
|
2020-05-27 08:00:38 +00:00
|
|
|
struct pmap *pc_curvmpmap; \
|
Utilize ASIDs to reduce both the direct and indirect costs of context
switching. The indirect costs being unnecessary TLB misses that are
incurred when ASIDs are not used. In fact, currently, when we perform a
context switch on one processor, we issue a broadcast TLB invalidation that
flushes the TLB contents on every processor.
Mark all user-space ("ttbr0") page table entries with the non-global flag so
that they are cached in the TLB under their ASID.
Correct an error in pmap_pinit0(). The pointer to the root of the page
table was being initialized to the root of the kernel-space page table
rather than a user-space page table. However, the root of the page table
that was being cached in process 0's md_l0addr field correctly pointed to a
user-space page table. As long as ASIDs weren't being used, this was
harmless, except that it led to some unnecessary page table switches in
pmap_switch(). Specifically, other kernel processes besides process 0 would
have their md_l0addr field set to the root of the kernel-space page table,
and so pmap_switch() would actually change page tables when switching
between process 0 and other kernel processes.
Implement a workaround for Cavium erratum 27456 affecting ThunderX machines.
(I would like to thank andrew@ for providing the code to detect the affected
machines.)
Address integer overflow in the definition of TCR_ASID_16.
Setup TCR according to the PARange and ASIDBits fields from
ID_AA64MMFR0_EL1. Previously, TCR_ASID_16 was unconditionally set.
Modify build_l1_block_pagetable so that lower attributes, such as ATTR_nG,
can be specified as a parameter.
Eliminate some unused code.
Earlier versions were tested to varying degrees by: andrew, emaste, markj
MFC after: 3 weeks
Differential Revision: https://reviews.freebsd.org/D21922
2019-11-03 17:45:30 +00:00
|
|
|
u_int pc_bcast_tlbi_workaround; \
|
2022-08-25 08:28:28 +00:00
|
|
|
/* Store as two u_int values to preserve KBI */ \
|
|
|
|
u_int pc_mpidr_low; /* lower MPIDR 32 bits */ \
|
|
|
|
u_int pc_mpidr_high; /* upper MPIDR 32 bits */ \
|
|
|
|
char __pad[197]
|
2015-03-23 11:54:56 +00:00
|
|
|
|
|
|
|
#ifdef _KERNEL
|
|
|
|
|
|
|
|
struct pcb;
|
|
|
|
struct pcpu;
|
|
|
|
|
2021-01-11 15:43:39 +00:00
|
|
|
register struct pcpu *pcpup __asm ("x18");
|
2015-03-23 11:54:56 +00:00
|
|
|
|
2022-03-08 11:38:51 +00:00
|
|
|
static inline struct pcpu *
|
|
|
|
get_pcpu(void)
|
|
|
|
{
|
|
|
|
struct pcpu *pcpu;
|
|
|
|
|
|
|
|
__asm __volatile("mov %0, x18" : "=&r"(pcpu));
|
|
|
|
return (pcpu);
|
|
|
|
}
|
2015-03-23 11:54:56 +00:00
|
|
|
|
|
|
|
static inline struct thread *
|
|
|
|
get_curthread(void)
|
|
|
|
{
|
|
|
|
struct thread *td;
|
|
|
|
|
|
|
|
__asm __volatile("ldr %0, [x18]" : "=&r"(td));
|
|
|
|
return (td);
|
|
|
|
}
|
|
|
|
|
|
|
|
#define curthread get_curthread()
|
|
|
|
|
2021-01-11 15:43:39 +00:00
|
|
|
#define PCPU_GET(member) (pcpup->pc_ ## member)
|
|
|
|
#define PCPU_ADD(member, value) (pcpup->pc_ ## member += (value))
|
|
|
|
#define PCPU_PTR(member) (&pcpup->pc_ ## member)
|
|
|
|
#define PCPU_SET(member,value) (pcpup->pc_ ## member = (value))
|
2015-03-23 11:54:56 +00:00
|
|
|
|
2022-08-25 08:28:28 +00:00
|
|
|
#define PCPU_GET_MPIDR(pc) \
|
|
|
|
((((uint64_t)((pc)->pc_mpidr_high)) << 32) | ((pc)->pc_mpidr_low))
|
|
|
|
|
2015-03-23 11:54:56 +00:00
|
|
|
#endif /* _KERNEL */
|
|
|
|
|
|
|
|
#endif /* !_MACHINE_PCPU_H_ */
|