2013-11-12 05:58:23 +00:00
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/*-
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* Copyright (c) 2013 Cedric GROSS <cg@cgross.info>
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* Copyright (c) 2011 Intel Corporation
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#ifndef __IF_IWN_CHIP_CFG_H__
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#define __IF_IWN_CHIP_CFG_H__
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/* ==========================================================================
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* NIC PARAMETERS
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*
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* ==========================================================================
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*/
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/*
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* Flags for managing calibration result. See calib_need
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* in iwn_base_params struct
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*
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* These are bitmasks that determine which indexes in the calibcmd
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* array are pushed up.
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*/
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#define IWN_FLG_NEED_PHY_CALIB_DC (1<<0)
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#define IWN_FLG_NEED_PHY_CALIB_LO (1<<1)
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#define IWN_FLG_NEED_PHY_CALIB_TX_IQ (1<<2)
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#define IWN_FLG_NEED_PHY_CALIB_TX_IQ_PERIODIC (1<<3)
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#define IWN_FLG_NEED_PHY_CALIB_BASE_BAND (1<<4)
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/*
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* These aren't (yet) included in the calibcmd array, but
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* are used as flags for which calibrations to use.
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*
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* XXX I think they should be named differently and
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* stuffed in a different member in the config struct!
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*/
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#define IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET (1<<5)
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#define IWN_FLG_NEED_PHY_CALIB_CRYSTAL (1<<6)
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#define IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2 (1<<7)
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2013-12-07 06:45:09 +00:00
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/*
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* Each chip has a different threshold for PLCP errors that should trigger a
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* retune.
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*/
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#define IWN_PLCP_ERR_DEFAULT_THRESHOLD 50
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#define IWN_PLCP_ERR_LONG_THRESHOLD 100
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#define IWN_PLCP_ERR_EXT_LONG_THRESHOLD 200
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2013-11-12 05:58:23 +00:00
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/*
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* Define some parameters for managing different NIC.
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* Refer to linux specific file like iwl-xxxx.c to determine correct value
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* for NIC.
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*
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* @max_ll_items: max number of OTP blocks
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* @shadow_ram_support: shadow support for OTP memory
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* @shadow_reg_enable: HW shadhow register bit
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* @no_idle_support: do not support idle mode
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* @advanced_bt_coexist : Advanced BT management
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* @bt_session_2 : NIC need a new struct for configure BT coexistence. Needed
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* only if advanced_bt_coexist is true
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* @bt_sco_disable :
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* @additional_nic_config: For 6005 series
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* @iq_invert : ? But need it for N 2000 series
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* @regulatory_bands : XXX
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* @enhanced_TX_power : EEPROM Has advanced TX power options. Set 'True'
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* if update_enhanced_txpower = iwl_eeprom_enhanced_txpower.
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* See iwl-agn-devices.c file to determine that(enhanced_txpower)
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* @need_temp_offset_calib : Need to compute some temp offset for calibration.
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* @calib_need : Use IWN_FLG_NEED_PHY_CALIB_* flags to specify which
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* calibration data ucode need. See calib_init_cfg in iwl-xxxx.c
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* linux kernel file
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* @support_hostap: Define IEEE80211_C_HOSTAP for ic_caps
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* @no_multi_vaps: See iwn_vap_create
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* @additional_gp_drv_bit : Specific bit to defined during nic_config
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* @bt_mode: BT configuration mode
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*/
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enum bt_mode_enum {
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IWN_BT_NONE,
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IWN_BT_SIMPLE,
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IWN_BT_ADVANCED
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};
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struct iwn_base_params {
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uint32_t pll_cfg_val;
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const uint16_t max_ll_items;
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#define IWN_OTP_MAX_LL_ITEMS_1000 (3) /* OTP blocks for 1000 */
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#define IWN_OTP_MAX_LL_ITEMS_6x00 (4) /* OTP blocks for 6x00 */
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#define IWN_OTP_MAX_LL_ITEMS_6x50 (7) /* OTP blocks for 6x50 */
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#define IWN_OTP_MAX_LL_ITEMS_2x00 (4) /* OTP blocks for 2x00 */
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const bool shadow_ram_support;
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const bool shadow_reg_enable;
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const bool bt_session_2;
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const bool bt_sco_disable;
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const bool additional_nic_config;
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const uint32_t *regulatory_bands;
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const bool enhanced_TX_power;
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const uint16_t calib_need;
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const bool support_hostap;
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const bool no_multi_vaps;
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uint8_t additional_gp_drv_bit;
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enum bt_mode_enum bt_mode;
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2013-12-07 06:45:09 +00:00
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uint32_t plcp_err_threshold;
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2013-11-12 05:58:23 +00:00
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};
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static const struct iwn_base_params iwn5000_base_params = {
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.pll_cfg_val = IWN_ANA_PLL_INIT, /* pll_cfg_val; */
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.max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00, /* max_ll_items */
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2014-06-14 06:54:03 +00:00
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.shadow_ram_support = false, /* shadow_ram_support */
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2013-11-12 05:58:23 +00:00
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.shadow_reg_enable = false, /* shadow_reg_enable */
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.bt_session_2 = false, /* bt_session_2 */
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.bt_sco_disable = true, /* bt_sco_disable */
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.additional_nic_config = false, /* additional_nic_config */
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.regulatory_bands = iwn5000_regulatory_bands, /* regulatory_bands */
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.enhanced_TX_power = false, /* enhanced_TX_power */
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.calib_need =
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( IWN_FLG_NEED_PHY_CALIB_LO
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| IWN_FLG_NEED_PHY_CALIB_TX_IQ_PERIODIC
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| IWN_FLG_NEED_PHY_CALIB_TX_IQ
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| IWN_FLG_NEED_PHY_CALIB_BASE_BAND ),
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.support_hostap = false, /* support_hostap */
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.no_multi_vaps = true, /* no_multi_vaps */
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.additional_gp_drv_bit = IWN_GP_DRIVER_NONE, /* additional_gp_drv_bit */
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.bt_mode = IWN_BT_NONE, /* bt_mode */
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2013-12-07 06:45:09 +00:00
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.plcp_err_threshold = IWN_PLCP_ERR_LONG_THRESHOLD,
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2013-11-12 05:58:23 +00:00
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};
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/*
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* 4965 support
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*/
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static const struct iwn_base_params iwn4965_base_params = {
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.pll_cfg_val = 0, /* pll_cfg_val; */
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.max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00, /* max_ll_items - ignored for 4965 */
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.shadow_ram_support = true, /* shadow_ram_support */
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.shadow_reg_enable = false, /* shadow_reg_enable */
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.bt_session_2 = false, /* bt_session_2 XXX unknown? */
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.bt_sco_disable = true, /* bt_sco_disable XXX unknown? */
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.additional_nic_config = false, /* additional_nic_config - not for 4965 */
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.regulatory_bands = iwn5000_regulatory_bands, /* regulatory_bands */
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.enhanced_TX_power = false, /* enhanced_TX_power - not for 4965 */
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.calib_need =
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(IWN_FLG_NEED_PHY_CALIB_DC
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| IWN_FLG_NEED_PHY_CALIB_LO
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| IWN_FLG_NEED_PHY_CALIB_TX_IQ_PERIODIC
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| IWN_FLG_NEED_PHY_CALIB_TX_IQ
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| IWN_FLG_NEED_PHY_CALIB_BASE_BAND ),
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.support_hostap = false, /* support_hostap - XXX should work on fixing! */
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.no_multi_vaps = true, /* no_multi_vaps - XXX should work on fixing! */
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.additional_gp_drv_bit = IWN_GP_DRIVER_NONE, /* additional_gp_drv_bit */
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.bt_mode = IWN_BT_SIMPLE, /* bt_mode */
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2013-12-07 06:45:09 +00:00
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.plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD,
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2013-11-12 05:58:23 +00:00
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};
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static const struct iwn_base_params iwn2000_base_params = {
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.pll_cfg_val = 0,
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.max_ll_items = IWN_OTP_MAX_LL_ITEMS_2x00,
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.shadow_ram_support = true,
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.shadow_reg_enable = false,
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.bt_session_2 = false,
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.bt_sco_disable = true,
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.additional_nic_config = false,
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.regulatory_bands = iwn2030_regulatory_bands,
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.enhanced_TX_power = true,
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.calib_need =
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(IWN_FLG_NEED_PHY_CALIB_DC
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| IWN_FLG_NEED_PHY_CALIB_LO
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| IWN_FLG_NEED_PHY_CALIB_TX_IQ
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| IWN_FLG_NEED_PHY_CALIB_BASE_BAND
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| IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2 ),
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.support_hostap = true,
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.no_multi_vaps = false,
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.additional_gp_drv_bit = IWN_GP_DRIVER_REG_BIT_RADIO_IQ_INVERT,
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2013-11-16 04:29:02 +00:00
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.bt_mode = IWN_BT_NONE,
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2013-12-07 06:45:09 +00:00
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.plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD,
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2013-11-12 05:58:23 +00:00
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};
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static const struct iwn_base_params iwn2030_base_params = {
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.pll_cfg_val = 0,
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.max_ll_items = IWN_OTP_MAX_LL_ITEMS_2x00,
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.shadow_ram_support = true,
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.shadow_reg_enable = false, /* XXX check? */
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.bt_session_2 = true,
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.bt_sco_disable = true,
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.additional_nic_config = false,
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.regulatory_bands = iwn2030_regulatory_bands,
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.enhanced_TX_power = true,
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.calib_need =
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(IWN_FLG_NEED_PHY_CALIB_DC
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| IWN_FLG_NEED_PHY_CALIB_LO
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| IWN_FLG_NEED_PHY_CALIB_TX_IQ
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| IWN_FLG_NEED_PHY_CALIB_BASE_BAND
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| IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2 ),
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.support_hostap = true,
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.no_multi_vaps = false,
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.additional_gp_drv_bit = IWN_GP_DRIVER_REG_BIT_RADIO_IQ_INVERT,
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.bt_mode = IWN_BT_ADVANCED,
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.plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD,
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2013-11-12 05:58:23 +00:00
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};
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static const struct iwn_base_params iwn1000_base_params = {
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.pll_cfg_val = IWN_ANA_PLL_INIT,
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.max_ll_items = IWN_OTP_MAX_LL_ITEMS_1000,
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.shadow_ram_support = false,
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.shadow_reg_enable = false, /* XXX check? */
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.bt_session_2 = false,
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.bt_sco_disable = false,
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.additional_nic_config = false,
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.regulatory_bands = iwn5000_regulatory_bands,
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.enhanced_TX_power = false,
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.calib_need =
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2014-05-10 05:56:10 +00:00
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( IWN_FLG_NEED_PHY_CALIB_LO
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| IWN_FLG_NEED_PHY_CALIB_TX_IQ_PERIODIC
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2013-11-12 05:58:23 +00:00
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| IWN_FLG_NEED_PHY_CALIB_TX_IQ
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2014-05-10 05:56:10 +00:00
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| IWN_FLG_NEED_PHY_CALIB_BASE_BAND
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),
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2013-11-12 05:58:23 +00:00
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.support_hostap = false,
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.no_multi_vaps = true,
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.additional_gp_drv_bit = IWN_GP_DRIVER_NONE,
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2014-05-10 05:56:10 +00:00
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/* XXX 1000 - no BT */
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.bt_mode = IWN_BT_SIMPLE,
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2013-12-07 06:45:09 +00:00
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.plcp_err_threshold = IWN_PLCP_ERR_EXT_LONG_THRESHOLD,
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2013-11-12 05:58:23 +00:00
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};
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static const struct iwn_base_params iwn_6000_base_params = {
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.pll_cfg_val = 0,
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.max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00,
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.shadow_ram_support = true,
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.shadow_reg_enable = true,
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.bt_session_2 = false,
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.bt_sco_disable = false,
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.additional_nic_config = false,
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.regulatory_bands = iwn6000_regulatory_bands,
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.enhanced_TX_power = true,
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.calib_need =
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(IWN_FLG_NEED_PHY_CALIB_DC
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| IWN_FLG_NEED_PHY_CALIB_LO
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| IWN_FLG_NEED_PHY_CALIB_TX_IQ
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| IWN_FLG_NEED_PHY_CALIB_BASE_BAND ),
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.support_hostap = false,
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.no_multi_vaps = true,
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.additional_gp_drv_bit = IWN_GP_DRIVER_NONE,
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.bt_mode = IWN_BT_SIMPLE,
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2013-12-07 06:45:09 +00:00
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.plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD,
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2013-11-12 05:58:23 +00:00
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};
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static const struct iwn_base_params iwn_6000i_base_params = {
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.pll_cfg_val = 0,
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.max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00,
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.shadow_ram_support = true,
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.shadow_reg_enable = true,
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.bt_session_2 = false,
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.bt_sco_disable = true,
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.additional_nic_config = false,
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.regulatory_bands = iwn6000_regulatory_bands,
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.enhanced_TX_power = true,
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.calib_need =
|
|
|
|
|
(IWN_FLG_NEED_PHY_CALIB_DC
|
|
|
|
|
| IWN_FLG_NEED_PHY_CALIB_LO
|
|
|
|
|
| IWN_FLG_NEED_PHY_CALIB_TX_IQ
|
|
|
|
|
| IWN_FLG_NEED_PHY_CALIB_BASE_BAND ),
|
|
|
|
|
.support_hostap = false,
|
|
|
|
|
.no_multi_vaps = true,
|
|
|
|
|
.additional_gp_drv_bit = IWN_GP_DRIVER_NONE,
|
|
|
|
|
.bt_mode = IWN_BT_SIMPLE,
|
2013-12-07 06:45:09 +00:00
|
|
|
.plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD,
|
2013-11-12 05:58:23 +00:00
|
|
|
};
|
|
|
|
|
static const struct iwn_base_params iwn_6000g2_base_params = {
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|
|
|
|
.pll_cfg_val = 0,
|
|
|
|
|
.max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00,
|
|
|
|
|
.shadow_ram_support = true,
|
|
|
|
|
.shadow_reg_enable = true,
|
|
|
|
|
.bt_session_2 = false,
|
|
|
|
|
.bt_sco_disable = true,
|
|
|
|
|
.additional_nic_config = false,
|
|
|
|
|
.regulatory_bands = iwn6000_regulatory_bands,
|
|
|
|
|
.enhanced_TX_power = true,
|
|
|
|
|
.calib_need =
|
|
|
|
|
(IWN_FLG_NEED_PHY_CALIB_DC
|
|
|
|
|
| IWN_FLG_NEED_PHY_CALIB_LO
|
|
|
|
|
| IWN_FLG_NEED_PHY_CALIB_TX_IQ
|
|
|
|
|
| IWN_FLG_NEED_PHY_CALIB_BASE_BAND
|
|
|
|
|
| IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET ),
|
|
|
|
|
.support_hostap = false,
|
|
|
|
|
.no_multi_vaps = true,
|
|
|
|
|
.additional_gp_drv_bit = 0,
|
|
|
|
|
.bt_mode = IWN_BT_SIMPLE,
|
2013-12-07 06:45:09 +00:00
|
|
|
.plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD,
|
2013-11-12 05:58:23 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct iwn_base_params iwn_6050_base_params = {
|
|
|
|
|
.pll_cfg_val = 0,
|
|
|
|
|
.max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x50,
|
|
|
|
|
.shadow_ram_support = true,
|
|
|
|
|
.shadow_reg_enable = true,
|
|
|
|
|
.bt_session_2 = false,
|
|
|
|
|
.bt_sco_disable = true,
|
|
|
|
|
.additional_nic_config = true,
|
|
|
|
|
.regulatory_bands = iwn6000_regulatory_bands,
|
|
|
|
|
.enhanced_TX_power = true,
|
|
|
|
|
.calib_need =
|
|
|
|
|
(IWN_FLG_NEED_PHY_CALIB_LO
|
|
|
|
|
| IWN_FLG_NEED_PHY_CALIB_TX_IQ
|
2013-12-28 05:50:53 +00:00
|
|
|
| IWN_FLG_NEED_PHY_CALIB_BASE_BAND ),
|
2013-11-12 05:58:23 +00:00
|
|
|
.support_hostap = false,
|
|
|
|
|
.no_multi_vaps = true,
|
|
|
|
|
.additional_gp_drv_bit = IWN_GP_DRIVER_NONE,
|
|
|
|
|
.bt_mode = IWN_BT_SIMPLE,
|
2013-12-07 06:45:09 +00:00
|
|
|
.plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD,
|
2013-11-12 05:58:23 +00:00
|
|
|
};
|
|
|
|
|
static const struct iwn_base_params iwn_6150_base_params = {
|
|
|
|
|
.pll_cfg_val = 0,
|
|
|
|
|
.max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x50,
|
|
|
|
|
.shadow_ram_support = true,
|
|
|
|
|
.shadow_reg_enable = true,
|
|
|
|
|
.bt_session_2 = false,
|
|
|
|
|
.bt_sco_disable = true,
|
|
|
|
|
.additional_nic_config = true,
|
|
|
|
|
.regulatory_bands = iwn6000_regulatory_bands,
|
|
|
|
|
.enhanced_TX_power = true,
|
|
|
|
|
.calib_need =
|
|
|
|
|
(IWN_FLG_NEED_PHY_CALIB_LO
|
|
|
|
|
| IWN_FLG_NEED_PHY_CALIB_TX_IQ
|
|
|
|
|
| IWN_FLG_NEED_PHY_CALIB_BASE_BAND),
|
|
|
|
|
.support_hostap = false,
|
|
|
|
|
.no_multi_vaps = true,
|
|
|
|
|
.additional_gp_drv_bit = IWN_GP_DRIVER_6050_1X2,
|
|
|
|
|
.bt_mode = IWN_BT_SIMPLE,
|
2013-12-07 06:45:09 +00:00
|
|
|
.plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD,
|
2013-11-12 05:58:23 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* IWL_DEVICE_6035 & IWL_DEVICE_6030 */
|
|
|
|
|
static const struct iwn_base_params iwn_6000g2b_base_params = {
|
|
|
|
|
.pll_cfg_val = 0,
|
|
|
|
|
.max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00,
|
|
|
|
|
.shadow_ram_support = true,
|
|
|
|
|
.shadow_reg_enable = true,
|
|
|
|
|
.bt_session_2 = false,
|
|
|
|
|
.bt_sco_disable = true,
|
|
|
|
|
.additional_nic_config = false,
|
|
|
|
|
.regulatory_bands = iwn6000_regulatory_bands,
|
|
|
|
|
.enhanced_TX_power = true,
|
|
|
|
|
.calib_need =
|
|
|
|
|
(IWN_FLG_NEED_PHY_CALIB_DC
|
|
|
|
|
| IWN_FLG_NEED_PHY_CALIB_LO
|
|
|
|
|
| IWN_FLG_NEED_PHY_CALIB_TX_IQ
|
|
|
|
|
| IWN_FLG_NEED_PHY_CALIB_BASE_BAND
|
|
|
|
|
| IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET ),
|
|
|
|
|
.support_hostap = false,
|
|
|
|
|
.no_multi_vaps = true,
|
|
|
|
|
.additional_gp_drv_bit = IWN_GP_DRIVER_NONE,
|
|
|
|
|
.bt_mode = IWN_BT_ADVANCED,
|
2013-12-07 06:45:09 +00:00
|
|
|
.plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD,
|
2013-11-12 05:58:23 +00:00
|
|
|
};
|
2013-12-09 03:40:02 +00:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* 6235 series NICs.
|
|
|
|
|
*/
|
|
|
|
|
static const struct iwn_base_params iwn_6235_base_params = {
|
|
|
|
|
.pll_cfg_val = 0,
|
|
|
|
|
.max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00,
|
|
|
|
|
.shadow_ram_support = true,
|
|
|
|
|
.shadow_reg_enable = true,
|
|
|
|
|
.bt_session_2 = false,
|
|
|
|
|
.bt_sco_disable = true,
|
|
|
|
|
.additional_nic_config = true,
|
|
|
|
|
.regulatory_bands = iwn6000_regulatory_bands,
|
|
|
|
|
.enhanced_TX_power = true,
|
|
|
|
|
.calib_need =
|
|
|
|
|
(IWN_FLG_NEED_PHY_CALIB_DC
|
|
|
|
|
| IWN_FLG_NEED_PHY_CALIB_LO
|
|
|
|
|
| IWN_FLG_NEED_PHY_CALIB_TX_IQ
|
|
|
|
|
| IWN_FLG_NEED_PHY_CALIB_BASE_BAND
|
|
|
|
|
| IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET ),
|
|
|
|
|
.support_hostap = false,
|
|
|
|
|
.no_multi_vaps = true,
|
2018-06-28 21:59:45 +00:00
|
|
|
.additional_gp_drv_bit = 0,
|
2013-12-09 03:40:02 +00:00
|
|
|
.bt_mode = IWN_BT_ADVANCED,
|
|
|
|
|
.plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD,
|
|
|
|
|
};
|
|
|
|
|
|
2013-11-12 05:58:23 +00:00
|
|
|
static const struct iwn_base_params iwn_5x50_base_params = {
|
|
|
|
|
.pll_cfg_val = IWN_ANA_PLL_INIT,
|
|
|
|
|
.max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00,
|
|
|
|
|
.shadow_ram_support = true,
|
|
|
|
|
.shadow_reg_enable = false,
|
|
|
|
|
.bt_session_2 = false,
|
|
|
|
|
.bt_sco_disable = true,
|
|
|
|
|
.additional_nic_config = false,
|
|
|
|
|
.regulatory_bands = iwn5000_regulatory_bands,
|
|
|
|
|
.enhanced_TX_power =false,
|
|
|
|
|
.calib_need =
|
|
|
|
|
(IWN_FLG_NEED_PHY_CALIB_DC
|
|
|
|
|
| IWN_FLG_NEED_PHY_CALIB_LO
|
|
|
|
|
| IWN_FLG_NEED_PHY_CALIB_TX_IQ
|
|
|
|
|
| IWN_FLG_NEED_PHY_CALIB_BASE_BAND ),
|
|
|
|
|
.support_hostap = false,
|
|
|
|
|
.no_multi_vaps = true,
|
|
|
|
|
.additional_gp_drv_bit = IWN_GP_DRIVER_NONE,
|
|
|
|
|
.bt_mode = IWN_BT_SIMPLE,
|
2013-12-07 06:45:09 +00:00
|
|
|
.plcp_err_threshold = IWN_PLCP_ERR_LONG_THRESHOLD,
|
2013-11-12 05:58:23 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
#endif /* __IF_IWN_CHIP_CFG_H__ */
|
