2011-03-21 09:58:24 +00:00
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/*
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2014-09-23 12:37:01 +00:00
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* Copyright (c) 2007, 2014 Mellanox Technologies. All rights reserved.
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2011-03-21 09:58:24 +00:00
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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*/
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2014-10-15 13:40:29 +00:00
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#include <linux/page.h>
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2011-03-21 09:58:24 +00:00
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#include <linux/mlx4/cq.h>
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2014-09-23 12:37:01 +00:00
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#include <linux/slab.h>
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2011-03-21 09:58:24 +00:00
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#include <linux/mlx4/qp.h>
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2014-09-23 12:37:01 +00:00
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#include <linux/if_vlan.h>
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2011-03-21 09:58:24 +00:00
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#include <linux/vmalloc.h>
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2014-09-23 12:37:01 +00:00
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#include <linux/moduleparam.h>
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2011-03-21 09:58:24 +00:00
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#include <netinet/in_systm.h>
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#include <netinet/in.h>
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#include <netinet/if_ether.h>
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#include <netinet/ip.h>
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#include <netinet/ip6.h>
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#include <netinet/tcp.h>
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#include <netinet/tcp_lro.h>
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#include <netinet/udp.h>
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2014-09-23 12:37:01 +00:00
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#include "mlx4_en.h"
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#include "utils.h"
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2011-03-21 09:58:24 +00:00
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enum {
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MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */
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MAX_BF = 256,
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2014-09-23 12:37:01 +00:00
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MIN_PKT_LEN = 17,
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2011-03-21 09:58:24 +00:00
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};
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2014-09-23 12:37:01 +00:00
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static int inline_thold __read_mostly = MAX_INLINE;
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2011-03-21 09:58:24 +00:00
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2014-09-23 12:37:01 +00:00
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module_param_named(inline_thold, inline_thold, uint, 0444);
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MODULE_PARM_DESC(inline_thold, "threshold for using inline data");
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2011-03-21 09:58:24 +00:00
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int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
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2014-09-23 12:37:01 +00:00
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struct mlx4_en_tx_ring **pring, u32 size,
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u16 stride, int node, int queue_idx)
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2011-03-21 09:58:24 +00:00
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{
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struct mlx4_en_dev *mdev = priv->mdev;
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2014-09-23 12:37:01 +00:00
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struct mlx4_en_tx_ring *ring;
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2011-03-21 09:58:24 +00:00
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int tmp;
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int err;
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2014-09-23 12:37:01 +00:00
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ring = kzalloc_node(sizeof(struct mlx4_en_tx_ring), GFP_KERNEL, node);
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if (!ring) {
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ring = kzalloc(sizeof(struct mlx4_en_tx_ring), GFP_KERNEL);
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if (!ring) {
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en_err(priv, "Failed allocating TX ring\n");
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return -ENOMEM;
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}
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}
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2011-03-21 09:58:24 +00:00
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ring->size = size;
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ring->size_mask = size - 1;
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ring->stride = stride;
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2014-09-23 12:37:01 +00:00
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ring->full_size = ring->size - HEADROOM - MAX_DESC_TXBBS;
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ring->inline_thold = min(inline_thold, MAX_INLINE);
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2011-03-21 09:58:24 +00:00
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mtx_init(&ring->tx_lock.m, "mlx4 tx", NULL, MTX_DEF);
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mtx_init(&ring->comp_lock.m, "mlx4 comp", NULL, MTX_DEF);
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/* Allocate the buf ring */
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ring->br = buf_ring_alloc(MLX4_EN_DEF_TX_QUEUE_SIZE, M_DEVBUF,
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2014-09-23 12:37:01 +00:00
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M_WAITOK, &ring->tx_lock.m);
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2011-03-21 09:58:24 +00:00
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if (ring->br == NULL) {
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en_err(priv, "Failed allocating tx_info ring\n");
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return -ENOMEM;
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}
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tmp = size * sizeof(struct mlx4_en_tx_info);
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2014-09-23 12:37:01 +00:00
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ring->tx_info = vmalloc_node(tmp, node);
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2011-03-21 09:58:24 +00:00
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if (!ring->tx_info) {
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2014-09-23 12:37:01 +00:00
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ring->tx_info = vmalloc(tmp);
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if (!ring->tx_info) {
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err = -ENOMEM;
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goto err_ring;
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}
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2011-03-21 09:58:24 +00:00
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}
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2014-09-23 12:37:01 +00:00
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2011-03-21 09:58:24 +00:00
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en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n",
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ring->tx_info, tmp);
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2014-09-23 12:37:01 +00:00
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ring->bounce_buf = kmalloc_node(MAX_DESC_SIZE, GFP_KERNEL, node);
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2011-03-21 09:58:24 +00:00
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if (!ring->bounce_buf) {
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2014-09-23 12:37:01 +00:00
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ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL);
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if (!ring->bounce_buf) {
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err = -ENOMEM;
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goto err_info;
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}
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2011-03-21 09:58:24 +00:00
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}
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ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE);
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2014-09-23 12:37:01 +00:00
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/* Allocate HW buffers on provided NUMA node */
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2011-03-21 09:58:24 +00:00
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err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size,
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2 * PAGE_SIZE);
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if (err) {
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en_err(priv, "Failed allocating hwq resources\n");
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goto err_bounce;
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}
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err = mlx4_en_map_buffer(&ring->wqres.buf);
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if (err) {
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en_err(priv, "Failed to map TX buffer\n");
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goto err_hwq_res;
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}
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ring->buf = ring->wqres.buf.direct.buf;
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en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d "
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"buf_size:%d dma:%llx\n", ring, ring->buf, ring->size,
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ring->buf_size, (unsigned long long) ring->wqres.buf.direct.map);
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2014-09-23 12:37:01 +00:00
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err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &ring->qpn,
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MLX4_RESERVE_BF_QP);
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2011-03-21 09:58:24 +00:00
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if (err) {
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2014-09-23 12:37:01 +00:00
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en_err(priv, "failed reserving qp for TX ring\n");
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2011-03-21 09:58:24 +00:00
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goto err_map;
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}
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err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp);
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if (err) {
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en_err(priv, "Failed allocating qp %d\n", ring->qpn);
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goto err_reserve;
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}
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ring->qp.event = mlx4_en_sqp_event;
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2014-09-23 12:37:01 +00:00
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err = mlx4_bf_alloc(mdev->dev, &ring->bf, node);
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2011-03-21 09:58:24 +00:00
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if (err) {
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2014-09-23 12:37:01 +00:00
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en_dbg(DRV, priv, "working without blueflame (%d)", err);
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2011-03-21 09:58:24 +00:00
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ring->bf.uar = &mdev->priv_uar;
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ring->bf.uar->map = mdev->uar_map;
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ring->bf_enabled = false;
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} else
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ring->bf_enabled = true;
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2014-09-23 12:37:01 +00:00
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ring->queue_index = queue_idx;
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if (queue_idx < priv->num_tx_rings_p_up )
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CPU_SET(queue_idx, &ring->affinity_mask);
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2011-03-21 09:58:24 +00:00
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2014-09-23 12:37:01 +00:00
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*pring = ring;
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2011-03-21 09:58:24 +00:00
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return 0;
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err_reserve:
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mlx4_qp_release_range(mdev->dev, ring->qpn, 1);
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err_map:
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mlx4_en_unmap_buffer(&ring->wqres.buf);
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err_hwq_res:
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mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
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err_bounce:
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kfree(ring->bounce_buf);
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2014-09-23 12:37:01 +00:00
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err_info:
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vfree(ring->tx_info);
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err_ring:
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2011-03-21 09:58:24 +00:00
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buf_ring_free(ring->br, M_DEVBUF);
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2014-09-23 12:37:01 +00:00
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kfree(ring);
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2011-03-21 09:58:24 +00:00
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return err;
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}
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void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
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2014-09-23 12:37:01 +00:00
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struct mlx4_en_tx_ring **pring)
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2011-03-21 09:58:24 +00:00
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{
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struct mlx4_en_dev *mdev = priv->mdev;
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2014-09-23 12:37:01 +00:00
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struct mlx4_en_tx_ring *ring = *pring;
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2011-03-21 09:58:24 +00:00
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en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn);
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buf_ring_free(ring->br, M_DEVBUF);
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if (ring->bf_enabled)
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mlx4_bf_free(mdev->dev, &ring->bf);
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mlx4_qp_remove(mdev->dev, &ring->qp);
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mlx4_qp_free(mdev->dev, &ring->qp);
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2014-09-23 12:37:01 +00:00
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mlx4_qp_release_range(priv->mdev->dev, ring->qpn, 1);
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2011-03-21 09:58:24 +00:00
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mlx4_en_unmap_buffer(&ring->wqres.buf);
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mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
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kfree(ring->bounce_buf);
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2014-09-23 12:37:01 +00:00
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vfree(ring->tx_info);
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2011-03-21 09:58:24 +00:00
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mtx_destroy(&ring->tx_lock.m);
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mtx_destroy(&ring->comp_lock.m);
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2014-09-23 12:37:01 +00:00
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kfree(ring);
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*pring = NULL;
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2011-03-21 09:58:24 +00:00
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}
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int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
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struct mlx4_en_tx_ring *ring,
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2014-09-23 12:37:01 +00:00
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int cq, int user_prio)
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2011-03-21 09:58:24 +00:00
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{
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struct mlx4_en_dev *mdev = priv->mdev;
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int err;
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ring->cqn = cq;
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ring->prod = 0;
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ring->cons = 0xffffffff;
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ring->last_nr_txbb = 1;
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ring->poll_cnt = 0;
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ring->blocked = 0;
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memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info));
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memset(ring->buf, 0, ring->buf_size);
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ring->qp_state = MLX4_QP_STATE_RST;
|
2014-09-23 12:37:01 +00:00
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ring->doorbell_qpn = ring->qp.qpn << 8;
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2011-03-21 09:58:24 +00:00
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mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 1, 0, ring->qpn,
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2014-09-23 12:37:01 +00:00
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ring->cqn, user_prio, &ring->context);
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2011-03-21 09:58:24 +00:00
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if (ring->bf_enabled)
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ring->context.usr_page = cpu_to_be32(ring->bf.uar->index);
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err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, &ring->context,
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&ring->qp, &ring->qp_state);
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return err;
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}
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void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
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struct mlx4_en_tx_ring *ring)
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{
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struct mlx4_en_dev *mdev = priv->mdev;
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mlx4_qp_modify(mdev->dev, NULL, ring->qp_state,
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MLX4_QP_STATE_RST, NULL, 0, 0, &ring->qp);
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}
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2014-09-23 12:37:01 +00:00
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static void mlx4_en_stamp_wqe(struct mlx4_en_priv *priv,
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struct mlx4_en_tx_ring *ring,
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int index, u8 owner)
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{
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struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
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struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE;
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void *end = ring->buf + ring->buf_size;
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__be32 *ptr = (__be32 *)tx_desc;
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__be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT));
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int i;
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/* Optimize the common case when there are no wraparounds */
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if (likely((void *)tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end))
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/* Stamp the freed descriptor */
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for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; i += STAMP_STRIDE) {
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*ptr = stamp;
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ptr += STAMP_DWORDS;
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}
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else
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/* Stamp the freed descriptor */
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for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; i += STAMP_STRIDE) {
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*ptr = stamp;
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ptr += STAMP_DWORDS;
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if ((void *)ptr >= end) {
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ptr = ring->buf;
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stamp ^= cpu_to_be32(0x80000000);
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}
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}
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}
|
2011-03-21 09:58:24 +00:00
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static u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
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struct mlx4_en_tx_ring *ring,
|
2014-09-23 12:37:01 +00:00
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int index, u8 owner, u64 timestamp)
|
2011-03-21 09:58:24 +00:00
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{
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struct mlx4_en_dev *mdev = priv->mdev;
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struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
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struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE;
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struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset;
|
2014-09-23 12:37:01 +00:00
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struct mbuf *mb = tx_info->mb;
|
2011-03-21 09:58:24 +00:00
|
|
|
void *end = ring->buf + ring->buf_size;
|
2014-09-23 12:37:01 +00:00
|
|
|
int frags = tx_info->nr_segs;;
|
2011-03-21 09:58:24 +00:00
|
|
|
int i;
|
|
|
|
|
|
|
|
/* Optimize the common case when there are no wraparounds */
|
|
|
|
if (likely((void *) tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) {
|
|
|
|
if (!tx_info->inl) {
|
2014-09-23 12:37:01 +00:00
|
|
|
if (tx_info->linear) {
|
|
|
|
dma_unmap_single(priv->ddev,
|
|
|
|
(dma_addr_t) be64_to_cpu(data->addr),
|
|
|
|
be32_to_cpu(data->byte_count),
|
|
|
|
PCI_DMA_TODEVICE);
|
|
|
|
++data;
|
|
|
|
}
|
|
|
|
|
2011-03-21 09:58:24 +00:00
|
|
|
for (i = 0; i < frags; i++) {
|
2014-09-23 12:37:01 +00:00
|
|
|
pci_unmap_single(mdev->pdev,
|
|
|
|
(dma_addr_t) be64_to_cpu(data[i].addr),
|
|
|
|
data[i].byte_count, PCI_DMA_TODEVICE);
|
2011-03-21 09:58:24 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
if (!tx_info->inl) {
|
2014-09-23 12:37:01 +00:00
|
|
|
if ((void *) data >= end) {
|
|
|
|
data = ring->buf + ((void *)data - end);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (tx_info->linear) {
|
|
|
|
dma_unmap_single(priv->ddev,
|
|
|
|
(dma_addr_t) be64_to_cpu(data->addr),
|
|
|
|
be32_to_cpu(data->byte_count),
|
|
|
|
PCI_DMA_TODEVICE);
|
|
|
|
++data;
|
|
|
|
}
|
|
|
|
|
2011-03-21 09:58:24 +00:00
|
|
|
for (i = 0; i < frags; i++) {
|
|
|
|
/* Check for wraparound before unmapping */
|
|
|
|
if ((void *) data >= end)
|
2014-09-23 12:37:01 +00:00
|
|
|
data = ring->buf;
|
|
|
|
pci_unmap_single(mdev->pdev,
|
|
|
|
(dma_addr_t) be64_to_cpu(data->addr),
|
|
|
|
data->byte_count, PCI_DMA_TODEVICE);
|
2011-03-21 09:58:24 +00:00
|
|
|
++data;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2014-09-23 12:37:01 +00:00
|
|
|
/* Send a copy of the frame to the BPF listener */
|
|
|
|
if (priv->dev && priv->dev->if_bpf)
|
|
|
|
ETHER_BPF_MTAP(priv->dev, mb);
|
|
|
|
m_freem(mb);
|
2011-03-21 09:58:24 +00:00
|
|
|
return tx_info->nr_txbb;
|
|
|
|
}
|
|
|
|
|
|
|
|
int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring)
|
|
|
|
{
|
|
|
|
struct mlx4_en_priv *priv = netdev_priv(dev);
|
|
|
|
int cnt = 0;
|
|
|
|
|
|
|
|
/* Skip last polled descriptor */
|
|
|
|
ring->cons += ring->last_nr_txbb;
|
|
|
|
en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n",
|
|
|
|
ring->cons, ring->prod);
|
|
|
|
|
|
|
|
if ((u32) (ring->prod - ring->cons) > ring->size) {
|
2014-09-23 12:37:01 +00:00
|
|
|
en_warn(priv, "Tx consumer passed producer!\n");
|
2011-03-21 09:58:24 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
while (ring->cons != ring->prod) {
|
|
|
|
ring->last_nr_txbb = mlx4_en_free_tx_desc(priv, ring,
|
|
|
|
ring->cons & ring->size_mask,
|
2014-09-23 12:37:01 +00:00
|
|
|
!!(ring->cons & ring->size), 0);
|
2011-03-21 09:58:24 +00:00
|
|
|
ring->cons += ring->last_nr_txbb;
|
|
|
|
cnt++;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cnt)
|
|
|
|
en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt);
|
|
|
|
|
|
|
|
return cnt;
|
|
|
|
}
|
|
|
|
|
2014-09-23 12:37:01 +00:00
|
|
|
static int mlx4_en_process_tx_cq(struct net_device *dev,
|
|
|
|
struct mlx4_en_cq *cq)
|
2011-03-21 09:58:24 +00:00
|
|
|
{
|
|
|
|
struct mlx4_en_priv *priv = netdev_priv(dev);
|
|
|
|
struct mlx4_cq *mcq = &cq->mcq;
|
2014-09-23 12:37:01 +00:00
|
|
|
struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring];
|
|
|
|
struct mlx4_cqe *cqe;
|
2011-03-21 09:58:24 +00:00
|
|
|
u16 index;
|
2014-09-23 12:37:01 +00:00
|
|
|
u16 new_index, ring_index, stamp_index;
|
2011-03-21 09:58:24 +00:00
|
|
|
u32 txbbs_skipped = 0;
|
2014-09-23 12:37:01 +00:00
|
|
|
u32 txbbs_stamp = 0;
|
|
|
|
u32 cons_index = mcq->cons_index;
|
|
|
|
int size = cq->size;
|
|
|
|
u32 size_mask = ring->size_mask;
|
|
|
|
struct mlx4_cqe *buf = cq->buf;
|
|
|
|
u32 packets = 0;
|
|
|
|
u32 bytes = 0;
|
|
|
|
int factor = priv->cqe_factor;
|
|
|
|
u64 timestamp = 0;
|
|
|
|
int done = 0;
|
2011-03-21 09:58:24 +00:00
|
|
|
|
|
|
|
|
|
|
|
if (!priv->port_up)
|
2014-09-23 12:37:01 +00:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
index = cons_index & size_mask;
|
|
|
|
cqe = &buf[(index << factor) + factor];
|
|
|
|
ring_index = ring->cons & size_mask;
|
|
|
|
stamp_index = ring_index;
|
|
|
|
|
|
|
|
/* Process all completed CQEs */
|
|
|
|
while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
|
|
|
|
cons_index & size)) {
|
|
|
|
/*
|
|
|
|
* make sure we read the CQE after we read the
|
|
|
|
* ownership bit
|
|
|
|
*/
|
|
|
|
rmb();
|
|
|
|
|
|
|
|
if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
|
|
|
|
MLX4_CQE_OPCODE_ERROR)) {
|
|
|
|
en_err(priv, "CQE completed in error - vendor syndrom: 0x%x syndrom: 0x%x\n",
|
|
|
|
((struct mlx4_err_cqe *)cqe)->
|
|
|
|
vendor_err_syndrome,
|
|
|
|
((struct mlx4_err_cqe *)cqe)->syndrome);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Skip over last polled CQE */
|
|
|
|
new_index = be16_to_cpu(cqe->wqe_index) & size_mask;
|
2011-03-21 09:58:24 +00:00
|
|
|
|
|
|
|
do {
|
|
|
|
txbbs_skipped += ring->last_nr_txbb;
|
2014-09-23 12:37:01 +00:00
|
|
|
ring_index = (ring_index + ring->last_nr_txbb) & size_mask;
|
|
|
|
/* free next descriptor */
|
2011-03-21 09:58:24 +00:00
|
|
|
ring->last_nr_txbb = mlx4_en_free_tx_desc(
|
2014-09-23 12:37:01 +00:00
|
|
|
priv, ring, ring_index,
|
|
|
|
!!((ring->cons + txbbs_skipped) &
|
|
|
|
ring->size), timestamp);
|
|
|
|
mlx4_en_stamp_wqe(priv, ring, stamp_index,
|
|
|
|
!!((ring->cons + txbbs_stamp) &
|
|
|
|
ring->size));
|
|
|
|
stamp_index = ring_index;
|
|
|
|
txbbs_stamp = txbbs_skipped;
|
|
|
|
packets++;
|
|
|
|
bytes += ring->tx_info[ring_index].nr_bytes;
|
|
|
|
} while (ring_index != new_index);
|
|
|
|
|
|
|
|
++cons_index;
|
|
|
|
index = cons_index & size_mask;
|
|
|
|
cqe = &buf[(index << factor) + factor];
|
|
|
|
}
|
2011-03-21 09:58:24 +00:00
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* To prevent CQ overflow we first update CQ consumer and only then
|
|
|
|
* the ring consumer.
|
|
|
|
*/
|
2014-09-23 12:37:01 +00:00
|
|
|
mcq->cons_index = cons_index;
|
2011-03-21 09:58:24 +00:00
|
|
|
mlx4_cq_set_ci(mcq);
|
|
|
|
wmb();
|
|
|
|
ring->cons += txbbs_skipped;
|
|
|
|
|
2014-09-23 12:37:01 +00:00
|
|
|
/* Wakeup Tx queue if it was stopped and ring is not full */
|
|
|
|
if (unlikely(ring->blocked) &&
|
|
|
|
(ring->prod - ring->cons) <= ring->full_size) {
|
|
|
|
ring->blocked = 0;
|
|
|
|
if (atomic_fetchadd_int(&priv->blocked, -1) == 1)
|
|
|
|
atomic_clear_int(&dev->if_drv_flags ,IFF_DRV_OACTIVE);
|
|
|
|
ring->wake_queue++;
|
|
|
|
priv->port_stats.wake_queue++;
|
2011-03-21 09:58:24 +00:00
|
|
|
}
|
2014-09-23 12:37:01 +00:00
|
|
|
return done;
|
2011-03-21 09:58:24 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void mlx4_en_tx_irq(struct mlx4_cq *mcq)
|
|
|
|
{
|
|
|
|
struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
|
|
|
|
struct mlx4_en_priv *priv = netdev_priv(cq->dev);
|
2014-09-23 12:37:01 +00:00
|
|
|
struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring];
|
2011-03-21 09:58:24 +00:00
|
|
|
|
|
|
|
if (!spin_trylock(&ring->comp_lock))
|
|
|
|
return;
|
|
|
|
mlx4_en_process_tx_cq(cq->dev, cq);
|
|
|
|
mod_timer(&cq->timer, jiffies + 1);
|
|
|
|
spin_unlock(&ring->comp_lock);
|
|
|
|
}
|
|
|
|
|
|
|
|
void mlx4_en_poll_tx_cq(unsigned long data)
|
|
|
|
{
|
|
|
|
struct mlx4_en_cq *cq = (struct mlx4_en_cq *) data;
|
|
|
|
struct mlx4_en_priv *priv = netdev_priv(cq->dev);
|
2014-09-23 12:37:01 +00:00
|
|
|
struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring];
|
2011-03-21 09:58:24 +00:00
|
|
|
u32 inflight;
|
|
|
|
|
|
|
|
INC_PERF_COUNTER(priv->pstats.tx_poll);
|
|
|
|
|
|
|
|
if (!spin_trylock(&ring->comp_lock)) {
|
|
|
|
mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
mlx4_en_process_tx_cq(cq->dev, cq);
|
|
|
|
inflight = (u32) (ring->prod - ring->cons - ring->last_nr_txbb);
|
|
|
|
|
|
|
|
/* If there are still packets in flight and the timer has not already
|
|
|
|
* been scheduled by the Tx routine then schedule it here to guarantee
|
|
|
|
* completion processing of these packets */
|
|
|
|
if (inflight && priv->port_up)
|
|
|
|
mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT);
|
|
|
|
|
|
|
|
spin_unlock(&ring->comp_lock);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv,
|
|
|
|
struct mlx4_en_tx_ring *ring,
|
|
|
|
u32 index,
|
|
|
|
unsigned int desc_size)
|
|
|
|
{
|
|
|
|
u32 copy = (ring->size - index) * TXBB_SIZE;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = desc_size - copy - 4; i >= 0; i -= 4) {
|
|
|
|
if ((i & (TXBB_SIZE - 1)) == 0)
|
|
|
|
wmb();
|
|
|
|
|
|
|
|
*((u32 *) (ring->buf + i)) =
|
|
|
|
*((u32 *) (ring->bounce_buf + copy + i));
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = copy - 4; i >= 4 ; i -= 4) {
|
|
|
|
if ((i & (TXBB_SIZE - 1)) == 0)
|
|
|
|
wmb();
|
|
|
|
|
|
|
|
*((u32 *) (ring->buf + index * TXBB_SIZE + i)) =
|
|
|
|
*((u32 *) (ring->bounce_buf + i));
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Return real descriptor location */
|
|
|
|
return ring->buf + index * TXBB_SIZE;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void mlx4_en_xmit_poll(struct mlx4_en_priv *priv, int tx_ind)
|
|
|
|
{
|
2014-09-23 12:37:01 +00:00
|
|
|
struct mlx4_en_cq *cq = priv->tx_cq[tx_ind];
|
|
|
|
struct mlx4_en_tx_ring *ring = priv->tx_ring[tx_ind];
|
2011-03-21 09:58:24 +00:00
|
|
|
|
|
|
|
/* If we don't have a pending timer, set one up to catch our recent
|
|
|
|
post in case the interface becomes idle */
|
|
|
|
if (!timer_pending(&cq->timer))
|
|
|
|
mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT);
|
|
|
|
|
|
|
|
/* Poll the CQ every mlx4_en_TX_MODER_POLL packets */
|
|
|
|
if ((++ring->poll_cnt & (MLX4_EN_TX_POLL_MODER - 1)) == 0)
|
|
|
|
if (spin_trylock(&ring->comp_lock)) {
|
|
|
|
mlx4_en_process_tx_cq(priv->dev, cq);
|
|
|
|
spin_unlock(&ring->comp_lock);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-09-23 12:37:01 +00:00
|
|
|
static int is_inline(struct mbuf *mb, int thold)
|
2011-03-21 09:58:24 +00:00
|
|
|
{
|
2014-09-23 12:37:01 +00:00
|
|
|
if (thold && mb->m_pkthdr.len <= thold &&
|
|
|
|
(mb->m_pkthdr.csum_flags & CSUM_TSO) == 0)
|
2011-03-21 09:58:24 +00:00
|
|
|
return 1;
|
|
|
|
|
2014-09-23 12:37:01 +00:00
|
|
|
return 0;
|
2011-03-21 09:58:24 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int inline_size(struct mbuf *mb)
|
|
|
|
{
|
|
|
|
int len;
|
|
|
|
|
|
|
|
len = mb->m_pkthdr.len;
|
|
|
|
if (len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg)
|
|
|
|
<= MLX4_INLINE_ALIGN)
|
|
|
|
return ALIGN(len + CTRL_SIZE +
|
|
|
|
sizeof(struct mlx4_wqe_inline_seg), 16);
|
|
|
|
else
|
|
|
|
return ALIGN(len + CTRL_SIZE + 2 *
|
|
|
|
sizeof(struct mlx4_wqe_inline_seg), 16);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int get_head_size(struct mbuf *mb)
|
|
|
|
{
|
2014-09-23 12:37:01 +00:00
|
|
|
struct ether_vlan_header *eh;
|
|
|
|
struct tcphdr *th;
|
|
|
|
struct ip *ip;
|
|
|
|
int ip_hlen, tcp_hlen;
|
|
|
|
struct ip6_hdr *ip6;
|
|
|
|
uint16_t eth_type;
|
|
|
|
int eth_hdr_len;
|
|
|
|
|
|
|
|
eh = mtod(mb, struct ether_vlan_header *);
|
|
|
|
if (mb->m_len < ETHER_HDR_LEN)
|
|
|
|
return (0);
|
|
|
|
if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
|
|
|
|
eth_type = ntohs(eh->evl_proto);
|
|
|
|
eth_hdr_len = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
|
|
|
|
} else {
|
|
|
|
eth_type = ntohs(eh->evl_encap_proto);
|
|
|
|
eth_hdr_len = ETHER_HDR_LEN;
|
|
|
|
}
|
|
|
|
if (mb->m_len < eth_hdr_len)
|
2011-03-21 09:58:24 +00:00
|
|
|
return (0);
|
2014-09-23 12:37:01 +00:00
|
|
|
switch (eth_type) {
|
|
|
|
case ETHERTYPE_IP:
|
|
|
|
ip = (struct ip *)(mb->m_data + eth_hdr_len);
|
|
|
|
if (mb->m_len < eth_hdr_len + sizeof(*ip))
|
|
|
|
return (0);
|
|
|
|
if (ip->ip_p != IPPROTO_TCP)
|
|
|
|
return (0);
|
|
|
|
ip_hlen = ip->ip_hl << 2;
|
|
|
|
eth_hdr_len += ip_hlen;
|
|
|
|
break;
|
|
|
|
case ETHERTYPE_IPV6:
|
|
|
|
ip6 = (struct ip6_hdr *)(mb->m_data + eth_hdr_len);
|
|
|
|
if (mb->m_len < eth_hdr_len + sizeof(*ip6))
|
|
|
|
return (0);
|
|
|
|
if (ip6->ip6_nxt != IPPROTO_TCP)
|
|
|
|
return (0);
|
|
|
|
eth_hdr_len += sizeof(*ip6);
|
|
|
|
break;
|
|
|
|
default:
|
2011-03-21 09:58:24 +00:00
|
|
|
return (0);
|
2014-09-23 12:37:01 +00:00
|
|
|
}
|
|
|
|
if (mb->m_len < eth_hdr_len + sizeof(*th))
|
2011-03-21 09:58:24 +00:00
|
|
|
return (0);
|
2014-09-23 12:37:01 +00:00
|
|
|
th = (struct tcphdr *)(mb->m_data + eth_hdr_len);
|
2011-03-21 09:58:24 +00:00
|
|
|
tcp_hlen = th->th_off << 2;
|
2014-09-23 12:37:01 +00:00
|
|
|
eth_hdr_len += tcp_hlen;
|
|
|
|
if (mb->m_len < eth_hdr_len)
|
2011-03-21 09:58:24 +00:00
|
|
|
return (0);
|
2014-09-23 12:37:01 +00:00
|
|
|
return (eth_hdr_len);
|
2011-03-21 09:58:24 +00:00
|
|
|
}
|
|
|
|
|
2014-09-23 12:37:01 +00:00
|
|
|
static int get_real_size(struct mbuf *mb, struct net_device *dev, int *p_n_segs,
|
|
|
|
int *lso_header_size, int inl)
|
2011-03-21 09:58:24 +00:00
|
|
|
{
|
2014-09-23 12:37:01 +00:00
|
|
|
struct mbuf *m;
|
|
|
|
int nr_segs = 0;
|
|
|
|
|
|
|
|
for (m = mb; m != NULL; m = m->m_next)
|
|
|
|
if (m->m_len)
|
|
|
|
nr_segs++;
|
|
|
|
|
|
|
|
if (mb->m_pkthdr.csum_flags & CSUM_TSO) {
|
|
|
|
*lso_header_size = get_head_size(mb);
|
|
|
|
if (*lso_header_size) {
|
|
|
|
if (mb->m_len == *lso_header_size)
|
|
|
|
nr_segs--;
|
|
|
|
*p_n_segs = nr_segs;
|
|
|
|
return CTRL_SIZE + nr_segs * DS_SIZE +
|
|
|
|
ALIGN(*lso_header_size + 4, DS_SIZE);
|
|
|
|
}
|
|
|
|
} else
|
|
|
|
*lso_header_size = 0;
|
|
|
|
*p_n_segs = nr_segs;
|
|
|
|
if (inl)
|
|
|
|
return inline_size(mb);
|
|
|
|
return (CTRL_SIZE + nr_segs * DS_SIZE);
|
2011-03-21 09:58:24 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static struct mbuf *mb_copy(struct mbuf *mb, int *offp, char *data, int len)
|
|
|
|
{
|
2014-09-23 12:37:01 +00:00
|
|
|
int bytes;
|
|
|
|
int off;
|
|
|
|
|
|
|
|
off = *offp;
|
|
|
|
while (len) {
|
|
|
|
bytes = min(mb->m_len - off, len);
|
|
|
|
if (bytes)
|
|
|
|
memcpy(data, mb->m_data + off, bytes);
|
|
|
|
len -= bytes;
|
|
|
|
data += bytes;
|
|
|
|
off += bytes;
|
|
|
|
if (off == mb->m_len) {
|
|
|
|
off = 0;
|
|
|
|
mb = mb->m_next;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
*offp = off;
|
|
|
|
return (mb);
|
2011-03-21 09:58:24 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc, struct mbuf *mb,
|
2014-09-23 12:37:01 +00:00
|
|
|
int real_size, u16 *vlan_tag, int tx_ind)
|
2011-03-21 09:58:24 +00:00
|
|
|
{
|
|
|
|
struct mlx4_wqe_inline_seg *inl = &tx_desc->inl;
|
|
|
|
int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof *inl;
|
|
|
|
int len;
|
|
|
|
int off;
|
|
|
|
|
|
|
|
off = 0;
|
|
|
|
len = mb->m_pkthdr.len;
|
|
|
|
if (len <= spc) {
|
2014-09-23 12:37:01 +00:00
|
|
|
inl->byte_count = cpu_to_be32(1 << 31 |
|
|
|
|
(max_t(typeof(len), len, MIN_PKT_LEN)));
|
2011-03-21 09:58:24 +00:00
|
|
|
mb_copy(mb, &off, (void *)(inl + 1), len);
|
2014-09-23 12:37:01 +00:00
|
|
|
if (len < MIN_PKT_LEN)
|
|
|
|
memset(((void *)(inl + 1)) + len, 0,
|
|
|
|
MIN_PKT_LEN - len);
|
2011-03-21 09:58:24 +00:00
|
|
|
} else {
|
|
|
|
inl->byte_count = cpu_to_be32(1 << 31 | spc);
|
|
|
|
mb = mb_copy(mb, &off, (void *)(inl + 1), spc);
|
|
|
|
inl = (void *) (inl + 1) + spc;
|
|
|
|
mb_copy(mb, &off, (void *)(inl + 1), len - spc);
|
|
|
|
wmb();
|
|
|
|
inl->byte_count = cpu_to_be32(1 << 31 | (len - spc));
|
|
|
|
}
|
|
|
|
tx_desc->ctrl.vlan_tag = cpu_to_be16(*vlan_tag);
|
|
|
|
tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN * !!(*vlan_tag);
|
|
|
|
tx_desc->ctrl.fence_size = (real_size / 16) & 0x3f;
|
|
|
|
}
|
|
|
|
|
2014-09-23 12:37:01 +00:00
|
|
|
static unsigned long hashrandom;
|
|
|
|
static void hashrandom_init(void *arg)
|
|
|
|
{
|
|
|
|
hashrandom = random();
|
|
|
|
}
|
|
|
|
SYSINIT(hashrandom_init, SI_SUB_KLD, SI_ORDER_SECOND, &hashrandom_init, NULL);
|
|
|
|
|
2011-03-21 09:58:24 +00:00
|
|
|
u16 mlx4_en_select_queue(struct net_device *dev, struct mbuf *mb)
|
|
|
|
{
|
|
|
|
struct mlx4_en_priv *priv = netdev_priv(dev);
|
2014-09-23 12:37:01 +00:00
|
|
|
u32 rings_p_up = priv->num_tx_rings_p_up;
|
|
|
|
u32 vlan_tag = 0;
|
|
|
|
u32 up = 0;
|
|
|
|
u32 queue_index;
|
2011-03-21 09:58:24 +00:00
|
|
|
|
|
|
|
/* Obtain VLAN information if present */
|
|
|
|
if (mb->m_flags & M_VLANTAG) {
|
|
|
|
vlan_tag = mb->m_pkthdr.ether_vtag;
|
2014-09-23 12:37:01 +00:00
|
|
|
up = (vlan_tag >> 13);
|
2011-03-21 09:58:24 +00:00
|
|
|
}
|
|
|
|
|
2014-09-23 12:37:01 +00:00
|
|
|
/* hash mbuf */
|
|
|
|
queue_index = mlx4_en_hashmbuf(MLX4_F_HASHL3 | MLX4_F_HASHL4, mb, hashrandom);
|
2011-03-21 09:58:24 +00:00
|
|
|
|
2014-09-23 12:37:01 +00:00
|
|
|
return ((queue_index % rings_p_up) + (up * rings_p_up));
|
2011-03-21 09:58:24 +00:00
|
|
|
}
|
|
|
|
|
2014-09-23 12:37:01 +00:00
|
|
|
static void mlx4_bf_copy(void __iomem *dst, unsigned long *src, unsigned bytecnt)
|
2011-03-21 09:58:24 +00:00
|
|
|
{
|
|
|
|
__iowrite64_copy(dst, src, bytecnt / 8);
|
|
|
|
}
|
|
|
|
|
2014-09-23 12:37:01 +00:00
|
|
|
static u64 mlx4_en_mac_to_u64(u8 *addr)
|
|
|
|
{
|
|
|
|
u64 mac = 0;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < ETHER_ADDR_LEN; i++) {
|
|
|
|
mac <<= 8;
|
|
|
|
mac |= addr[i];
|
|
|
|
}
|
|
|
|
return mac;
|
|
|
|
}
|
|
|
|
|
2011-03-21 09:58:24 +00:00
|
|
|
static int mlx4_en_xmit(struct net_device *dev, int tx_ind, struct mbuf **mbp)
|
|
|
|
{
|
|
|
|
struct mlx4_en_priv *priv = netdev_priv(dev);
|
|
|
|
struct mlx4_en_dev *mdev = priv->mdev;
|
|
|
|
struct mlx4_en_tx_ring *ring;
|
|
|
|
struct mlx4_en_cq *cq;
|
|
|
|
struct mlx4_en_tx_desc *tx_desc;
|
|
|
|
struct mlx4_wqe_data_seg *data;
|
|
|
|
struct mlx4_en_tx_info *tx_info;
|
|
|
|
struct mbuf *m;
|
|
|
|
int nr_txbb;
|
|
|
|
int nr_segs;
|
|
|
|
int desc_size;
|
|
|
|
int real_size;
|
|
|
|
dma_addr_t dma;
|
2014-09-23 12:37:01 +00:00
|
|
|
u32 index, bf_index, ring_size;
|
2011-03-21 09:58:24 +00:00
|
|
|
__be32 op_own;
|
|
|
|
u16 vlan_tag = 0;
|
|
|
|
int i;
|
|
|
|
int lso_header_size;
|
|
|
|
bool bounce = false;
|
2014-09-23 12:37:01 +00:00
|
|
|
bool inl = false;
|
2011-03-21 09:58:24 +00:00
|
|
|
struct mbuf *mb;
|
2014-09-23 12:37:01 +00:00
|
|
|
mb = *mbp;
|
2011-03-21 09:58:24 +00:00
|
|
|
int defrag = 1;
|
|
|
|
|
|
|
|
if (!priv->port_up)
|
|
|
|
goto tx_drop;
|
|
|
|
|
2014-09-23 12:37:01 +00:00
|
|
|
ring = priv->tx_ring[tx_ind];
|
|
|
|
ring_size = ring->size;
|
|
|
|
inl = is_inline(mb, ring->inline_thold);
|
|
|
|
|
2011-03-21 09:58:24 +00:00
|
|
|
retry:
|
2014-09-23 12:37:01 +00:00
|
|
|
real_size = get_real_size(mb, dev, &nr_segs, &lso_header_size, inl);
|
2011-03-21 09:58:24 +00:00
|
|
|
if (unlikely(!real_size))
|
|
|
|
goto tx_drop;
|
|
|
|
|
2014-09-23 12:37:01 +00:00
|
|
|
/* Align descriptor to TXBB size */
|
2011-03-21 09:58:24 +00:00
|
|
|
desc_size = ALIGN(real_size, TXBB_SIZE);
|
|
|
|
nr_txbb = desc_size / TXBB_SIZE;
|
|
|
|
if (unlikely(nr_txbb > MAX_DESC_TXBBS)) {
|
|
|
|
if (defrag) {
|
2014-09-23 12:37:01 +00:00
|
|
|
mb = m_defrag(*mbp, M_NOWAIT);
|
|
|
|
if (mb == NULL) {
|
|
|
|
mb = *mbp;
|
|
|
|
goto tx_drop;
|
|
|
|
}
|
|
|
|
*mbp = mb;
|
|
|
|
defrag = 0;
|
|
|
|
goto retry;
|
|
|
|
}
|
|
|
|
en_warn(priv, "Oversized header or SG list\n");
|
2011-03-21 09:58:24 +00:00
|
|
|
goto tx_drop;
|
|
|
|
}
|
|
|
|
|
2014-09-23 12:37:01 +00:00
|
|
|
/* Obtain VLAN information if present */
|
|
|
|
if (mb->m_flags & M_VLANTAG) {
|
|
|
|
vlan_tag = mb->m_pkthdr.ether_vtag;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Check available TXBBs and 2K spare for prefetch
|
|
|
|
* Even if netif_tx_stop_queue() will be called
|
|
|
|
* driver will send current packet to ensure
|
|
|
|
* that at least one completion will be issued after
|
|
|
|
* stopping the queue
|
|
|
|
*/
|
|
|
|
if (unlikely((int)(ring->prod - ring->cons) > ring->full_size)) {
|
2011-03-21 09:58:24 +00:00
|
|
|
/* every full Tx ring stops queue */
|
|
|
|
if (ring->blocked == 0)
|
2014-09-23 12:37:01 +00:00
|
|
|
atomic_add_int(&priv->blocked, 1);
|
|
|
|
/* Set HW-queue-is-full flag */
|
2011-03-21 09:58:24 +00:00
|
|
|
atomic_set_int(&dev->if_drv_flags, IFF_DRV_OACTIVE);
|
|
|
|
ring->blocked = 1;
|
|
|
|
priv->port_stats.queue_stopped++;
|
2014-09-23 12:37:01 +00:00
|
|
|
ring->queue_stopped++;
|
2011-03-21 09:58:24 +00:00
|
|
|
|
|
|
|
/* Use interrupts to find out when queue opened */
|
2014-09-23 12:37:01 +00:00
|
|
|
cq = priv->tx_cq[tx_ind];
|
2011-03-21 09:58:24 +00:00
|
|
|
mlx4_en_arm_cq(priv, cq);
|
|
|
|
return EBUSY;
|
2014-09-23 12:37:01 +00:00
|
|
|
}
|
2011-03-21 09:58:24 +00:00
|
|
|
|
|
|
|
/* Track current inflight packets for performance analysis */
|
|
|
|
AVG_PERF_COUNTER(priv->pstats.inflight_avg,
|
|
|
|
(u32) (ring->prod - ring->cons - 1));
|
|
|
|
|
|
|
|
/* Packet is good - grab an index and transmit it */
|
|
|
|
index = ring->prod & ring->size_mask;
|
|
|
|
bf_index = ring->prod;
|
|
|
|
|
|
|
|
/* See if we have enough space for whole descriptor TXBB for setting
|
|
|
|
* SW ownership on next descriptor; if not, use a bounce buffer. */
|
2014-09-23 12:37:01 +00:00
|
|
|
if (likely(index + nr_txbb <= ring_size))
|
2011-03-21 09:58:24 +00:00
|
|
|
tx_desc = ring->buf + index * TXBB_SIZE;
|
|
|
|
else {
|
|
|
|
tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf;
|
|
|
|
bounce = true;
|
|
|
|
}
|
|
|
|
|
2014-09-23 12:37:01 +00:00
|
|
|
/* Save mb in tx_info ring */
|
|
|
|
tx_info = &ring->tx_info[index];
|
|
|
|
tx_info->mb = mb;
|
|
|
|
tx_info->nr_txbb = nr_txbb;
|
|
|
|
tx_info->nr_segs = nr_segs;
|
|
|
|
|
|
|
|
if (lso_header_size) {
|
|
|
|
memcpy(tx_desc->lso.header, mb->m_data, lso_header_size);
|
|
|
|
data = ((void *)&tx_desc->lso + ALIGN(lso_header_size + 4,
|
|
|
|
DS_SIZE));
|
|
|
|
/* lso header is part of m_data.
|
|
|
|
* need to omit when mapping DMA */
|
|
|
|
mb->m_data += lso_header_size;
|
|
|
|
mb->m_len -= lso_header_size;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
data = &tx_desc->data;
|
|
|
|
|
|
|
|
/* valid only for none inline segments */
|
|
|
|
tx_info->data_offset = (void *)data - (void *)tx_desc;
|
|
|
|
|
|
|
|
if (inl) {
|
|
|
|
tx_info->inl = 1;
|
|
|
|
} else {
|
|
|
|
for (i = 0, m = mb; i < nr_segs; i++, m = m->m_next) {
|
|
|
|
if (m->m_len == 0) {
|
|
|
|
i--;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
dma = pci_map_single(mdev->dev->pdev, m->m_data,
|
|
|
|
m->m_len, PCI_DMA_TODEVICE);
|
|
|
|
data->addr = cpu_to_be64(dma);
|
|
|
|
data->lkey = cpu_to_be32(mdev->mr.key);
|
|
|
|
wmb();
|
|
|
|
data->byte_count = cpu_to_be32(m->m_len);
|
|
|
|
data++;
|
|
|
|
}
|
|
|
|
if (lso_header_size) {
|
|
|
|
mb->m_data -= lso_header_size;
|
|
|
|
mb->m_len += lso_header_size;
|
|
|
|
}
|
|
|
|
tx_info->inl = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2011-03-21 09:58:24 +00:00
|
|
|
/* Prepare ctrl segement apart opcode+ownership, which depends on
|
|
|
|
* whether LSO is used */
|
|
|
|
tx_desc->ctrl.vlan_tag = cpu_to_be16(vlan_tag);
|
2014-09-23 12:37:01 +00:00
|
|
|
tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN *
|
|
|
|
!!vlan_tag;
|
2011-03-21 09:58:24 +00:00
|
|
|
tx_desc->ctrl.fence_size = (real_size / 16) & 0x3f;
|
2014-09-23 12:37:01 +00:00
|
|
|
tx_desc->ctrl.srcrb_flags = priv->ctrl_flags;
|
|
|
|
if (mb->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO |
|
|
|
|
CSUM_TCP | CSUM_UDP | CSUM_TCP_IPV6 | CSUM_UDP_IPV6)) {
|
|
|
|
if (mb->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO))
|
|
|
|
tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM);
|
|
|
|
if (mb->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP |
|
|
|
|
CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
|
|
|
|
tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_TCP_UDP_CSUM);
|
2011-03-21 09:58:24 +00:00
|
|
|
priv->port_stats.tx_chksum_offload++;
|
2014-09-23 12:37:01 +00:00
|
|
|
ring->tx_csum++;
|
|
|
|
}
|
2011-03-21 09:58:24 +00:00
|
|
|
|
|
|
|
if (unlikely(priv->validate_loopback)) {
|
|
|
|
/* Copy dst mac address to wqe */
|
2014-09-23 12:37:01 +00:00
|
|
|
struct ether_header *ethh;
|
|
|
|
u64 mac;
|
|
|
|
u32 mac_l, mac_h;
|
|
|
|
|
|
|
|
ethh = mtod(mb, struct ether_header *);
|
|
|
|
mac = mlx4_en_mac_to_u64(ethh->ether_dhost);
|
|
|
|
if (mac) {
|
|
|
|
mac_h = (u32) ((mac & 0xffff00000000ULL) >> 16);
|
|
|
|
mac_l = (u32) (mac & 0xffffffff);
|
|
|
|
tx_desc->ctrl.srcrb_flags |= cpu_to_be32(mac_h);
|
|
|
|
tx_desc->ctrl.imm = cpu_to_be32(mac_l);
|
|
|
|
}
|
2011-03-21 09:58:24 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Handle LSO (TSO) packets */
|
|
|
|
if (lso_header_size) {
|
|
|
|
int segsz;
|
|
|
|
/* Mark opcode as LSO */
|
|
|
|
op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) |
|
2014-09-23 12:37:01 +00:00
|
|
|
((ring->prod & ring_size) ?
|
2011-03-21 09:58:24 +00:00
|
|
|
cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
|
|
|
|
|
|
|
|
/* Fill in the LSO prefix */
|
|
|
|
tx_desc->lso.mss_hdr_size = cpu_to_be32(
|
|
|
|
mb->m_pkthdr.tso_segsz << 16 | lso_header_size);
|
|
|
|
|
2014-09-23 12:37:01 +00:00
|
|
|
priv->port_stats.tso_packets++;
|
|
|
|
segsz = mb->m_pkthdr.tso_segsz;
|
|
|
|
i = ((mb->m_pkthdr.len - lso_header_size + segsz - 1) / segsz);
|
|
|
|
tx_info->nr_bytes= mb->m_pkthdr.len + (i - 1) * lso_header_size;
|
|
|
|
ring->packets += i;
|
2011-03-21 09:58:24 +00:00
|
|
|
} else {
|
|
|
|
/* Normal (Non LSO) packet */
|
|
|
|
op_own = cpu_to_be32(MLX4_OPCODE_SEND) |
|
2014-09-23 12:37:01 +00:00
|
|
|
((ring->prod & ring_size) ?
|
2011-03-21 09:58:24 +00:00
|
|
|
cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
|
2014-09-23 12:37:01 +00:00
|
|
|
tx_info->nr_bytes = max(mb->m_pkthdr.len,
|
|
|
|
(unsigned int)ETHER_MIN_LEN - ETHER_CRC_LEN);
|
2011-03-21 09:58:24 +00:00
|
|
|
ring->packets++;
|
|
|
|
|
|
|
|
}
|
2014-09-23 12:37:01 +00:00
|
|
|
ring->bytes += tx_info->nr_bytes;
|
2011-03-21 09:58:24 +00:00
|
|
|
AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, mb->m_pkthdr.len);
|
|
|
|
|
2014-09-23 12:37:01 +00:00
|
|
|
if (tx_info->inl) {
|
2011-03-21 09:58:24 +00:00
|
|
|
build_inline_wqe(tx_desc, mb, real_size, &vlan_tag, tx_ind);
|
|
|
|
tx_info->inl = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
ring->prod += nr_txbb;
|
|
|
|
|
2014-09-23 12:37:01 +00:00
|
|
|
|
2011-03-21 09:58:24 +00:00
|
|
|
/* If we used a bounce buffer then copy descriptor back into place */
|
2014-09-23 12:37:01 +00:00
|
|
|
if (unlikely(bounce))
|
2011-03-21 09:58:24 +00:00
|
|
|
tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size);
|
|
|
|
if (ring->bf_enabled && desc_size <= MAX_BF && !bounce && !vlan_tag) {
|
2014-09-23 12:37:01 +00:00
|
|
|
*(__be32 *) (&tx_desc->ctrl.vlan_tag) |= cpu_to_be32(ring->doorbell_qpn);
|
2011-03-21 09:58:24 +00:00
|
|
|
op_own |= htonl((bf_index & 0xffff) << 8);
|
|
|
|
/* Ensure new descirptor hits memory
|
|
|
|
* before setting ownership of this descriptor to HW */
|
|
|
|
wmb();
|
|
|
|
tx_desc->ctrl.owner_opcode = op_own;
|
|
|
|
|
|
|
|
wmb();
|
|
|
|
|
|
|
|
mlx4_bf_copy(ring->bf.reg + ring->bf.offset, (unsigned long *) &tx_desc->ctrl,
|
|
|
|
desc_size);
|
|
|
|
|
|
|
|
wmb();
|
|
|
|
|
|
|
|
ring->bf.offset ^= ring->bf.buf_size;
|
|
|
|
} else {
|
|
|
|
/* Ensure new descirptor hits memory
|
|
|
|
* before setting ownership of this descriptor to HW */
|
|
|
|
wmb();
|
|
|
|
tx_desc->ctrl.owner_opcode = op_own;
|
|
|
|
wmb();
|
2014-09-23 12:37:01 +00:00
|
|
|
writel(cpu_to_be32(ring->doorbell_qpn), ring->bf.uar->map + MLX4_SEND_DOORBELL);
|
2011-03-21 09:58:24 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
tx_drop:
|
|
|
|
*mbp = NULL;
|
|
|
|
m_freem(mb);
|
|
|
|
return EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
mlx4_en_transmit_locked(struct ifnet *dev, int tx_ind, struct mbuf *m)
|
|
|
|
{
|
|
|
|
struct mlx4_en_priv *priv = netdev_priv(dev);
|
|
|
|
struct mlx4_en_tx_ring *ring;
|
|
|
|
struct mbuf *next;
|
|
|
|
int enqueued, err = 0;
|
|
|
|
|
2014-09-23 12:37:01 +00:00
|
|
|
ring = priv->tx_ring[tx_ind];
|
2011-03-21 09:58:24 +00:00
|
|
|
if ((dev->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
|
|
|
|
IFF_DRV_RUNNING || priv->port_up == 0) {
|
|
|
|
if (m != NULL)
|
|
|
|
err = drbr_enqueue(dev, ring->br, m);
|
2014-09-23 12:37:01 +00:00
|
|
|
return (err);
|
2011-03-21 09:58:24 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
enqueued = 0;
|
2013-02-07 15:20:54 +00:00
|
|
|
if (m != NULL) {
|
2011-03-21 09:58:24 +00:00
|
|
|
if ((err = drbr_enqueue(dev, ring->br, m)) != 0)
|
|
|
|
return (err);
|
2013-02-07 15:20:54 +00:00
|
|
|
}
|
2011-03-21 09:58:24 +00:00
|
|
|
/* Process the queue */
|
2013-02-09 04:13:45 +00:00
|
|
|
while ((next = drbr_peek(dev, ring->br)) != NULL) {
|
2011-03-21 09:58:24 +00:00
|
|
|
if ((err = mlx4_en_xmit(dev, tx_ind, &next)) != 0) {
|
2013-02-07 15:20:54 +00:00
|
|
|
if (next == NULL) {
|
2013-02-09 04:13:45 +00:00
|
|
|
drbr_advance(dev, ring->br);
|
2013-02-07 15:20:54 +00:00
|
|
|
} else {
|
2013-02-09 04:13:45 +00:00
|
|
|
drbr_putback(dev, ring->br, next);
|
2013-02-07 15:20:54 +00:00
|
|
|
}
|
2011-03-21 09:58:24 +00:00
|
|
|
break;
|
|
|
|
}
|
2013-02-09 04:13:45 +00:00
|
|
|
drbr_advance(dev, ring->br);
|
2011-03-21 09:58:24 +00:00
|
|
|
enqueued++;
|
|
|
|
if ((dev->if_drv_flags & IFF_DRV_RUNNING) == 0)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (enqueued > 0)
|
|
|
|
ring->watchdog_time = ticks;
|
|
|
|
|
|
|
|
return (err);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
mlx4_en_tx_que(void *context, int pending)
|
|
|
|
{
|
|
|
|
struct mlx4_en_tx_ring *ring;
|
|
|
|
struct mlx4_en_priv *priv;
|
|
|
|
struct net_device *dev;
|
|
|
|
struct mlx4_en_cq *cq;
|
|
|
|
int tx_ind;
|
|
|
|
cq = context;
|
|
|
|
dev = cq->dev;
|
|
|
|
priv = dev->if_softc;
|
|
|
|
tx_ind = cq->ring;
|
2014-09-23 12:37:01 +00:00
|
|
|
ring = priv->tx_ring[tx_ind];
|
2011-03-21 09:58:24 +00:00
|
|
|
if (dev->if_drv_flags & IFF_DRV_RUNNING) {
|
|
|
|
mlx4_en_xmit_poll(priv, tx_ind);
|
|
|
|
spin_lock(&ring->tx_lock);
|
|
|
|
if (!drbr_empty(dev, ring->br))
|
|
|
|
mlx4_en_transmit_locked(dev, tx_ind, NULL);
|
|
|
|
spin_unlock(&ring->tx_lock);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
mlx4_en_transmit(struct ifnet *dev, struct mbuf *m)
|
|
|
|
{
|
|
|
|
struct mlx4_en_priv *priv = netdev_priv(dev);
|
|
|
|
struct mlx4_en_tx_ring *ring;
|
|
|
|
struct mlx4_en_cq *cq;
|
|
|
|
int i = 0, err = 0;
|
|
|
|
|
|
|
|
/* Which queue to use */
|
2014-09-23 12:37:01 +00:00
|
|
|
if ((m->m_flags & (M_FLOWID | M_VLANTAG)) == M_FLOWID) {
|
|
|
|
i = m->m_pkthdr.flowid % (priv->tx_ring_num - 1);
|
|
|
|
}
|
|
|
|
else {
|
2011-03-21 09:58:24 +00:00
|
|
|
i = mlx4_en_select_queue(dev, m);
|
2014-09-23 12:37:01 +00:00
|
|
|
}
|
|
|
|
ring = priv->tx_ring[i];
|
2011-03-21 09:58:24 +00:00
|
|
|
|
|
|
|
if (spin_trylock(&ring->tx_lock)) {
|
|
|
|
err = mlx4_en_transmit_locked(dev, i, m);
|
|
|
|
spin_unlock(&ring->tx_lock);
|
|
|
|
/* Poll CQ here */
|
|
|
|
mlx4_en_xmit_poll(priv, i);
|
|
|
|
} else {
|
|
|
|
err = drbr_enqueue(dev, ring->br, m);
|
2014-09-23 12:37:01 +00:00
|
|
|
cq = priv->tx_cq[i];
|
2011-03-21 09:58:24 +00:00
|
|
|
taskqueue_enqueue(cq->tq, &cq->cq_task);
|
|
|
|
}
|
|
|
|
|
|
|
|
return (err);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Flush ring buffers.
|
|
|
|
*/
|
|
|
|
void
|
|
|
|
mlx4_en_qflush(struct ifnet *dev)
|
|
|
|
{
|
|
|
|
struct mlx4_en_priv *priv = netdev_priv(dev);
|
2014-09-23 12:37:01 +00:00
|
|
|
struct mlx4_en_tx_ring *ring;
|
2011-03-21 09:58:24 +00:00
|
|
|
struct mbuf *m;
|
|
|
|
|
2014-09-23 12:37:01 +00:00
|
|
|
for (int i = 0; i < priv->tx_ring_num; i++) {
|
|
|
|
ring = priv->tx_ring[i];
|
2011-03-21 09:58:24 +00:00
|
|
|
spin_lock(&ring->tx_lock);
|
|
|
|
while ((m = buf_ring_dequeue_sc(ring->br)) != NULL)
|
|
|
|
m_freem(m);
|
|
|
|
spin_unlock(&ring->tx_lock);
|
|
|
|
}
|
|
|
|
if_qflush(dev);
|
|
|
|
}
|