118 lines
2.6 KiB
ArmAsm
118 lines
2.6 KiB
ArmAsm
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// $FreeBSD$
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//
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// Copyright (c) 2000, Intel Corporation
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// All rights reserved.
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//
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// Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache,
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// Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab,
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// Intel Corporation.
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//
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// WARRANTY DISCLAIMER
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
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// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING
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// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Intel Corporation is the author of this code, and requests that all
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// problem reports or change requests be submitted to it directly at
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// http://developer.intel.com/opensource.
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//
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#include <machine/asm.h>
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ENTRY(__divsf3, 0)
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{ .mfi
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// a is in f8
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// b is in f9
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// general registers used: r31, r32, r33, r34
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// predicate registers used: p6
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// floating-point registers used: f6, f7, f8
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nop.m 0
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// load a, the first argument, in f6
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mov f6=f8
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nop.i 0;;
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} { .mfi
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nop.m 0
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// load b, the second argument, in f7
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mov f7=f9
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nop.i 0;;
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} { .mfi
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// BEGIN SINGLE PRECISION LATENCY-OPTIMIZED DIVIDE ALGORITHM
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nop.m 0
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// Step (1)
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// y0 = 1 / b in f8
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frcpa.s0 f8,p6=f6,f7
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nop.i 0;;
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} { .mfi
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nop.m 0
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// Step (2)
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// q0 = a * y0 in f6
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(p6) fma.s1 f6=f6,f8,f0
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nop.i 0
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} { .mfi
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nop.m 0
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// Step (3)
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// e0 = 1 - b * y0 in f7
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(p6) fnma.s1 f7=f7,f8,f1
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nop.i 0;;
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} { .mfi
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nop.m 0
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// Step (4)
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// q1 = q0 + e0 * q0 in f6
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(p6) fma.s1 f6=f7,f6,f6
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nop.i 0
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} { .mfi
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nop.m 0
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// Step (5)
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// e1 = e0 * e0 in f7
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(p6) fma.s1 f7=f7,f7,f0
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nop.i 0;;
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} { .mfi
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nop.m 0
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// Step (6)
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// q2 = q1 + e1 * q1 in f6
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(p6) fma.s1 f6=f7,f6,f6
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nop.i 0
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} { .mfi
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nop.m 0
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// Step (7)
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// e2 = e1 * e1 in f7
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(p6) fma.s1 f7=f7,f7,f0
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nop.i 0;;
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} { .mfi
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nop.m 0
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// Step (8)
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// q3 = q2 + e2 * q2 in f6
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(p6) fma.d.s1 f6=f7,f6,f6
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nop.i 0;;
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} { .mfi
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nop.m 0
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// Step (9)
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// q3' = q3 in f8
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(p6) fma.s.s0 f8=f6,f1,f0
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nop.i 0;;
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// END SINGLE PRECISION LATENCY-OPTIMIZED DIVIDE ALGORITHM
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} { .mmb
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nop.m 0
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nop.m 0
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// return
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br.ret.sptk b0;;
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}
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END(__divsf3)
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