2016-09-27 00:53:41 +00:00
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/*-
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2016-10-08 01:18:01 +00:00
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* Copyright (c) 2016 Justin Hibbits
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2016-09-27 00:53:41 +00:00
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <sys/fbio.h>
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#include <sys/consio.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/videomode/videomode.h>
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#include <dev/videomode/edidvar.h>
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#include <dev/vt/vt.h>
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#include <dev/vt/colors/vt_termcolors.h>
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#include <powerpc/mpc85xx/mpc85xx.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include "fb_if.h"
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#define DIU_DESC_1 0x000 /* Plane1 Area Descriptor Pointer Register */
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#define DIU_DESC_2 0x004 /* Plane2 Area Descriptor Pointer Register */
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#define DIU_DESC_3 0x008 /* Plane3 Area Descriptor Pointer Register */
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#define DIU_GAMMA 0x00C /* Gamma Register */
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#define DIU_PALETTE 0x010 /* Palette Register */
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#define DIU_CURSOR 0x014 /* Cursor Register */
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#define DIU_CURS_POS 0x018 /* Cursor Position Register */
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#define CURSOR_Y_SHIFT 16
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#define CURSOR_X_SHIFT 0
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#define DIU_DIU_MODE 0x01C /* DIU4 Mode */
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#define DIU_MODE_M 0x7
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#define DIU_MODE_S 0
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#define DIU_MODE_NORMAL 0x1
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#define DIU_MODE_2 0x2
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#define DIU_MODE_3 0x3
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#define DIU_MODE_COLBAR 0x4
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#define DIU_BGND 0x020 /* Background */
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#define DIU_BGND_WB 0x024 /* Background Color in write back Mode Register */
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#define DIU_DISP_SIZE 0x028 /* Display Size */
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#define DELTA_Y_S 16
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#define DELTA_X_S 0
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#define DIU_WB_SIZE 0x02C /* Write back Plane Size Register */
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#define DELTA_Y_WB_S 16
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#define DELTA_X_WB_S 0
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#define DIU_WB_MEM_ADDR 0x030 /* Address to Store the write back Plane Register */
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#define DIU_HSYN_PARA 0x034 /* Horizontal Sync Parameter */
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#define BP_H_SHIFT 22
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#define PW_H_SHIFT 11
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#define FP_H_SHIFT 0
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#define DIU_VSYN_PARA 0x038 /* Vertical Sync Parameter */
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#define BP_V_SHIFT 22
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#define PW_V_SHIFT 11
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#define FP_V_SHIFT 0
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#define DIU_SYNPOL 0x03C /* Synchronize Polarity */
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#define BP_VS (1 << 4)
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#define BP_HS (1 << 3)
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#define INV_CS (1 << 2)
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#define INV_VS (1 << 1)
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#define INV_HS (1 << 0)
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#define INV_PDI_VS (1 << 8) /* Polarity of PDI input VSYNC. */
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#define INV_PDI_HS (1 << 9) /* Polarity of PDI input HSYNC. */
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#define INV_PDI_DE (1 << 10) /* Polarity of PDI input DE. */
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#define DIU_THRESHOLD 0x040 /* Threshold */
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#define LS_BF_VS_SHIFT 16
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#define OUT_BUF_LOW_SHIFT 0
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#define DIU_INT_STATUS 0x044 /* Interrupt Status */
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#define DIU_INT_MASK 0x048 /* Interrupt Mask */
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#define DIU_COLBAR_1 0x04C /* COLBAR_1 */
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#define DIU_COLORBARn_R(x) ((x & 0xff) << 16)
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#define DIU_COLORBARn_G(x) ((x & 0xff) << 8)
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#define DIU_COLORBARn_B(x) ((x & 0xff) << 0)
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#define DIU_COLBAR_2 0x050 /* COLBAR_2 */
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#define DIU_COLBAR_3 0x054 /* COLBAR_3 */
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#define DIU_COLBAR_4 0x058 /* COLBAR_4 */
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#define DIU_COLBAR_5 0x05c /* COLBAR_5 */
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#define DIU_COLBAR_6 0x060 /* COLBAR_6 */
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#define DIU_COLBAR_7 0x064 /* COLBAR_7 */
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#define DIU_COLBAR_8 0x068 /* COLBAR_8 */
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#define DIU_FILLING 0x06C /* Filling Register */
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#define DIU_PLUT 0x070 /* Priority Look Up Table Register */
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/* Control Descriptor */
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#define DIU_CTRLDESCL(n, m) 0x200 + (0x40 * n) + 0x4 * (m - 1)
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#define DIU_CTRLDESCLn_1(n) DIU_CTRLDESCL(n, 1)
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#define DIU_CTRLDESCLn_2(n) DIU_CTRLDESCL(n, 2)
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#define DIU_CTRLDESCLn_3(n) DIU_CTRLDESCL(n, 3)
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#define TRANS_SHIFT 20
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#define DIU_CTRLDESCLn_4(n) DIU_CTRLDESCL(n, 4)
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#define BPP_MASK 0xf /* Bit per pixel Mask */
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#define BPP_SHIFT 16 /* Bit per pixel Shift */
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#define BPP24 0x5
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#define EN_LAYER (1 << 31) /* Enable the layer */
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#define DIU_CTRLDESCLn_5(n) DIU_CTRLDESCL(n, 5)
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#define DIU_CTRLDESCLn_6(n) DIU_CTRLDESCL(n, 6)
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#define DIU_CTRLDESCLn_7(n) DIU_CTRLDESCL(n, 7)
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#define DIU_CTRLDESCLn_8(n) DIU_CTRLDESCL(n, 8)
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#define DIU_CTRLDESCLn_9(n) DIU_CTRLDESCL(n, 9)
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#define NUM_LAYERS 1
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struct panel_info {
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uint32_t panel_width;
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uint32_t panel_height;
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uint32_t panel_hbp;
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uint32_t panel_hpw;
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uint32_t panel_hfp;
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uint32_t panel_vbp;
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uint32_t panel_vpw;
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uint32_t panel_vfp;
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uint32_t panel_freq;
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uint32_t clk_div;
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};
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struct diu_area_descriptor {
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uint32_t pixel_format;
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uint32_t bitmap_address;
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uint32_t source_size;
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uint32_t aoi_size;
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uint32_t aoi_offset;
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uint32_t display_offset;
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uint32_t chroma_key_max;
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uint32_t chroma_key_min;
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uint32_t next_ad_addr;
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} __aligned(32);
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struct diu_softc {
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struct resource *res[2];
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void *ih;
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device_t sc_dev;
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device_t sc_fbd; /* fbd child */
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struct fb_info sc_info;
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struct panel_info sc_panel;
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struct diu_area_descriptor *sc_planes[3];
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uint8_t *sc_gamma;
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uint8_t *sc_cursor;
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};
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static struct resource_spec diu_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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static int
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diu_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "fsl,diu"))
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return (ENXIO);
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device_set_desc(dev, "Freescale Display Interface Unit");
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return (BUS_PROBE_DEFAULT);
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}
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static void
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diu_intr(void *arg)
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{
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struct diu_softc *sc;
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int reg;
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sc = arg;
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/* Ack interrupts */
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reg = bus_read_4(sc->res[0], DIU_INT_STATUS);
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bus_write_4(sc->res[0], DIU_INT_STATUS, reg);
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/* TODO interrupt handler */
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}
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static int
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diu_set_pxclk(device_t dev, unsigned int freq)
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{
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unsigned long bus_freq;
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uint32_t pxclk_set;
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uint32_t clkdvd;
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2017-06-14 04:16:37 +00:00
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if ((bus_freq = mpc85xx_get_platform_clock()) <= 0) {
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2016-09-27 00:53:41 +00:00
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device_printf(dev, "Unable to get bus frequency\n");
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return (ENXIO);
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}
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/* freq is in kHz */
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freq *= 1000;
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/* adding freq/2 to round-to-closest */
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pxclk_set = min(max((bus_freq + freq/2) / freq, 2), 255) << 16;
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pxclk_set |= OCP85XX_CLKDVDR_PXCKEN;
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clkdvd = ccsr_read4(OCP85XX_CLKDVDR);
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clkdvd &= ~(OCP85XX_CLKDVDR_PXCKEN | OCP85XX_CLKDVDR_PXCKINV |
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OCP85XX_CLKDVDR_PXCLK_MASK);
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ccsr_write4(OCP85XX_CLKDVDR, clkdvd);
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ccsr_write4(OCP85XX_CLKDVDR, clkdvd | pxclk_set);
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return (0);
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}
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static int
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diu_init(struct diu_softc *sc)
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{
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struct panel_info *panel;
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int reg;
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panel = &sc->sc_panel;
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/* Temporarily disable the DIU while configuring */
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reg = bus_read_4(sc->res[0], DIU_DIU_MODE);
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reg &= ~(DIU_MODE_M << DIU_MODE_S);
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bus_write_4(sc->res[0], DIU_DIU_MODE, reg);
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if (diu_set_pxclk(sc->sc_dev, panel->panel_freq) < 0) {
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return (ENXIO);
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}
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/* Configure DIU */
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/* Need to set these somehow later... */
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bus_write_4(sc->res[0], DIU_GAMMA, vtophys(sc->sc_gamma));
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bus_write_4(sc->res[0], DIU_CURSOR, vtophys(sc->sc_cursor));
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bus_write_4(sc->res[0], DIU_CURS_POS, 0);
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reg = ((sc->sc_info.fb_height) << DELTA_Y_S);
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reg |= sc->sc_info.fb_width;
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bus_write_4(sc->res[0], DIU_DISP_SIZE, reg);
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reg = (panel->panel_hbp << BP_H_SHIFT);
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reg |= (panel->panel_hpw << PW_H_SHIFT);
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reg |= (panel->panel_hfp << FP_H_SHIFT);
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bus_write_4(sc->res[0], DIU_HSYN_PARA, reg);
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reg = (panel->panel_vbp << BP_V_SHIFT);
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reg |= (panel->panel_vpw << PW_V_SHIFT);
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reg |= (panel->panel_vfp << FP_V_SHIFT);
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bus_write_4(sc->res[0], DIU_VSYN_PARA, reg);
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bus_write_4(sc->res[0], DIU_BGND, 0);
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/* Mask all the interrupts */
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bus_write_4(sc->res[0], DIU_INT_MASK, 0x3f);
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/* Reset all layers */
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sc->sc_planes[0] = contigmalloc(sizeof(struct diu_area_descriptor),
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M_DEVBUF, M_ZERO, 0, BUS_SPACE_MAXADDR_32BIT, 32, 0);
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bus_write_4(sc->res[0], DIU_DESC_1, vtophys(sc->sc_planes[0]));
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bus_write_4(sc->res[0], DIU_DESC_2, 0);
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bus_write_4(sc->res[0], DIU_DESC_3, 0);
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/* Setup first plane */
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/* Area descriptor fields are little endian, so byte swap. */
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/* Word 0: Pixel format */
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/* Set to 8:8:8:8 ARGB, 4 bytes per pixel, no flip. */
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#define MAKE_PXLFMT(as,rs,gs,bs,a,r,g,b,f,s) \
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htole32((as << (4 * a)) | (rs << 4 * r) | \
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(gs << 4 * g) | (bs << 4 * b) | \
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(f << 28) | (s << 16) | \
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(a << 25) | (r << 19) | \
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(g << 21) | (b << 24))
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reg = MAKE_PXLFMT(8, 8, 8, 8, 3, 2, 1, 0, 1, 3);
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sc->sc_planes[0]->pixel_format = reg;
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/* Word 1: Bitmap address */
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sc->sc_planes[0]->bitmap_address = htole32(sc->sc_info.fb_pbase);
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/* Word 2: Source size/global alpha */
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reg = (sc->sc_info.fb_width | (sc->sc_info.fb_height << 12));
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sc->sc_planes[0]->source_size = htole32(reg);
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/* Word 3: AOI Size */
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reg = (sc->sc_info.fb_width | (sc->sc_info.fb_height << 16));
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sc->sc_planes[0]->aoi_size = htole32(reg);
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/* Word 4: AOI Offset */
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sc->sc_planes[0]->aoi_offset = 0;
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/* Word 5: Display offset */
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sc->sc_planes[0]->display_offset = 0;
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/* Word 6: Chroma key max */
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sc->sc_planes[0]->chroma_key_max = 0;
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/* Word 7: Chroma key min */
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reg = 255 << 16 | 255 << 8 | 255;
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sc->sc_planes[0]->chroma_key_min = htole32(reg);
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/* Word 8: Next AD */
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sc->sc_planes[0]->next_ad_addr = 0;
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/* TODO: derive this from the panel size */
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|
|
bus_write_4(sc->res[0], DIU_PLUT, 0x1f5f666);
|
|
|
|
|
|
|
|
/* Enable DIU in normal mode */
|
|
|
|
reg = bus_read_4(sc->res[0], DIU_DIU_MODE);
|
|
|
|
reg &= ~(DIU_MODE_M << DIU_MODE_S);
|
|
|
|
reg |= (DIU_MODE_NORMAL << DIU_MODE_S);
|
|
|
|
bus_write_4(sc->res[0], DIU_DIU_MODE, reg);
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
diu_attach(device_t dev)
|
|
|
|
{
|
2017-01-22 05:49:43 +00:00
|
|
|
struct edid_info edid;
|
2016-09-27 00:53:41 +00:00
|
|
|
struct diu_softc *sc;
|
|
|
|
const struct videomode *videomode;
|
|
|
|
void *edid_cells;
|
|
|
|
const char *vm_name;
|
|
|
|
phandle_t node;
|
|
|
|
int h, r, w;
|
|
|
|
int err, i;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
sc->sc_dev = dev;
|
|
|
|
|
|
|
|
if (bus_alloc_resources(dev, diu_spec, sc->res)) {
|
|
|
|
device_printf(dev, "could not allocate resources\n");
|
|
|
|
return (ENXIO);
|
|
|
|
}
|
|
|
|
|
|
|
|
node = ofw_bus_get_node(dev);
|
|
|
|
/* Setup interrupt handler */
|
|
|
|
err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_BIO | INTR_MPSAFE,
|
|
|
|
NULL, diu_intr, sc, &sc->ih);
|
|
|
|
if (err) {
|
|
|
|
device_printf(dev, "Unable to alloc interrupt resource.\n");
|
|
|
|
return (ENXIO);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* TODO: Eventually, allow EDID to be dynamically provided. */
|
2018-04-08 22:59:34 +00:00
|
|
|
if (OF_getprop_alloc(node, "edid", &edid_cells) <= 0) {
|
2018-04-16 04:02:53 +00:00
|
|
|
/* Get a resource hint: hint.fb.N.mode */
|
|
|
|
if (resource_string_value(device_get_name(dev),
|
|
|
|
device_get_unit(dev), "mode", &vm_name) != 0) {
|
2016-09-27 00:53:41 +00:00
|
|
|
device_printf(dev,
|
|
|
|
"No EDID data and no video-mode env set\n");
|
|
|
|
return (ENXIO);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (edid_cells != NULL) {
|
2017-01-22 05:49:43 +00:00
|
|
|
if (edid_parse(edid_cells, &edid) != 0) {
|
2016-09-27 00:53:41 +00:00
|
|
|
device_printf(dev, "Error parsing EDID\n");
|
|
|
|
OF_prop_free(edid_cells);
|
|
|
|
return (ENXIO);
|
|
|
|
}
|
2017-01-22 06:17:31 +00:00
|
|
|
videomode = edid.edid_preferred_mode;
|
2016-09-27 00:53:41 +00:00
|
|
|
} else {
|
|
|
|
/* Parse video-mode kenv variable. */
|
2018-04-16 04:02:53 +00:00
|
|
|
if ((err = sscanf(vm_name, "%dx%d@%d", &w, &h, &r)) != 3) {
|
2016-09-27 00:53:41 +00:00
|
|
|
device_printf(dev,
|
|
|
|
"Cannot parse video mode: %s\n", vm_name);
|
|
|
|
return (ENXIO);
|
|
|
|
}
|
|
|
|
videomode = pick_mode_by_ref(w, h, r);
|
|
|
|
if (videomode == NULL) {
|
|
|
|
device_printf(dev,
|
|
|
|
"Cannot find mode for %dx%d@%d", w, h, r);
|
|
|
|
return (ENXIO);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
sc->sc_panel.panel_width = videomode->hdisplay;
|
|
|
|
sc->sc_panel.panel_height = videomode->vdisplay;
|
|
|
|
sc->sc_panel.panel_hbp = videomode->hsync_start - videomode->hdisplay;
|
|
|
|
sc->sc_panel.panel_hfp = videomode->htotal - videomode->hsync_end;
|
|
|
|
sc->sc_panel.panel_hpw = videomode->hsync_end - videomode->hsync_start;
|
|
|
|
sc->sc_panel.panel_vbp = videomode->vsync_start - videomode->vdisplay;
|
|
|
|
sc->sc_panel.panel_vfp = videomode->vtotal - videomode->vsync_end;
|
|
|
|
sc->sc_panel.panel_vpw = videomode->vsync_end - videomode->vsync_start;
|
|
|
|
sc->sc_panel.panel_freq = videomode->dot_clock;
|
|
|
|
|
|
|
|
sc->sc_info.fb_width = sc->sc_panel.panel_width;
|
|
|
|
sc->sc_info.fb_height = sc->sc_panel.panel_height;
|
|
|
|
sc->sc_info.fb_stride = sc->sc_info.fb_width * 4;
|
|
|
|
sc->sc_info.fb_bpp = sc->sc_info.fb_depth = 32;
|
|
|
|
sc->sc_info.fb_size = sc->sc_info.fb_height * sc->sc_info.fb_stride;
|
|
|
|
sc->sc_info.fb_vbase = (intptr_t)contigmalloc(sc->sc_info.fb_size,
|
|
|
|
M_DEVBUF, M_ZERO, 0, BUS_SPACE_MAXADDR_32BIT, PAGE_SIZE, 0);
|
|
|
|
sc->sc_info.fb_pbase = (intptr_t)vtophys(sc->sc_info.fb_vbase);
|
2017-12-02 01:42:07 +00:00
|
|
|
sc->sc_info.fb_flags = FB_FLAG_MEMATTR;
|
|
|
|
sc->sc_info.fb_memattr = VM_MEMATTR_DEFAULT;
|
2020-09-01 21:20:08 +00:00
|
|
|
|
2016-09-27 00:53:41 +00:00
|
|
|
/* Gamma table is 3 consecutive segments of 256 bytes. */
|
|
|
|
sc->sc_gamma = contigmalloc(3 * 256, M_DEVBUF, 0, 0,
|
|
|
|
BUS_SPACE_MAXADDR_32BIT, PAGE_SIZE, 0);
|
|
|
|
/* Initialize gamma to default */
|
|
|
|
for (i = 0; i < 3 * 256; i++)
|
|
|
|
sc->sc_gamma[i] = (i % 256);
|
|
|
|
|
|
|
|
/* Cursor format is 32x32x16bpp */
|
|
|
|
sc->sc_cursor = contigmalloc(32 * 32 * 2, M_DEVBUF, M_ZERO, 0,
|
|
|
|
BUS_SPACE_MAXADDR_32BIT, PAGE_SIZE, 0);
|
|
|
|
|
|
|
|
diu_init(sc);
|
|
|
|
|
|
|
|
sc->sc_info.fb_name = device_get_nameunit(dev);
|
|
|
|
|
|
|
|
/* Ask newbus to attach framebuffer device to me. */
|
|
|
|
sc->sc_fbd = device_add_child(dev, "fbd", device_get_unit(dev));
|
|
|
|
if (sc->sc_fbd == NULL)
|
|
|
|
device_printf(dev, "Can't attach fbd device\n");
|
|
|
|
|
|
|
|
if ((err = device_probe_and_attach(sc->sc_fbd)) != 0) {
|
|
|
|
device_printf(dev, "Failed to attach fbd device: %d\n", err);
|
|
|
|
}
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct fb_info *
|
|
|
|
diu_fb_getinfo(device_t dev)
|
|
|
|
{
|
|
|
|
struct diu_softc *sc = device_get_softc(dev);
|
|
|
|
|
|
|
|
return (&sc->sc_info);
|
|
|
|
}
|
|
|
|
|
|
|
|
static device_method_t diu_methods[] = {
|
|
|
|
DEVMETHOD(device_probe, diu_probe),
|
|
|
|
DEVMETHOD(device_attach, diu_attach),
|
|
|
|
|
|
|
|
/* Framebuffer service methods */
|
|
|
|
DEVMETHOD(fb_getinfo, diu_fb_getinfo),
|
|
|
|
{ 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static driver_t diu_driver = {
|
|
|
|
"fb",
|
|
|
|
diu_methods,
|
|
|
|
sizeof(struct diu_softc),
|
|
|
|
};
|
|
|
|
|
2022-05-10 17:21:38 +00:00
|
|
|
DRIVER_MODULE(fb, simplebus, diu_driver, 0, 0);
|