2013-11-11 16:14:25 +00:00
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/*-
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2017-11-27 15:09:59 +00:00
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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2013-11-11 16:14:25 +00:00
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* Copyright (c) 2008-2012 Semihalf.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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2015-12-30 03:43:25 +00:00
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#include "opt_platform.h"
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2013-11-11 16:14:25 +00:00
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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2019-02-27 03:30:49 +00:00
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#include <sys/module.h>
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2013-11-11 16:14:25 +00:00
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#include <sys/bus.h>
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#include <sys/pcpu.h>
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#include <sys/proc.h>
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#include <sys/smp.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/hid.h>
|
Add ePAPR boot support for PowerPC book-E (MPC85xx) hardware
Summary:
u-boot, following the ePAPR specification, puts secondary cores into a
spinloop at boot, rather than leaving them shut off. It then relies on the host
OS to write the correct values to a special spin table, located in coherent
memory (on newer implementations), or noncoherent memory (older
implementations).
This supports both implementations of ePAPR, as well as continuing to support
non-ePAPR booting, by first attempting to use the spintable, and falling back to
expecting non-started CPUs.
Test Plan:
Booted on a P5020 board. Tested before and after the changes.
Before the changes, prints the error "SMP: CPU 1 already out of hold-off state!"
and panics shortly thereafter. After the changes, same boot method lets it
complete boot.
Reviewed by: nwhitehorn
MFC after: 2 weeks
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
Differential Revision: https://reviews.freebsd.org/D7494
2016-08-13 16:16:02 +00:00
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#include <machine/_inttypes.h>
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2015-12-30 03:43:25 +00:00
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#include <machine/machdep.h>
|
Add ePAPR boot support for PowerPC book-E (MPC85xx) hardware
Summary:
u-boot, following the ePAPR specification, puts secondary cores into a
spinloop at boot, rather than leaving them shut off. It then relies on the host
OS to write the correct values to a special spin table, located in coherent
memory (on newer implementations), or noncoherent memory (older
implementations).
This supports both implementations of ePAPR, as well as continuing to support
non-ePAPR booting, by first attempting to use the spintable, and falling back to
expecting non-started CPUs.
Test Plan:
Booted on a P5020 board. Tested before and after the changes.
Before the changes, prints the error "SMP: CPU 1 already out of hold-off state!"
and panics shortly thereafter. After the changes, same boot method lets it
complete boot.
Reviewed by: nwhitehorn
MFC after: 2 weeks
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
Differential Revision: https://reviews.freebsd.org/D7494
2016-08-13 16:16:02 +00:00
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#include <machine/md_var.h>
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2013-11-11 16:14:25 +00:00
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#include <machine/platform.h>
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#include <machine/platformvar.h>
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#include <machine/smp.h>
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#include <machine/spr.h>
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#include <machine/vmparam.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/ofw/openfirm.h>
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2013-11-17 02:03:36 +00:00
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#include <vm/vm.h>
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#include <vm/pmap.h>
|
Add ePAPR boot support for PowerPC book-E (MPC85xx) hardware
Summary:
u-boot, following the ePAPR specification, puts secondary cores into a
spinloop at boot, rather than leaving them shut off. It then relies on the host
OS to write the correct values to a special spin table, located in coherent
memory (on newer implementations), or noncoherent memory (older
implementations).
This supports both implementations of ePAPR, as well as continuing to support
non-ePAPR booting, by first attempting to use the spintable, and falling back to
expecting non-started CPUs.
Test Plan:
Booted on a P5020 board. Tested before and after the changes.
Before the changes, prints the error "SMP: CPU 1 already out of hold-off state!"
and panics shortly thereafter. After the changes, same boot method lets it
complete boot.
Reviewed by: nwhitehorn
MFC after: 2 weeks
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
Differential Revision: https://reviews.freebsd.org/D7494
2016-08-13 16:16:02 +00:00
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#include <vm/vm_extern.h>
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2013-11-17 02:03:36 +00:00
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2013-11-11 16:14:25 +00:00
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#include <powerpc/mpc85xx/mpc85xx.h>
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#include "platform_if.h"
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#ifdef SMP
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extern void *ap_pcpu;
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extern vm_paddr_t kernload; /* Kernel physical load address */
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extern uint8_t __boot_page[]; /* Boot page body */
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2019-11-02 21:15:56 +00:00
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extern vm_paddr_t bp_kernload; /* Boot page copy of kernload */
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extern vm_offset_t bp_virtaddr; /* Virtual address of boot page */
|
2018-11-28 02:00:27 +00:00
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extern vm_offset_t __startkernel;
|
Add ePAPR boot support for PowerPC book-E (MPC85xx) hardware
Summary:
u-boot, following the ePAPR specification, puts secondary cores into a
spinloop at boot, rather than leaving them shut off. It then relies on the host
OS to write the correct values to a special spin table, located in coherent
memory (on newer implementations), or noncoherent memory (older
implementations).
This supports both implementations of ePAPR, as well as continuing to support
non-ePAPR booting, by first attempting to use the spintable, and falling back to
expecting non-started CPUs.
Test Plan:
Booted on a P5020 board. Tested before and after the changes.
Before the changes, prints the error "SMP: CPU 1 already out of hold-off state!"
and panics shortly thereafter. After the changes, same boot method lets it
complete boot.
Reviewed by: nwhitehorn
MFC after: 2 weeks
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
Differential Revision: https://reviews.freebsd.org/D7494
2016-08-13 16:16:02 +00:00
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struct cpu_release {
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uint32_t entry_h;
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uint32_t entry_l;
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uint32_t r3_h;
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uint32_t r3_l;
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uint32_t reserved;
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uint32_t pir;
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};
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2013-11-11 16:14:25 +00:00
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#endif
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extern uint32_t *bootinfo;
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2016-11-16 05:24:42 +00:00
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vm_paddr_t ccsrbar_pa;
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2013-11-17 02:03:36 +00:00
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vm_offset_t ccsrbar_va;
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2016-11-16 05:24:42 +00:00
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vm_size_t ccsrbar_size;
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2013-11-11 16:14:25 +00:00
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static int cpu, maxcpu;
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2019-02-27 03:30:49 +00:00
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static device_t rcpm_dev;
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static void dummy_freeze(device_t, bool);
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static void (*freeze_timebase)(device_t, bool) = dummy_freeze;
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2013-11-11 16:14:25 +00:00
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static int mpc85xx_probe(platform_t);
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2013-12-01 19:43:15 +00:00
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static void mpc85xx_mem_regions(platform_t, struct mem_region *phys,
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int *physsz, struct mem_region *avail, int *availsz);
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2013-11-11 16:14:25 +00:00
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static u_long mpc85xx_timebase_freq(platform_t, struct cpuref *cpuref);
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static int mpc85xx_smp_first_cpu(platform_t, struct cpuref *cpuref);
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static int mpc85xx_smp_next_cpu(platform_t, struct cpuref *cpuref);
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static int mpc85xx_smp_get_bsp(platform_t, struct cpuref *cpuref);
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static int mpc85xx_smp_start_cpu(platform_t, struct pcpu *cpu);
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2017-11-25 21:59:59 +00:00
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static void mpc85xx_smp_timebase_sync(platform_t, u_long tb, int ap);
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2013-11-11 16:14:25 +00:00
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static void mpc85xx_reset(platform_t);
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static platform_method_t mpc85xx_methods[] = {
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PLATFORMMETHOD(platform_probe, mpc85xx_probe),
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PLATFORMMETHOD(platform_attach, mpc85xx_attach),
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PLATFORMMETHOD(platform_mem_regions, mpc85xx_mem_regions),
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PLATFORMMETHOD(platform_timebase_freq, mpc85xx_timebase_freq),
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PLATFORMMETHOD(platform_smp_first_cpu, mpc85xx_smp_first_cpu),
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PLATFORMMETHOD(platform_smp_next_cpu, mpc85xx_smp_next_cpu),
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PLATFORMMETHOD(platform_smp_get_bsp, mpc85xx_smp_get_bsp),
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PLATFORMMETHOD(platform_smp_start_cpu, mpc85xx_smp_start_cpu),
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2017-11-25 21:59:59 +00:00
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PLATFORMMETHOD(platform_smp_timebase_sync, mpc85xx_smp_timebase_sync),
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2013-11-11 16:14:25 +00:00
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PLATFORMMETHOD(platform_reset, mpc85xx_reset),
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PLATFORMMETHOD_END
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};
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2015-08-22 03:29:12 +00:00
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DEFINE_CLASS_0(mpc85xx, mpc85xx_platform, mpc85xx_methods, 0);
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2013-11-11 16:14:25 +00:00
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PLATFORM_DEF(mpc85xx_platform);
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static int
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mpc85xx_probe(platform_t plat)
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{
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2016-08-30 02:09:40 +00:00
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u_int pvr = (mfpvr() >> 16) & 0xFFFF;
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switch (pvr) {
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case FSL_E500v1:
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case FSL_E500v2:
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case FSL_E500mc:
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case FSL_E5500:
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case FSL_E6500:
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return (BUS_PROBE_DEFAULT);
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}
|
2013-11-11 16:14:25 +00:00
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return (ENXIO);
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}
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|
2015-08-22 03:29:12 +00:00
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int
|
2013-11-11 16:14:25 +00:00
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mpc85xx_attach(platform_t plat)
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{
|
2013-11-17 02:03:36 +00:00
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phandle_t cpus, child, ccsr;
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const char *soc_name_guesses[] = {"/soc", "soc", NULL};
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const char **name;
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pcell_t ranges[6], acells, pacells, scells;
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uint64_t ccsrbar, ccsrsize;
|
2016-08-30 02:09:40 +00:00
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int i;
|
2013-11-11 16:14:25 +00:00
|
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if ((cpus = OF_finddevice("/cpus")) != -1) {
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for (maxcpu = 0, child = OF_child(cpus); child != 0;
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child = OF_peer(child), maxcpu++)
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;
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} else
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maxcpu = 1;
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|
2013-11-17 02:03:36 +00:00
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/*
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* Locate CCSR region. Irritatingly, there is no way to find it
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* unless you already know where it is. Try to infer its location
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* from the device tree.
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*/
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ccsr = -1;
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for (name = soc_name_guesses; *name != NULL && ccsr == -1; name++)
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ccsr = OF_finddevice(*name);
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if (ccsr == -1) {
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char type[64];
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/* That didn't work. Search for devices of type "soc" */
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child = OF_child(OF_peer(0));
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for (OF_child(child); child != 0; child = OF_peer(child)) {
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if (OF_getprop(child, "device_type", type, sizeof(type))
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<= 0)
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continue;
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if (strcmp(type, "soc") == 0) {
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ccsr = child;
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break;
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}
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}
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}
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if (ccsr == -1)
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panic("Could not locate CCSR window!");
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OF_getprop(ccsr, "#size-cells", &scells, sizeof(scells));
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OF_getprop(ccsr, "#address-cells", &acells, sizeof(acells));
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OF_searchprop(OF_parent(ccsr), "#address-cells", &pacells,
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sizeof(pacells));
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OF_getprop(ccsr, "ranges", ranges, sizeof(ranges));
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ccsrbar = ccsrsize = 0;
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for (i = acells; i < acells + pacells; i++) {
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ccsrbar <<= 32;
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ccsrbar |= ranges[i];
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|
|
}
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for (i = acells + pacells; i < acells + pacells + scells; i++) {
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ccsrsize <<= 32;
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|
ccsrsize |= ranges[i];
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|
|
}
|
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|
ccsrbar_va = pmap_early_io_map(ccsrbar, ccsrsize);
|
2016-11-16 05:24:42 +00:00
|
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|
ccsrbar_pa = ccsrbar;
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ccsrbar_size = ccsrsize;
|
2013-11-17 02:03:36 +00:00
|
|
|
|
2015-12-30 03:43:25 +00:00
|
|
|
mpc85xx_enable_l3_cache();
|
|
|
|
|
2013-11-11 16:14:25 +00:00
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2013-12-01 19:43:15 +00:00
|
|
|
mpc85xx_mem_regions(platform_t plat, struct mem_region *phys, int *physsz,
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|
|
|
struct mem_region *avail, int *availsz)
|
2013-11-11 16:14:25 +00:00
|
|
|
{
|
|
|
|
|
|
|
|
ofw_mem_regions(phys, physsz, avail, availsz);
|
|
|
|
}
|
|
|
|
|
|
|
|
static u_long
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|
|
|
mpc85xx_timebase_freq(platform_t plat, struct cpuref *cpuref)
|
|
|
|
{
|
|
|
|
u_long ticks;
|
|
|
|
phandle_t cpus, child;
|
|
|
|
pcell_t freq;
|
|
|
|
|
|
|
|
if (bootinfo != NULL) {
|
|
|
|
if (bootinfo[0] == 1) {
|
|
|
|
/* Backward compatibility. See 8-STABLE. */
|
|
|
|
ticks = bootinfo[3] >> 3;
|
|
|
|
} else {
|
|
|
|
/* Compatibility with Juniper's loader. */
|
|
|
|
ticks = bootinfo[5] >> 3;
|
|
|
|
}
|
|
|
|
} else
|
|
|
|
ticks = 0;
|
|
|
|
|
|
|
|
if ((cpus = OF_finddevice("/cpus")) == -1)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
if ((child = OF_child(cpus)) == 0)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
switch (OF_getproplen(child, "timebase-frequency")) {
|
|
|
|
case 4:
|
|
|
|
{
|
|
|
|
uint32_t tbase;
|
|
|
|
OF_getprop(child, "timebase-frequency", &tbase, sizeof(tbase));
|
|
|
|
ticks = tbase;
|
|
|
|
return (ticks);
|
|
|
|
}
|
|
|
|
case 8:
|
|
|
|
{
|
|
|
|
uint64_t tbase;
|
|
|
|
OF_getprop(child, "timebase-frequency", &tbase, sizeof(tbase));
|
|
|
|
ticks = tbase;
|
|
|
|
return (ticks);
|
|
|
|
}
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
freq = 0;
|
|
|
|
if (OF_getprop(child, "bus-frequency", (void *)&freq,
|
|
|
|
sizeof(freq)) <= 0)
|
|
|
|
goto out;
|
|
|
|
|
2016-08-03 01:22:11 +00:00
|
|
|
if (freq == 0)
|
|
|
|
goto out;
|
|
|
|
|
2013-11-11 16:14:25 +00:00
|
|
|
/*
|
|
|
|
* Time Base and Decrementer are updated every 8 CCB bus clocks.
|
|
|
|
* HID0[SEL_TBCLK] = 0
|
|
|
|
*/
|
2016-08-03 01:22:11 +00:00
|
|
|
if (mpc85xx_is_qoriq())
|
2015-12-30 03:43:25 +00:00
|
|
|
ticks = freq / 32;
|
2016-08-03 01:22:11 +00:00
|
|
|
else
|
2013-11-11 16:14:25 +00:00
|
|
|
ticks = freq / 8;
|
|
|
|
|
|
|
|
out:
|
|
|
|
if (ticks <= 0)
|
|
|
|
panic("Unable to determine timebase frequency!");
|
|
|
|
|
|
|
|
return (ticks);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
mpc85xx_smp_first_cpu(platform_t plat, struct cpuref *cpuref)
|
|
|
|
{
|
|
|
|
|
|
|
|
cpu = 0;
|
|
|
|
cpuref->cr_cpuid = cpu;
|
|
|
|
cpuref->cr_hwref = cpuref->cr_cpuid;
|
|
|
|
if (bootverbose)
|
|
|
|
printf("powerpc_smp_first_cpu: cpuid %d\n", cpuref->cr_cpuid);
|
|
|
|
cpu++;
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
mpc85xx_smp_next_cpu(platform_t plat, struct cpuref *cpuref)
|
|
|
|
{
|
|
|
|
|
|
|
|
if (cpu >= maxcpu)
|
|
|
|
return (ENOENT);
|
|
|
|
|
|
|
|
cpuref->cr_cpuid = cpu++;
|
|
|
|
cpuref->cr_hwref = cpuref->cr_cpuid;
|
|
|
|
if (bootverbose)
|
|
|
|
printf("powerpc_smp_next_cpu: cpuid %d\n", cpuref->cr_cpuid);
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
mpc85xx_smp_get_bsp(platform_t plat, struct cpuref *cpuref)
|
|
|
|
{
|
|
|
|
|
|
|
|
cpuref->cr_cpuid = mfspr(SPR_PIR);
|
|
|
|
cpuref->cr_hwref = cpuref->cr_cpuid;
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
Add ePAPR boot support for PowerPC book-E (MPC85xx) hardware
Summary:
u-boot, following the ePAPR specification, puts secondary cores into a
spinloop at boot, rather than leaving them shut off. It then relies on the host
OS to write the correct values to a special spin table, located in coherent
memory (on newer implementations), or noncoherent memory (older
implementations).
This supports both implementations of ePAPR, as well as continuing to support
non-ePAPR booting, by first attempting to use the spintable, and falling back to
expecting non-started CPUs.
Test Plan:
Booted on a P5020 board. Tested before and after the changes.
Before the changes, prints the error "SMP: CPU 1 already out of hold-off state!"
and panics shortly thereafter. After the changes, same boot method lets it
complete boot.
Reviewed by: nwhitehorn
MFC after: 2 weeks
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
Differential Revision: https://reviews.freebsd.org/D7494
2016-08-13 16:16:02 +00:00
|
|
|
#ifdef SMP
|
|
|
|
static int
|
|
|
|
mpc85xx_smp_start_cpu_epapr(platform_t plat, struct pcpu *pc)
|
|
|
|
{
|
|
|
|
vm_paddr_t rel_pa, bptr;
|
|
|
|
volatile struct cpu_release *rel;
|
|
|
|
vm_offset_t rel_va, rel_page;
|
|
|
|
phandle_t node;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* If we're calling this, the node already exists. */
|
|
|
|
node = OF_finddevice("/cpus");
|
|
|
|
for (i = 0, node = OF_child(node); i < pc->pc_cpuid;
|
|
|
|
i++, node = OF_peer(node))
|
|
|
|
;
|
|
|
|
if (OF_getencprop(node, "cpu-release-addr", (pcell_t *)&rel_pa,
|
|
|
|
sizeof(rel_pa)) == -1) {
|
|
|
|
return (ENOENT);
|
|
|
|
}
|
|
|
|
|
|
|
|
rel_page = kva_alloc(PAGE_SIZE);
|
|
|
|
if (rel_page == 0)
|
|
|
|
return (ENOMEM);
|
|
|
|
|
|
|
|
critical_enter();
|
|
|
|
rel_va = rel_page + (rel_pa & PAGE_MASK);
|
|
|
|
pmap_kenter(rel_page, rel_pa & ~PAGE_MASK);
|
|
|
|
rel = (struct cpu_release *)rel_va;
|
2018-12-10 04:16:40 +00:00
|
|
|
bptr = pmap_kextract((uintptr_t)__boot_page);
|
2019-11-02 21:15:56 +00:00
|
|
|
|
|
|
|
cpu_flush_dcache(__DEVOLATILE(struct cpu_release *,rel), sizeof(*rel));
|
|
|
|
rel->pir = pc->pc_cpuid; __asm __volatile("sync" ::: "memory");
|
|
|
|
rel->entry_h = (bptr >> 32); __asm __volatile("sync" ::: "memory");
|
Add ePAPR boot support for PowerPC book-E (MPC85xx) hardware
Summary:
u-boot, following the ePAPR specification, puts secondary cores into a
spinloop at boot, rather than leaving them shut off. It then relies on the host
OS to write the correct values to a special spin table, located in coherent
memory (on newer implementations), or noncoherent memory (older
implementations).
This supports both implementations of ePAPR, as well as continuing to support
non-ePAPR booting, by first attempting to use the spintable, and falling back to
expecting non-started CPUs.
Test Plan:
Booted on a P5020 board. Tested before and after the changes.
Before the changes, prints the error "SMP: CPU 1 already out of hold-off state!"
and panics shortly thereafter. After the changes, same boot method lets it
complete boot.
Reviewed by: nwhitehorn
MFC after: 2 weeks
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
Differential Revision: https://reviews.freebsd.org/D7494
2016-08-13 16:16:02 +00:00
|
|
|
cpu_flush_dcache(__DEVOLATILE(struct cpu_release *,rel), sizeof(*rel));
|
2019-11-02 21:15:56 +00:00
|
|
|
rel->entry_l = bptr & 0xffffffff; __asm __volatile("sync" ::: "memory");
|
Add ePAPR boot support for PowerPC book-E (MPC85xx) hardware
Summary:
u-boot, following the ePAPR specification, puts secondary cores into a
spinloop at boot, rather than leaving them shut off. It then relies on the host
OS to write the correct values to a special spin table, located in coherent
memory (on newer implementations), or noncoherent memory (older
implementations).
This supports both implementations of ePAPR, as well as continuing to support
non-ePAPR booting, by first attempting to use the spintable, and falling back to
expecting non-started CPUs.
Test Plan:
Booted on a P5020 board. Tested before and after the changes.
Before the changes, prints the error "SMP: CPU 1 already out of hold-off state!"
and panics shortly thereafter. After the changes, same boot method lets it
complete boot.
Reviewed by: nwhitehorn
MFC after: 2 weeks
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
Differential Revision: https://reviews.freebsd.org/D7494
2016-08-13 16:16:02 +00:00
|
|
|
cpu_flush_dcache(__DEVOLATILE(struct cpu_release *,rel), sizeof(*rel));
|
|
|
|
if (bootverbose)
|
|
|
|
printf("Waking up CPU %d via CPU release page %p\n",
|
|
|
|
pc->pc_cpuid, rel);
|
|
|
|
critical_exit();
|
|
|
|
pmap_kremove(rel_page);
|
|
|
|
kva_free(rel_page, PAGE_SIZE);
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2013-11-11 16:14:25 +00:00
|
|
|
static int
|
|
|
|
mpc85xx_smp_start_cpu(platform_t plat, struct pcpu *pc)
|
|
|
|
{
|
|
|
|
#ifdef SMP
|
2015-12-30 03:43:25 +00:00
|
|
|
vm_paddr_t bptr;
|
|
|
|
uint32_t reg;
|
2016-04-19 01:48:18 +00:00
|
|
|
int timeout;
|
2015-12-30 03:43:25 +00:00
|
|
|
uintptr_t brr;
|
|
|
|
int cpuid;
|
Add ePAPR boot support for PowerPC book-E (MPC85xx) hardware
Summary:
u-boot, following the ePAPR specification, puts secondary cores into a
spinloop at boot, rather than leaving them shut off. It then relies on the host
OS to write the correct values to a special spin table, located in coherent
memory (on newer implementations), or noncoherent memory (older
implementations).
This supports both implementations of ePAPR, as well as continuing to support
non-ePAPR booting, by first attempting to use the spintable, and falling back to
expecting non-started CPUs.
Test Plan:
Booted on a P5020 board. Tested before and after the changes.
Before the changes, prints the error "SMP: CPU 1 already out of hold-off state!"
and panics shortly thereafter. After the changes, same boot method lets it
complete boot.
Reviewed by: nwhitehorn
MFC after: 2 weeks
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
Differential Revision: https://reviews.freebsd.org/D7494
2016-08-13 16:16:02 +00:00
|
|
|
int epapr_boot = 0;
|
2015-12-30 03:43:25 +00:00
|
|
|
uint32_t tgt;
|
2013-11-11 16:14:25 +00:00
|
|
|
|
2016-08-03 01:22:11 +00:00
|
|
|
if (mpc85xx_is_qoriq()) {
|
|
|
|
reg = ccsr_read4(OCP85XX_COREDISR);
|
|
|
|
cpuid = pc->pc_cpuid;
|
2015-12-30 03:43:25 +00:00
|
|
|
|
2016-08-03 01:22:11 +00:00
|
|
|
if ((reg & (1 << cpuid)) != 0) {
|
|
|
|
printf("%s: CPU %d is disabled!\n", __func__, pc->pc_cpuid);
|
|
|
|
return (-1);
|
|
|
|
}
|
2015-12-30 03:43:25 +00:00
|
|
|
|
2016-08-03 01:22:11 +00:00
|
|
|
brr = OCP85XX_BRR;
|
|
|
|
} else {
|
|
|
|
brr = OCP85XX_EEBPCR;
|
|
|
|
cpuid = pc->pc_cpuid + 24;
|
|
|
|
}
|
2016-04-19 01:48:18 +00:00
|
|
|
bp_kernload = kernload;
|
2019-11-02 21:15:56 +00:00
|
|
|
bp_virtaddr = (vm_offset_t)&__boot_page;
|
Add ePAPR boot support for PowerPC book-E (MPC85xx) hardware
Summary:
u-boot, following the ePAPR specification, puts secondary cores into a
spinloop at boot, rather than leaving them shut off. It then relies on the host
OS to write the correct values to a special spin table, located in coherent
memory (on newer implementations), or noncoherent memory (older
implementations).
This supports both implementations of ePAPR, as well as continuing to support
non-ePAPR booting, by first attempting to use the spintable, and falling back to
expecting non-started CPUs.
Test Plan:
Booted on a P5020 board. Tested before and after the changes.
Before the changes, prints the error "SMP: CPU 1 already out of hold-off state!"
and panics shortly thereafter. After the changes, same boot method lets it
complete boot.
Reviewed by: nwhitehorn
MFC after: 2 weeks
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
Differential Revision: https://reviews.freebsd.org/D7494
2016-08-13 16:16:02 +00:00
|
|
|
/*
|
2019-11-02 21:15:56 +00:00
|
|
|
* bp_kernload and bp_virtaddr are in the boot page. Sync the cache
|
|
|
|
* because ePAPR booting has the other core(s) already running.
|
Add ePAPR boot support for PowerPC book-E (MPC85xx) hardware
Summary:
u-boot, following the ePAPR specification, puts secondary cores into a
spinloop at boot, rather than leaving them shut off. It then relies on the host
OS to write the correct values to a special spin table, located in coherent
memory (on newer implementations), or noncoherent memory (older
implementations).
This supports both implementations of ePAPR, as well as continuing to support
non-ePAPR booting, by first attempting to use the spintable, and falling back to
expecting non-started CPUs.
Test Plan:
Booted on a P5020 board. Tested before and after the changes.
Before the changes, prints the error "SMP: CPU 1 already out of hold-off state!"
and panics shortly thereafter. After the changes, same boot method lets it
complete boot.
Reviewed by: nwhitehorn
MFC after: 2 weeks
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
Differential Revision: https://reviews.freebsd.org/D7494
2016-08-13 16:16:02 +00:00
|
|
|
*/
|
2016-08-14 03:49:37 +00:00
|
|
|
cpu_flush_dcache(&bp_kernload, sizeof(bp_kernload));
|
2019-11-02 21:15:56 +00:00
|
|
|
cpu_flush_dcache(&bp_virtaddr, sizeof(bp_virtaddr));
|
Add ePAPR boot support for PowerPC book-E (MPC85xx) hardware
Summary:
u-boot, following the ePAPR specification, puts secondary cores into a
spinloop at boot, rather than leaving them shut off. It then relies on the host
OS to write the correct values to a special spin table, located in coherent
memory (on newer implementations), or noncoherent memory (older
implementations).
This supports both implementations of ePAPR, as well as continuing to support
non-ePAPR booting, by first attempting to use the spintable, and falling back to
expecting non-started CPUs.
Test Plan:
Booted on a P5020 board. Tested before and after the changes.
Before the changes, prints the error "SMP: CPU 1 already out of hold-off state!"
and panics shortly thereafter. After the changes, same boot method lets it
complete boot.
Reviewed by: nwhitehorn
MFC after: 2 weeks
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
Differential Revision: https://reviews.freebsd.org/D7494
2016-08-13 16:16:02 +00:00
|
|
|
|
|
|
|
ap_pcpu = pc;
|
|
|
|
__asm __volatile("msync; isync");
|
|
|
|
|
|
|
|
/* First try the ePAPR way. */
|
|
|
|
if (mpc85xx_smp_start_cpu_epapr(plat, pc) == 0) {
|
|
|
|
epapr_boot = 1;
|
|
|
|
goto spin_wait;
|
|
|
|
}
|
2016-08-03 01:22:11 +00:00
|
|
|
|
2015-12-30 03:43:25 +00:00
|
|
|
reg = ccsr_read4(brr);
|
|
|
|
if ((reg & (1 << cpuid)) != 0) {
|
2013-11-11 16:14:25 +00:00
|
|
|
printf("SMP: CPU %d already out of hold-off state!\n",
|
|
|
|
pc->pc_cpuid);
|
|
|
|
return (ENXIO);
|
|
|
|
}
|
|
|
|
|
2015-12-30 03:43:25 +00:00
|
|
|
/* Flush caches to have our changes hit DRAM. */
|
|
|
|
cpu_flush_dcache(__boot_page, 4096);
|
|
|
|
|
2018-12-10 04:16:40 +00:00
|
|
|
bptr = pmap_kextract((uintptr_t)__boot_page);
|
2015-12-30 03:43:25 +00:00
|
|
|
KASSERT((bptr & 0xfff) == 0,
|
|
|
|
("%s: boot page is not aligned (%#jx)", __func__, (uintmax_t)bptr));
|
2016-08-03 01:22:11 +00:00
|
|
|
if (mpc85xx_is_qoriq()) {
|
|
|
|
/*
|
|
|
|
* Read DDR controller configuration to select proper BPTR target ID.
|
|
|
|
*
|
|
|
|
* On P5020 bit 29 of DDR1_CS0_CONFIG enables DDR controllers
|
|
|
|
* interleaving. If this bit is set, we have to use
|
|
|
|
* OCP85XX_TGTIF_RAM_INTL as BPTR target ID. On other QorIQ DPAA SoCs,
|
|
|
|
* this bit is reserved and always 0.
|
|
|
|
*/
|
|
|
|
|
|
|
|
reg = ccsr_read4(OCP85XX_DDR1_CS0_CONFIG);
|
|
|
|
if (reg & (1 << 29))
|
|
|
|
tgt = OCP85XX_TGTIF_RAM_INTL;
|
|
|
|
else
|
|
|
|
tgt = OCP85XX_TGTIF_RAM1;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Set BSTR to the physical address of the boot page
|
|
|
|
*/
|
|
|
|
ccsr_write4(OCP85XX_BSTRH, bptr >> 32);
|
|
|
|
ccsr_write4(OCP85XX_BSTRL, bptr);
|
|
|
|
ccsr_write4(OCP85XX_BSTAR, OCP85XX_ENA_MASK |
|
|
|
|
(tgt << OCP85XX_TRGT_SHIFT_QORIQ) | (ffsl(PAGE_SIZE) - 2));
|
|
|
|
|
|
|
|
/* Read back OCP85XX_BSTAR to synchronize write */
|
|
|
|
ccsr_read4(OCP85XX_BSTAR);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable and configure time base on new CPU.
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* Set TB clock source to platform clock / 32 */
|
|
|
|
reg = ccsr_read4(CCSR_CTBCKSELR);
|
|
|
|
ccsr_write4(CCSR_CTBCKSELR, reg & ~(1 << pc->pc_cpuid));
|
|
|
|
|
|
|
|
/* Enable TB */
|
|
|
|
reg = ccsr_read4(CCSR_CTBENR);
|
|
|
|
ccsr_write4(CCSR_CTBENR, reg | (1 << pc->pc_cpuid));
|
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* Set BPTR to the physical address of the boot page
|
|
|
|
*/
|
|
|
|
bptr = (bptr >> 12) | 0x80000000u;
|
|
|
|
ccsr_write4(OCP85XX_BPTR, bptr);
|
|
|
|
__asm __volatile("isync; msync");
|
|
|
|
}
|
2013-11-11 16:14:25 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Release AP from hold-off state
|
|
|
|
*/
|
2015-12-30 03:43:25 +00:00
|
|
|
reg = ccsr_read4(brr);
|
|
|
|
ccsr_write4(brr, reg | (1 << cpuid));
|
2013-11-11 16:14:25 +00:00
|
|
|
__asm __volatile("isync; msync");
|
|
|
|
|
Add ePAPR boot support for PowerPC book-E (MPC85xx) hardware
Summary:
u-boot, following the ePAPR specification, puts secondary cores into a
spinloop at boot, rather than leaving them shut off. It then relies on the host
OS to write the correct values to a special spin table, located in coherent
memory (on newer implementations), or noncoherent memory (older
implementations).
This supports both implementations of ePAPR, as well as continuing to support
non-ePAPR booting, by first attempting to use the spintable, and falling back to
expecting non-started CPUs.
Test Plan:
Booted on a P5020 board. Tested before and after the changes.
Before the changes, prints the error "SMP: CPU 1 already out of hold-off state!"
and panics shortly thereafter. After the changes, same boot method lets it
complete boot.
Reviewed by: nwhitehorn
MFC after: 2 weeks
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
Differential Revision: https://reviews.freebsd.org/D7494
2016-08-13 16:16:02 +00:00
|
|
|
spin_wait:
|
2013-11-11 16:14:25 +00:00
|
|
|
timeout = 500;
|
|
|
|
while (!pc->pc_awake && timeout--)
|
|
|
|
DELAY(1000); /* wait 1ms */
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Disable boot page translation so that the 4K page at the default
|
|
|
|
* address (= 0xfffff000) isn't permanently remapped and thus not
|
|
|
|
* usable otherwise.
|
|
|
|
*/
|
Add ePAPR boot support for PowerPC book-E (MPC85xx) hardware
Summary:
u-boot, following the ePAPR specification, puts secondary cores into a
spinloop at boot, rather than leaving them shut off. It then relies on the host
OS to write the correct values to a special spin table, located in coherent
memory (on newer implementations), or noncoherent memory (older
implementations).
This supports both implementations of ePAPR, as well as continuing to support
non-ePAPR booting, by first attempting to use the spintable, and falling back to
expecting non-started CPUs.
Test Plan:
Booted on a P5020 board. Tested before and after the changes.
Before the changes, prints the error "SMP: CPU 1 already out of hold-off state!"
and panics shortly thereafter. After the changes, same boot method lets it
complete boot.
Reviewed by: nwhitehorn
MFC after: 2 weeks
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
Differential Revision: https://reviews.freebsd.org/D7494
2016-08-13 16:16:02 +00:00
|
|
|
if (!epapr_boot) {
|
|
|
|
if (mpc85xx_is_qoriq())
|
|
|
|
ccsr_write4(OCP85XX_BSTAR, 0);
|
|
|
|
else
|
|
|
|
ccsr_write4(OCP85XX_BPTR, 0);
|
|
|
|
__asm __volatile("isync; msync");
|
|
|
|
}
|
2013-11-11 16:14:25 +00:00
|
|
|
|
|
|
|
if (!pc->pc_awake)
|
2016-08-03 01:22:11 +00:00
|
|
|
panic("SMP: CPU %d didn't wake up.\n", pc->pc_cpuid);
|
2013-11-11 16:14:25 +00:00
|
|
|
return ((pc->pc_awake) ? 0 : EBUSY);
|
|
|
|
#else
|
|
|
|
/* No SMP support */
|
|
|
|
return (ENXIO);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
mpc85xx_reset(platform_t plat)
|
|
|
|
{
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Try the dedicated reset register first.
|
|
|
|
* If the SoC doesn't have one, we'll fall
|
|
|
|
* back to using the debug control register.
|
|
|
|
*/
|
|
|
|
ccsr_write4(OCP85XX_RSTCR, 2);
|
|
|
|
|
2019-05-23 03:47:25 +00:00
|
|
|
mtmsr(mfmsr() & ~PSL_DE);
|
|
|
|
|
|
|
|
/* Enable debug interrupts and issue reset. */
|
|
|
|
mtspr(SPR_DBCR0, DBCR0_IDM | DBCR0_RST_SYSTEM);
|
2013-11-11 16:14:25 +00:00
|
|
|
__asm __volatile("isync");
|
|
|
|
|
|
|
|
/* Enable Debug Interrupts in MSR. */
|
|
|
|
mtmsr(mfmsr() | PSL_DE);
|
|
|
|
|
|
|
|
printf("Reset failed...\n");
|
|
|
|
while (1)
|
|
|
|
;
|
|
|
|
}
|
|
|
|
|
2017-11-25 21:59:59 +00:00
|
|
|
static void
|
|
|
|
mpc85xx_smp_timebase_sync(platform_t plat, u_long tb, int ap)
|
|
|
|
{
|
2019-02-27 03:30:49 +00:00
|
|
|
static volatile bool tb_ready;
|
|
|
|
static volatile int cpu_done;
|
|
|
|
|
|
|
|
if (ap) {
|
|
|
|
/* APs. Hold off until we get a stable timebase. */
|
|
|
|
while (!tb_ready)
|
|
|
|
atomic_thread_fence_seq_cst();
|
|
|
|
mttb(tb);
|
|
|
|
atomic_add_int(&cpu_done, 1);
|
|
|
|
while (cpu_done < mp_ncpus)
|
|
|
|
atomic_thread_fence_seq_cst();
|
|
|
|
} else {
|
|
|
|
/* BSP */
|
|
|
|
freeze_timebase(rcpm_dev, true);
|
|
|
|
tb_ready = true;
|
|
|
|
mttb(tb);
|
|
|
|
atomic_add_int(&cpu_done, 1);
|
|
|
|
while (cpu_done < mp_ncpus)
|
|
|
|
atomic_thread_fence_seq_cst();
|
|
|
|
freeze_timebase(rcpm_dev, false);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Fallback freeze. In case no real handler is found in the device tree. */
|
|
|
|
static void
|
|
|
|
dummy_freeze(device_t dev, bool freeze)
|
|
|
|
{
|
|
|
|
/* Nothing to do here, move along. */
|
|
|
|
}
|
|
|
|
|
|
|
|
/* QorIQ Run control/power management timebase management. */
|
|
|
|
|
|
|
|
#define RCPM_CTBENR 0x00000084
|
|
|
|
struct mpc85xx_rcpm_softc {
|
|
|
|
struct resource *sc_mem;
|
|
|
|
};
|
|
|
|
|
|
|
|
static void
|
|
|
|
mpc85xx_rcpm_freeze_timebase(device_t dev, bool freeze)
|
|
|
|
{
|
|
|
|
struct mpc85xx_rcpm_softc *sc;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
2020-09-01 21:20:08 +00:00
|
|
|
|
2019-02-27 03:30:49 +00:00
|
|
|
if (freeze)
|
|
|
|
bus_write_4(sc->sc_mem, RCPM_CTBENR, 0);
|
|
|
|
else
|
|
|
|
bus_write_4(sc->sc_mem, RCPM_CTBENR, (1 << maxcpu) - 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
mpc85xx_rcpm_probe(device_t dev)
|
|
|
|
{
|
|
|
|
if (!ofw_bus_is_compatible(dev, "fsl,qoriq-rcpm-1.0"))
|
|
|
|
return (ENXIO);
|
|
|
|
|
|
|
|
device_set_desc(dev, "QorIQ Run control and power management");
|
|
|
|
return (BUS_PROBE_GENERIC);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
mpc85xx_rcpm_attach(device_t dev)
|
|
|
|
{
|
|
|
|
struct mpc85xx_rcpm_softc *sc;
|
|
|
|
int rid;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
freeze_timebase = mpc85xx_rcpm_freeze_timebase;
|
|
|
|
rcpm_dev = dev;
|
|
|
|
|
|
|
|
rid = 0;
|
|
|
|
sc->sc_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
|
|
|
|
RF_ACTIVE | RF_SHAREABLE);
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static device_method_t mpc85xx_rcpm_methods[] = {
|
|
|
|
DEVMETHOD(device_probe, mpc85xx_rcpm_probe),
|
|
|
|
DEVMETHOD(device_attach, mpc85xx_rcpm_attach),
|
|
|
|
DEVMETHOD_END
|
|
|
|
};
|
|
|
|
|
|
|
|
static driver_t mpc85xx_rcpm_driver = {
|
|
|
|
"rcpm",
|
|
|
|
mpc85xx_rcpm_methods,
|
|
|
|
sizeof(struct mpc85xx_rcpm_softc)
|
|
|
|
};
|
|
|
|
|
2022-05-10 17:21:38 +00:00
|
|
|
EARLY_DRIVER_MODULE(mpc85xx_rcpm, simplebus, mpc85xx_rcpm_driver, 0, 0,
|
|
|
|
BUS_PASS_BUS);
|
2019-02-27 03:30:49 +00:00
|
|
|
|
|
|
|
/* "Global utilities" power management/Timebase management. */
|
|
|
|
|
|
|
|
#define GUTS_DEVDISR 0x00000070
|
|
|
|
#define DEVDISR_TB0 0x00004000
|
|
|
|
#define DEVDISR_TB1 0x00001000
|
|
|
|
|
|
|
|
struct mpc85xx_guts_softc {
|
|
|
|
struct resource *sc_mem;
|
|
|
|
};
|
|
|
|
|
|
|
|
static void
|
|
|
|
mpc85xx_guts_freeze_timebase(device_t dev, bool freeze)
|
|
|
|
{
|
|
|
|
struct mpc85xx_guts_softc *sc;
|
|
|
|
uint32_t devdisr;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
2020-09-01 21:20:08 +00:00
|
|
|
|
2019-02-27 03:30:49 +00:00
|
|
|
devdisr = bus_read_4(sc->sc_mem, GUTS_DEVDISR);
|
|
|
|
if (freeze)
|
|
|
|
bus_write_4(sc->sc_mem, GUTS_DEVDISR,
|
|
|
|
devdisr | (DEVDISR_TB0 | DEVDISR_TB1));
|
|
|
|
else
|
|
|
|
bus_write_4(sc->sc_mem, GUTS_DEVDISR,
|
|
|
|
devdisr & ~(DEVDISR_TB0 | DEVDISR_TB1));
|
|
|
|
}
|
2017-11-25 21:59:59 +00:00
|
|
|
|
2019-02-27 03:30:49 +00:00
|
|
|
static int
|
|
|
|
mpc85xx_guts_probe(device_t dev)
|
|
|
|
{
|
|
|
|
if (!ofw_bus_is_compatible(dev, "fsl,mpc8572-guts") &&
|
|
|
|
!ofw_bus_is_compatible(dev, "fsl,p1020-guts") &&
|
|
|
|
!ofw_bus_is_compatible(dev, "fsl,p1021-guts") &&
|
|
|
|
!ofw_bus_is_compatible(dev, "fsl,p1022-guts") &&
|
|
|
|
!ofw_bus_is_compatible(dev, "fsl,p1023-guts") &&
|
|
|
|
!ofw_bus_is_compatible(dev, "fsl,p2020-guts"))
|
|
|
|
return (ENXIO);
|
|
|
|
|
|
|
|
device_set_desc(dev, "MPC85xx Global Utilities");
|
|
|
|
return (BUS_PROBE_GENERIC);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
mpc85xx_guts_attach(device_t dev)
|
|
|
|
{
|
|
|
|
struct mpc85xx_rcpm_softc *sc;
|
|
|
|
int rid;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
freeze_timebase = mpc85xx_guts_freeze_timebase;
|
|
|
|
rcpm_dev = dev;
|
|
|
|
|
|
|
|
rid = 0;
|
|
|
|
sc->sc_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
|
|
|
|
RF_ACTIVE | RF_SHAREABLE);
|
|
|
|
|
|
|
|
return (0);
|
2017-11-25 21:59:59 +00:00
|
|
|
}
|
|
|
|
|
2019-02-27 03:30:49 +00:00
|
|
|
static device_method_t mpc85xx_guts_methods[] = {
|
|
|
|
DEVMETHOD(device_probe, mpc85xx_guts_probe),
|
|
|
|
DEVMETHOD(device_attach, mpc85xx_guts_attach),
|
|
|
|
DEVMETHOD_END
|
|
|
|
};
|
|
|
|
|
|
|
|
static driver_t mpc85xx_guts_driver = {
|
|
|
|
"guts",
|
|
|
|
mpc85xx_guts_methods,
|
|
|
|
sizeof(struct mpc85xx_guts_softc)
|
|
|
|
};
|
|
|
|
|
2022-05-10 17:21:38 +00:00
|
|
|
EARLY_DRIVER_MODULE(mpc85xx_guts, simplebus, mpc85xx_guts_driver, 0, 0,
|
|
|
|
BUS_PASS_BUS);
|