2017-10-30 03:41:04 +00:00
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/*
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* Copyright 2008-2012 Freescale Semiconductor Inc.
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Add support for the Freescale dTSEC DPAA-based ethernet controller.
Freescale's QorIQ line includes a new ethernet controller, based on their
Datapath Acceleration Architecture (DPAA). This uses a combination of a Frame
manager, Buffer manager, and Queue manager to improve performance across all
interfaces by being able to pass data directly between hardware acceleration
interfaces.
As part of this import, Freescale's Netcomm Software (ncsw) driver is imported.
This was an attempt by Freescale to create an OS-agnostic sub-driver for
managing the hardware, using shims to interface to the OS-specific APIs. This
work was abandoned, and Freescale's primary work is in the Linux driver (dual
BSD/GPL license). Hence, this was imported directly to sys/contrib, rather than
going through the vendor area. Going forward, FreeBSD-specific changes may be
made to the ncsw code, diverging from the upstream in potentially incompatible
ways. An alternative could be to import the Linux driver itself, using the
linuxKPI layer, as that would maintain parity with the vendor-maintained driver.
However, the Linux driver has not been evaluated for reliability yet, and may
have issues with the import, whereas the ncsw-based driver in this commit was
completed by Semihalf 4 years ago, and is very stable.
Other SoC modules based on DPAA, which could be added in the future:
* Security and Encryption engine (SEC4.x, SEC5.x)
* RAID engine
Additional work to be done:
* Implement polling mode
* Test vlan support
* Add support for the Pattern Matching Engine, which can do regular expression
matching on packets.
This driver has been tested on the P5020 QorIQ SoC. Others listed in the
dtsec(4) manual page are expected to work as the same DPAA engine is included in
all.
Obtained from: Semihalf
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
2016-02-29 03:38:00 +00:00
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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2017-10-30 03:41:04 +00:00
|
|
|
|
Add support for the Freescale dTSEC DPAA-based ethernet controller.
Freescale's QorIQ line includes a new ethernet controller, based on their
Datapath Acceleration Architecture (DPAA). This uses a combination of a Frame
manager, Buffer manager, and Queue manager to improve performance across all
interfaces by being able to pass data directly between hardware acceleration
interfaces.
As part of this import, Freescale's Netcomm Software (ncsw) driver is imported.
This was an attempt by Freescale to create an OS-agnostic sub-driver for
managing the hardware, using shims to interface to the OS-specific APIs. This
work was abandoned, and Freescale's primary work is in the Linux driver (dual
BSD/GPL license). Hence, this was imported directly to sys/contrib, rather than
going through the vendor area. Going forward, FreeBSD-specific changes may be
made to the ncsw code, diverging from the upstream in potentially incompatible
ways. An alternative could be to import the Linux driver itself, using the
linuxKPI layer, as that would maintain parity with the vendor-maintained driver.
However, the Linux driver has not been evaluated for reliability yet, and may
have issues with the import, whereas the ncsw-based driver in this commit was
completed by Semihalf 4 years ago, and is very stable.
Other SoC modules based on DPAA, which could be added in the future:
* Security and Encryption engine (SEC4.x, SEC5.x)
* RAID engine
Additional work to be done:
* Implement polling mode
* Test vlan support
* Add support for the Pattern Matching Engine, which can do regular expression
matching on packets.
This driver has been tested on the P5020 QorIQ SoC. Others listed in the
dtsec(4) manual page are expected to work as the same DPAA engine is included in
all.
Obtained from: Semihalf
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
2016-02-29 03:38:00 +00:00
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#include "std_ext.h"
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#include "xx_ext.h"
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#include "memcpy_ext.h"
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2017-10-30 03:41:04 +00:00
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void * MemCpy8(void* pDst, void* pSrc, uint32_t size)
|
Add support for the Freescale dTSEC DPAA-based ethernet controller.
Freescale's QorIQ line includes a new ethernet controller, based on their
Datapath Acceleration Architecture (DPAA). This uses a combination of a Frame
manager, Buffer manager, and Queue manager to improve performance across all
interfaces by being able to pass data directly between hardware acceleration
interfaces.
As part of this import, Freescale's Netcomm Software (ncsw) driver is imported.
This was an attempt by Freescale to create an OS-agnostic sub-driver for
managing the hardware, using shims to interface to the OS-specific APIs. This
work was abandoned, and Freescale's primary work is in the Linux driver (dual
BSD/GPL license). Hence, this was imported directly to sys/contrib, rather than
going through the vendor area. Going forward, FreeBSD-specific changes may be
made to the ncsw code, diverging from the upstream in potentially incompatible
ways. An alternative could be to import the Linux driver itself, using the
linuxKPI layer, as that would maintain parity with the vendor-maintained driver.
However, the Linux driver has not been evaluated for reliability yet, and may
have issues with the import, whereas the ncsw-based driver in this commit was
completed by Semihalf 4 years ago, and is very stable.
Other SoC modules based on DPAA, which could be added in the future:
* Security and Encryption engine (SEC4.x, SEC5.x)
* RAID engine
Additional work to be done:
* Implement polling mode
* Test vlan support
* Add support for the Pattern Matching Engine, which can do regular expression
matching on packets.
This driver has been tested on the P5020 QorIQ SoC. Others listed in the
dtsec(4) manual page are expected to work as the same DPAA engine is included in
all.
Obtained from: Semihalf
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
2016-02-29 03:38:00 +00:00
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{
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2017-10-31 02:53:50 +00:00
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uint32_t i;
|
Add support for the Freescale dTSEC DPAA-based ethernet controller.
Freescale's QorIQ line includes a new ethernet controller, based on their
Datapath Acceleration Architecture (DPAA). This uses a combination of a Frame
manager, Buffer manager, and Queue manager to improve performance across all
interfaces by being able to pass data directly between hardware acceleration
interfaces.
As part of this import, Freescale's Netcomm Software (ncsw) driver is imported.
This was an attempt by Freescale to create an OS-agnostic sub-driver for
managing the hardware, using shims to interface to the OS-specific APIs. This
work was abandoned, and Freescale's primary work is in the Linux driver (dual
BSD/GPL license). Hence, this was imported directly to sys/contrib, rather than
going through the vendor area. Going forward, FreeBSD-specific changes may be
made to the ncsw code, diverging from the upstream in potentially incompatible
ways. An alternative could be to import the Linux driver itself, using the
linuxKPI layer, as that would maintain parity with the vendor-maintained driver.
However, the Linux driver has not been evaluated for reliability yet, and may
have issues with the import, whereas the ncsw-based driver in this commit was
completed by Semihalf 4 years ago, and is very stable.
Other SoC modules based on DPAA, which could be added in the future:
* Security and Encryption engine (SEC4.x, SEC5.x)
* RAID engine
Additional work to be done:
* Implement polling mode
* Test vlan support
* Add support for the Pattern Matching Engine, which can do regular expression
matching on packets.
This driver has been tested on the P5020 QorIQ SoC. Others listed in the
dtsec(4) manual page are expected to work as the same DPAA engine is included in
all.
Obtained from: Semihalf
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
2016-02-29 03:38:00 +00:00
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2017-10-30 03:41:04 +00:00
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for(i = 0; i < size; ++i)
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*(((uint8_t*)(pDst)) + i) = *(((uint8_t*)(pSrc)) + i);
|
Add support for the Freescale dTSEC DPAA-based ethernet controller.
Freescale's QorIQ line includes a new ethernet controller, based on their
Datapath Acceleration Architecture (DPAA). This uses a combination of a Frame
manager, Buffer manager, and Queue manager to improve performance across all
interfaces by being able to pass data directly between hardware acceleration
interfaces.
As part of this import, Freescale's Netcomm Software (ncsw) driver is imported.
This was an attempt by Freescale to create an OS-agnostic sub-driver for
managing the hardware, using shims to interface to the OS-specific APIs. This
work was abandoned, and Freescale's primary work is in the Linux driver (dual
BSD/GPL license). Hence, this was imported directly to sys/contrib, rather than
going through the vendor area. Going forward, FreeBSD-specific changes may be
made to the ncsw code, diverging from the upstream in potentially incompatible
ways. An alternative could be to import the Linux driver itself, using the
linuxKPI layer, as that would maintain parity with the vendor-maintained driver.
However, the Linux driver has not been evaluated for reliability yet, and may
have issues with the import, whereas the ncsw-based driver in this commit was
completed by Semihalf 4 years ago, and is very stable.
Other SoC modules based on DPAA, which could be added in the future:
* Security and Encryption engine (SEC4.x, SEC5.x)
* RAID engine
Additional work to be done:
* Implement polling mode
* Test vlan support
* Add support for the Pattern Matching Engine, which can do regular expression
matching on packets.
This driver has been tested on the P5020 QorIQ SoC. Others listed in the
dtsec(4) manual page are expected to work as the same DPAA engine is included in
all.
Obtained from: Semihalf
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
2016-02-29 03:38:00 +00:00
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2017-10-30 03:41:04 +00:00
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return pDst;
|
Add support for the Freescale dTSEC DPAA-based ethernet controller.
Freescale's QorIQ line includes a new ethernet controller, based on their
Datapath Acceleration Architecture (DPAA). This uses a combination of a Frame
manager, Buffer manager, and Queue manager to improve performance across all
interfaces by being able to pass data directly between hardware acceleration
interfaces.
As part of this import, Freescale's Netcomm Software (ncsw) driver is imported.
This was an attempt by Freescale to create an OS-agnostic sub-driver for
managing the hardware, using shims to interface to the OS-specific APIs. This
work was abandoned, and Freescale's primary work is in the Linux driver (dual
BSD/GPL license). Hence, this was imported directly to sys/contrib, rather than
going through the vendor area. Going forward, FreeBSD-specific changes may be
made to the ncsw code, diverging from the upstream in potentially incompatible
ways. An alternative could be to import the Linux driver itself, using the
linuxKPI layer, as that would maintain parity with the vendor-maintained driver.
However, the Linux driver has not been evaluated for reliability yet, and may
have issues with the import, whereas the ncsw-based driver in this commit was
completed by Semihalf 4 years ago, and is very stable.
Other SoC modules based on DPAA, which could be added in the future:
* Security and Encryption engine (SEC4.x, SEC5.x)
* RAID engine
Additional work to be done:
* Implement polling mode
* Test vlan support
* Add support for the Pattern Matching Engine, which can do regular expression
matching on packets.
This driver has been tested on the P5020 QorIQ SoC. Others listed in the
dtsec(4) manual page are expected to work as the same DPAA engine is included in
all.
Obtained from: Semihalf
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
2016-02-29 03:38:00 +00:00
|
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}
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2017-10-30 03:41:04 +00:00
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void * MemSet8(void* pDst, int c, uint32_t size)
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{
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2017-10-31 02:53:50 +00:00
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uint32_t i;
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2017-10-30 03:41:04 +00:00
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for(i = 0; i < size; ++i)
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*(((uint8_t*)(pDst)) + i) = (uint8_t)(c);
|
Add support for the Freescale dTSEC DPAA-based ethernet controller.
Freescale's QorIQ line includes a new ethernet controller, based on their
Datapath Acceleration Architecture (DPAA). This uses a combination of a Frame
manager, Buffer manager, and Queue manager to improve performance across all
interfaces by being able to pass data directly between hardware acceleration
interfaces.
As part of this import, Freescale's Netcomm Software (ncsw) driver is imported.
This was an attempt by Freescale to create an OS-agnostic sub-driver for
managing the hardware, using shims to interface to the OS-specific APIs. This
work was abandoned, and Freescale's primary work is in the Linux driver (dual
BSD/GPL license). Hence, this was imported directly to sys/contrib, rather than
going through the vendor area. Going forward, FreeBSD-specific changes may be
made to the ncsw code, diverging from the upstream in potentially incompatible
ways. An alternative could be to import the Linux driver itself, using the
linuxKPI layer, as that would maintain parity with the vendor-maintained driver.
However, the Linux driver has not been evaluated for reliability yet, and may
have issues with the import, whereas the ncsw-based driver in this commit was
completed by Semihalf 4 years ago, and is very stable.
Other SoC modules based on DPAA, which could be added in the future:
* Security and Encryption engine (SEC4.x, SEC5.x)
* RAID engine
Additional work to be done:
* Implement polling mode
* Test vlan support
* Add support for the Pattern Matching Engine, which can do regular expression
matching on packets.
This driver has been tested on the P5020 QorIQ SoC. Others listed in the
dtsec(4) manual page are expected to work as the same DPAA engine is included in
all.
Obtained from: Semihalf
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
2016-02-29 03:38:00 +00:00
|
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2017-10-30 03:41:04 +00:00
|
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return pDst;
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|
}
|
Add support for the Freescale dTSEC DPAA-based ethernet controller.
Freescale's QorIQ line includes a new ethernet controller, based on their
Datapath Acceleration Architecture (DPAA). This uses a combination of a Frame
manager, Buffer manager, and Queue manager to improve performance across all
interfaces by being able to pass data directly between hardware acceleration
interfaces.
As part of this import, Freescale's Netcomm Software (ncsw) driver is imported.
This was an attempt by Freescale to create an OS-agnostic sub-driver for
managing the hardware, using shims to interface to the OS-specific APIs. This
work was abandoned, and Freescale's primary work is in the Linux driver (dual
BSD/GPL license). Hence, this was imported directly to sys/contrib, rather than
going through the vendor area. Going forward, FreeBSD-specific changes may be
made to the ncsw code, diverging from the upstream in potentially incompatible
ways. An alternative could be to import the Linux driver itself, using the
linuxKPI layer, as that would maintain parity with the vendor-maintained driver.
However, the Linux driver has not been evaluated for reliability yet, and may
have issues with the import, whereas the ncsw-based driver in this commit was
completed by Semihalf 4 years ago, and is very stable.
Other SoC modules based on DPAA, which could be added in the future:
* Security and Encryption engine (SEC4.x, SEC5.x)
* RAID engine
Additional work to be done:
* Implement polling mode
* Test vlan support
* Add support for the Pattern Matching Engine, which can do regular expression
matching on packets.
This driver has been tested on the P5020 QorIQ SoC. Others listed in the
dtsec(4) manual page are expected to work as the same DPAA engine is included in
all.
Obtained from: Semihalf
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
2016-02-29 03:38:00 +00:00
|
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void * MemCpy32(void* pDst,void* pSrc, uint32_t size)
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{
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uint32_t leftAlign;
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uint32_t rightAlign;
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uint32_t lastWord;
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uint32_t currWord;
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uint32_t *p_Src32;
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uint32_t *p_Dst32;
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uint8_t *p_Src8;
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uint8_t *p_Dst8;
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p_Src8 = (uint8_t*)(pSrc);
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p_Dst8 = (uint8_t*)(pDst);
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/* first copy byte by byte till the source first alignment
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* this step is necessary to ensure we do not even try to access
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* data which is before the source buffer, hence it is not ours.
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*/
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while((PTR_TO_UINT(p_Src8) & 3) && size) /* (pSrc mod 4) > 0 and size > 0 */
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{
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*p_Dst8++ = *p_Src8++;
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size--;
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}
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/* align destination (possibly disaligning source)*/
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while((PTR_TO_UINT(p_Dst8) & 3) && size) /* (pDst mod 4) > 0 and size > 0 */
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{
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*p_Dst8++ = *p_Src8++;
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size--;
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}
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/* dest is aligned and source is not necessarily aligned */
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leftAlign = (uint32_t)((PTR_TO_UINT(p_Src8) & 3) << 3); /* leftAlign = (pSrc mod 4)*8 */
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rightAlign = 32 - leftAlign;
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if (leftAlign == 0)
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{
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/* source is also aligned */
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p_Src32 = (uint32_t*)(p_Src8);
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p_Dst32 = (uint32_t*)(p_Dst8);
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while (size >> 2) /* size >= 4 */
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{
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*p_Dst32++ = *p_Src32++;
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size -= 4;
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}
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p_Src8 = (uint8_t*)(p_Src32);
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p_Dst8 = (uint8_t*)(p_Dst32);
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}
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else
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{
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/* source is not aligned (destination is aligned)*/
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p_Src32 = (uint32_t*)(p_Src8 - (leftAlign >> 3));
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p_Dst32 = (uint32_t*)(p_Dst8);
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lastWord = *p_Src32++;
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while(size >> 3) /* size >= 8 */
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{
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currWord = *p_Src32;
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*p_Dst32 = (lastWord << leftAlign) | (currWord >> rightAlign);
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lastWord = currWord;
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p_Src32++;
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p_Dst32++;
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size -= 4;
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}
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p_Dst8 = (uint8_t*)(p_Dst32);
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p_Src8 = (uint8_t*)(p_Src32) - 4 + (leftAlign >> 3);
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}
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/* complete the left overs */
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while (size--)
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*p_Dst8++ = *p_Src8++;
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return pDst;
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}
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void * IO2IOCpy32(void* pDst,void* pSrc, uint32_t size)
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{
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uint32_t leftAlign;
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uint32_t rightAlign;
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uint32_t lastWord;
|
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uint32_t currWord;
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uint32_t *p_Src32;
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uint32_t *p_Dst32;
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uint8_t *p_Src8;
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uint8_t *p_Dst8;
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p_Src8 = (uint8_t*)(pSrc);
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p_Dst8 = (uint8_t*)(pDst);
|
|
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/* first copy byte by byte till the source first alignment
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|
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* this step is necessary to ensure we do not even try to access
|
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* data which is before the source buffer, hence it is not ours.
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*/
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while((PTR_TO_UINT(p_Src8) & 3) && size) /* (pSrc mod 4) > 0 and size > 0 */
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{
|
2017-10-30 03:41:04 +00:00
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|
WRITE_UINT8(*p_Dst8, GET_UINT8(*p_Src8));
|
Add support for the Freescale dTSEC DPAA-based ethernet controller.
Freescale's QorIQ line includes a new ethernet controller, based on their
Datapath Acceleration Architecture (DPAA). This uses a combination of a Frame
manager, Buffer manager, and Queue manager to improve performance across all
interfaces by being able to pass data directly between hardware acceleration
interfaces.
As part of this import, Freescale's Netcomm Software (ncsw) driver is imported.
This was an attempt by Freescale to create an OS-agnostic sub-driver for
managing the hardware, using shims to interface to the OS-specific APIs. This
work was abandoned, and Freescale's primary work is in the Linux driver (dual
BSD/GPL license). Hence, this was imported directly to sys/contrib, rather than
going through the vendor area. Going forward, FreeBSD-specific changes may be
made to the ncsw code, diverging from the upstream in potentially incompatible
ways. An alternative could be to import the Linux driver itself, using the
linuxKPI layer, as that would maintain parity with the vendor-maintained driver.
However, the Linux driver has not been evaluated for reliability yet, and may
have issues with the import, whereas the ncsw-based driver in this commit was
completed by Semihalf 4 years ago, and is very stable.
Other SoC modules based on DPAA, which could be added in the future:
* Security and Encryption engine (SEC4.x, SEC5.x)
* RAID engine
Additional work to be done:
* Implement polling mode
* Test vlan support
* Add support for the Pattern Matching Engine, which can do regular expression
matching on packets.
This driver has been tested on the P5020 QorIQ SoC. Others listed in the
dtsec(4) manual page are expected to work as the same DPAA engine is included in
all.
Obtained from: Semihalf
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
2016-02-29 03:38:00 +00:00
|
|
|
p_Dst8++;p_Src8++;
|
|
|
|
size--;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* align destination (possibly disaligning source)*/
|
|
|
|
while((PTR_TO_UINT(p_Dst8) & 3) && size) /* (pDst mod 4) > 0 and size > 0 */
|
|
|
|
{
|
2017-10-30 03:41:04 +00:00
|
|
|
WRITE_UINT8(*p_Dst8, GET_UINT8(*p_Src8));
|
Add support for the Freescale dTSEC DPAA-based ethernet controller.
Freescale's QorIQ line includes a new ethernet controller, based on their
Datapath Acceleration Architecture (DPAA). This uses a combination of a Frame
manager, Buffer manager, and Queue manager to improve performance across all
interfaces by being able to pass data directly between hardware acceleration
interfaces.
As part of this import, Freescale's Netcomm Software (ncsw) driver is imported.
This was an attempt by Freescale to create an OS-agnostic sub-driver for
managing the hardware, using shims to interface to the OS-specific APIs. This
work was abandoned, and Freescale's primary work is in the Linux driver (dual
BSD/GPL license). Hence, this was imported directly to sys/contrib, rather than
going through the vendor area. Going forward, FreeBSD-specific changes may be
made to the ncsw code, diverging from the upstream in potentially incompatible
ways. An alternative could be to import the Linux driver itself, using the
linuxKPI layer, as that would maintain parity with the vendor-maintained driver.
However, the Linux driver has not been evaluated for reliability yet, and may
have issues with the import, whereas the ncsw-based driver in this commit was
completed by Semihalf 4 years ago, and is very stable.
Other SoC modules based on DPAA, which could be added in the future:
* Security and Encryption engine (SEC4.x, SEC5.x)
* RAID engine
Additional work to be done:
* Implement polling mode
* Test vlan support
* Add support for the Pattern Matching Engine, which can do regular expression
matching on packets.
This driver has been tested on the P5020 QorIQ SoC. Others listed in the
dtsec(4) manual page are expected to work as the same DPAA engine is included in
all.
Obtained from: Semihalf
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
2016-02-29 03:38:00 +00:00
|
|
|
p_Dst8++;p_Src8++;
|
|
|
|
size--;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* dest is aligned and source is not necessarily aligned */
|
|
|
|
leftAlign = (uint32_t)((PTR_TO_UINT(p_Src8) & 3) << 3); /* leftAlign = (pSrc mod 4)*8 */
|
|
|
|
rightAlign = 32 - leftAlign;
|
|
|
|
|
|
|
|
if (leftAlign == 0)
|
|
|
|
{
|
|
|
|
/* source is also aligned */
|
|
|
|
p_Src32 = (uint32_t*)(p_Src8);
|
|
|
|
p_Dst32 = (uint32_t*)(p_Dst8);
|
|
|
|
while (size >> 2) /* size >= 4 */
|
|
|
|
{
|
|
|
|
WRITE_UINT32(*p_Dst32, GET_UINT32(*p_Src32));
|
|
|
|
p_Dst32++;p_Src32++;
|
|
|
|
size -= 4;
|
|
|
|
}
|
|
|
|
p_Src8 = (uint8_t*)(p_Src32);
|
|
|
|
p_Dst8 = (uint8_t*)(p_Dst32);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* source is not aligned (destination is aligned)*/
|
|
|
|
p_Src32 = (uint32_t*)(p_Src8 - (leftAlign >> 3));
|
|
|
|
p_Dst32 = (uint32_t*)(p_Dst8);
|
|
|
|
lastWord = GET_UINT32(*p_Src32);
|
|
|
|
p_Src32++;
|
|
|
|
while(size >> 3) /* size >= 8 */
|
|
|
|
{
|
|
|
|
currWord = GET_UINT32(*p_Src32);
|
|
|
|
WRITE_UINT32(*p_Dst32, (lastWord << leftAlign) | (currWord >> rightAlign));
|
|
|
|
lastWord = currWord;
|
|
|
|
p_Src32++;p_Dst32++;
|
|
|
|
size -= 4;
|
|
|
|
}
|
|
|
|
p_Dst8 = (uint8_t*)(p_Dst32);
|
|
|
|
p_Src8 = (uint8_t*)(p_Src32) - 4 + (leftAlign >> 3);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* complete the left overs */
|
|
|
|
while (size--)
|
|
|
|
{
|
2017-10-30 03:41:04 +00:00
|
|
|
WRITE_UINT8(*p_Dst8, GET_UINT8(*p_Src8));
|
Add support for the Freescale dTSEC DPAA-based ethernet controller.
Freescale's QorIQ line includes a new ethernet controller, based on their
Datapath Acceleration Architecture (DPAA). This uses a combination of a Frame
manager, Buffer manager, and Queue manager to improve performance across all
interfaces by being able to pass data directly between hardware acceleration
interfaces.
As part of this import, Freescale's Netcomm Software (ncsw) driver is imported.
This was an attempt by Freescale to create an OS-agnostic sub-driver for
managing the hardware, using shims to interface to the OS-specific APIs. This
work was abandoned, and Freescale's primary work is in the Linux driver (dual
BSD/GPL license). Hence, this was imported directly to sys/contrib, rather than
going through the vendor area. Going forward, FreeBSD-specific changes may be
made to the ncsw code, diverging from the upstream in potentially incompatible
ways. An alternative could be to import the Linux driver itself, using the
linuxKPI layer, as that would maintain parity with the vendor-maintained driver.
However, the Linux driver has not been evaluated for reliability yet, and may
have issues with the import, whereas the ncsw-based driver in this commit was
completed by Semihalf 4 years ago, and is very stable.
Other SoC modules based on DPAA, which could be added in the future:
* Security and Encryption engine (SEC4.x, SEC5.x)
* RAID engine
Additional work to be done:
* Implement polling mode
* Test vlan support
* Add support for the Pattern Matching Engine, which can do regular expression
matching on packets.
This driver has been tested on the P5020 QorIQ SoC. Others listed in the
dtsec(4) manual page are expected to work as the same DPAA engine is included in
all.
Obtained from: Semihalf
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
2016-02-29 03:38:00 +00:00
|
|
|
p_Dst8++;p_Src8++;
|
|
|
|
}
|
|
|
|
|
|
|
|
return pDst;
|
|
|
|
}
|
|
|
|
|
|
|
|
void * Mem2IOCpy32(void* pDst,void* pSrc, uint32_t size)
|
|
|
|
{
|
|
|
|
uint32_t leftAlign;
|
|
|
|
uint32_t rightAlign;
|
|
|
|
uint32_t lastWord;
|
|
|
|
uint32_t currWord;
|
|
|
|
uint32_t *p_Src32;
|
|
|
|
uint32_t *p_Dst32;
|
|
|
|
uint8_t *p_Src8;
|
|
|
|
uint8_t *p_Dst8;
|
|
|
|
|
|
|
|
p_Src8 = (uint8_t*)(pSrc);
|
|
|
|
p_Dst8 = (uint8_t*)(pDst);
|
|
|
|
/* first copy byte by byte till the source first alignment
|
|
|
|
* this step is necessary to ensure we do not even try to access
|
|
|
|
* data which is before the source buffer, hence it is not ours.
|
|
|
|
*/
|
|
|
|
while((PTR_TO_UINT(p_Src8) & 3) && size) /* (pSrc mod 4) > 0 and size > 0 */
|
|
|
|
{
|
2017-10-30 03:41:04 +00:00
|
|
|
WRITE_UINT8(*p_Dst8, *p_Src8);
|
Add support for the Freescale dTSEC DPAA-based ethernet controller.
Freescale's QorIQ line includes a new ethernet controller, based on their
Datapath Acceleration Architecture (DPAA). This uses a combination of a Frame
manager, Buffer manager, and Queue manager to improve performance across all
interfaces by being able to pass data directly between hardware acceleration
interfaces.
As part of this import, Freescale's Netcomm Software (ncsw) driver is imported.
This was an attempt by Freescale to create an OS-agnostic sub-driver for
managing the hardware, using shims to interface to the OS-specific APIs. This
work was abandoned, and Freescale's primary work is in the Linux driver (dual
BSD/GPL license). Hence, this was imported directly to sys/contrib, rather than
going through the vendor area. Going forward, FreeBSD-specific changes may be
made to the ncsw code, diverging from the upstream in potentially incompatible
ways. An alternative could be to import the Linux driver itself, using the
linuxKPI layer, as that would maintain parity with the vendor-maintained driver.
However, the Linux driver has not been evaluated for reliability yet, and may
have issues with the import, whereas the ncsw-based driver in this commit was
completed by Semihalf 4 years ago, and is very stable.
Other SoC modules based on DPAA, which could be added in the future:
* Security and Encryption engine (SEC4.x, SEC5.x)
* RAID engine
Additional work to be done:
* Implement polling mode
* Test vlan support
* Add support for the Pattern Matching Engine, which can do regular expression
matching on packets.
This driver has been tested on the P5020 QorIQ SoC. Others listed in the
dtsec(4) manual page are expected to work as the same DPAA engine is included in
all.
Obtained from: Semihalf
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
2016-02-29 03:38:00 +00:00
|
|
|
p_Dst8++;p_Src8++;
|
|
|
|
size--;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* align destination (possibly disaligning source)*/
|
|
|
|
while((PTR_TO_UINT(p_Dst8) & 3) && size) /* (pDst mod 4) > 0 and size > 0 */
|
|
|
|
{
|
2017-10-30 03:41:04 +00:00
|
|
|
WRITE_UINT8(*p_Dst8, *p_Src8);
|
Add support for the Freescale dTSEC DPAA-based ethernet controller.
Freescale's QorIQ line includes a new ethernet controller, based on their
Datapath Acceleration Architecture (DPAA). This uses a combination of a Frame
manager, Buffer manager, and Queue manager to improve performance across all
interfaces by being able to pass data directly between hardware acceleration
interfaces.
As part of this import, Freescale's Netcomm Software (ncsw) driver is imported.
This was an attempt by Freescale to create an OS-agnostic sub-driver for
managing the hardware, using shims to interface to the OS-specific APIs. This
work was abandoned, and Freescale's primary work is in the Linux driver (dual
BSD/GPL license). Hence, this was imported directly to sys/contrib, rather than
going through the vendor area. Going forward, FreeBSD-specific changes may be
made to the ncsw code, diverging from the upstream in potentially incompatible
ways. An alternative could be to import the Linux driver itself, using the
linuxKPI layer, as that would maintain parity with the vendor-maintained driver.
However, the Linux driver has not been evaluated for reliability yet, and may
have issues with the import, whereas the ncsw-based driver in this commit was
completed by Semihalf 4 years ago, and is very stable.
Other SoC modules based on DPAA, which could be added in the future:
* Security and Encryption engine (SEC4.x, SEC5.x)
* RAID engine
Additional work to be done:
* Implement polling mode
* Test vlan support
* Add support for the Pattern Matching Engine, which can do regular expression
matching on packets.
This driver has been tested on the P5020 QorIQ SoC. Others listed in the
dtsec(4) manual page are expected to work as the same DPAA engine is included in
all.
Obtained from: Semihalf
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
2016-02-29 03:38:00 +00:00
|
|
|
p_Dst8++;p_Src8++;
|
|
|
|
size--;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* dest is aligned and source is not necessarily aligned */
|
|
|
|
leftAlign = (uint32_t)((PTR_TO_UINT(p_Src8) & 3) << 3); /* leftAlign = (pSrc mod 4)*8 */
|
|
|
|
rightAlign = 32 - leftAlign;
|
|
|
|
|
|
|
|
if (leftAlign == 0)
|
|
|
|
{
|
|
|
|
/* source is also aligned */
|
|
|
|
p_Src32 = (uint32_t*)(p_Src8);
|
|
|
|
p_Dst32 = (uint32_t*)(p_Dst8);
|
|
|
|
while (size >> 2) /* size >= 4 */
|
|
|
|
{
|
|
|
|
WRITE_UINT32(*p_Dst32, *p_Src32);
|
|
|
|
p_Dst32++;p_Src32++;
|
|
|
|
size -= 4;
|
|
|
|
}
|
|
|
|
p_Src8 = (uint8_t*)(p_Src32);
|
|
|
|
p_Dst8 = (uint8_t*)(p_Dst32);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* source is not aligned (destination is aligned)*/
|
|
|
|
p_Src32 = (uint32_t*)(p_Src8 - (leftAlign >> 3));
|
|
|
|
p_Dst32 = (uint32_t*)(p_Dst8);
|
|
|
|
lastWord = *p_Src32++;
|
|
|
|
while(size >> 3) /* size >= 8 */
|
|
|
|
{
|
|
|
|
currWord = *p_Src32;
|
|
|
|
WRITE_UINT32(*p_Dst32, (lastWord << leftAlign) | (currWord >> rightAlign));
|
|
|
|
lastWord = currWord;
|
|
|
|
p_Src32++;p_Dst32++;
|
|
|
|
size -= 4;
|
|
|
|
}
|
|
|
|
p_Dst8 = (uint8_t*)(p_Dst32);
|
|
|
|
p_Src8 = (uint8_t*)(p_Src32) - 4 + (leftAlign >> 3);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* complete the left overs */
|
|
|
|
while (size--)
|
|
|
|
{
|
2017-10-30 03:41:04 +00:00
|
|
|
WRITE_UINT8(*p_Dst8, *p_Src8);
|
Add support for the Freescale dTSEC DPAA-based ethernet controller.
Freescale's QorIQ line includes a new ethernet controller, based on their
Datapath Acceleration Architecture (DPAA). This uses a combination of a Frame
manager, Buffer manager, and Queue manager to improve performance across all
interfaces by being able to pass data directly between hardware acceleration
interfaces.
As part of this import, Freescale's Netcomm Software (ncsw) driver is imported.
This was an attempt by Freescale to create an OS-agnostic sub-driver for
managing the hardware, using shims to interface to the OS-specific APIs. This
work was abandoned, and Freescale's primary work is in the Linux driver (dual
BSD/GPL license). Hence, this was imported directly to sys/contrib, rather than
going through the vendor area. Going forward, FreeBSD-specific changes may be
made to the ncsw code, diverging from the upstream in potentially incompatible
ways. An alternative could be to import the Linux driver itself, using the
linuxKPI layer, as that would maintain parity with the vendor-maintained driver.
However, the Linux driver has not been evaluated for reliability yet, and may
have issues with the import, whereas the ncsw-based driver in this commit was
completed by Semihalf 4 years ago, and is very stable.
Other SoC modules based on DPAA, which could be added in the future:
* Security and Encryption engine (SEC4.x, SEC5.x)
* RAID engine
Additional work to be done:
* Implement polling mode
* Test vlan support
* Add support for the Pattern Matching Engine, which can do regular expression
matching on packets.
This driver has been tested on the P5020 QorIQ SoC. Others listed in the
dtsec(4) manual page are expected to work as the same DPAA engine is included in
all.
Obtained from: Semihalf
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
2016-02-29 03:38:00 +00:00
|
|
|
p_Dst8++;p_Src8++;
|
|
|
|
}
|
|
|
|
|
|
|
|
return pDst;
|
|
|
|
}
|
|
|
|
|
|
|
|
void * IO2MemCpy32(void* pDst,void* pSrc, uint32_t size)
|
|
|
|
{
|
|
|
|
uint32_t leftAlign;
|
|
|
|
uint32_t rightAlign;
|
|
|
|
uint32_t lastWord;
|
|
|
|
uint32_t currWord;
|
|
|
|
uint32_t *p_Src32;
|
|
|
|
uint32_t *p_Dst32;
|
|
|
|
uint8_t *p_Src8;
|
|
|
|
uint8_t *p_Dst8;
|
|
|
|
|
|
|
|
p_Src8 = (uint8_t*)(pSrc);
|
|
|
|
p_Dst8 = (uint8_t*)(pDst);
|
|
|
|
/* first copy byte by byte till the source first alignment
|
|
|
|
* this step is necessary to ensure we do not even try to access
|
|
|
|
* data which is before the source buffer, hence it is not ours.
|
|
|
|
*/
|
|
|
|
while((PTR_TO_UINT(p_Src8) & 3) && size) /* (pSrc mod 4) > 0 and size > 0 */
|
|
|
|
{
|
2017-10-30 03:41:04 +00:00
|
|
|
*p_Dst8 = GET_UINT8(*p_Src8);
|
Add support for the Freescale dTSEC DPAA-based ethernet controller.
Freescale's QorIQ line includes a new ethernet controller, based on their
Datapath Acceleration Architecture (DPAA). This uses a combination of a Frame
manager, Buffer manager, and Queue manager to improve performance across all
interfaces by being able to pass data directly between hardware acceleration
interfaces.
As part of this import, Freescale's Netcomm Software (ncsw) driver is imported.
This was an attempt by Freescale to create an OS-agnostic sub-driver for
managing the hardware, using shims to interface to the OS-specific APIs. This
work was abandoned, and Freescale's primary work is in the Linux driver (dual
BSD/GPL license). Hence, this was imported directly to sys/contrib, rather than
going through the vendor area. Going forward, FreeBSD-specific changes may be
made to the ncsw code, diverging from the upstream in potentially incompatible
ways. An alternative could be to import the Linux driver itself, using the
linuxKPI layer, as that would maintain parity with the vendor-maintained driver.
However, the Linux driver has not been evaluated for reliability yet, and may
have issues with the import, whereas the ncsw-based driver in this commit was
completed by Semihalf 4 years ago, and is very stable.
Other SoC modules based on DPAA, which could be added in the future:
* Security and Encryption engine (SEC4.x, SEC5.x)
* RAID engine
Additional work to be done:
* Implement polling mode
* Test vlan support
* Add support for the Pattern Matching Engine, which can do regular expression
matching on packets.
This driver has been tested on the P5020 QorIQ SoC. Others listed in the
dtsec(4) manual page are expected to work as the same DPAA engine is included in
all.
Obtained from: Semihalf
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
2016-02-29 03:38:00 +00:00
|
|
|
p_Dst8++;p_Src8++;
|
|
|
|
size--;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* align destination (possibly disaligning source)*/
|
|
|
|
while((PTR_TO_UINT(p_Dst8) & 3) && size) /* (pDst mod 4) > 0 and size > 0 */
|
|
|
|
{
|
2017-10-30 03:41:04 +00:00
|
|
|
*p_Dst8 = GET_UINT8(*p_Src8);
|
Add support for the Freescale dTSEC DPAA-based ethernet controller.
Freescale's QorIQ line includes a new ethernet controller, based on their
Datapath Acceleration Architecture (DPAA). This uses a combination of a Frame
manager, Buffer manager, and Queue manager to improve performance across all
interfaces by being able to pass data directly between hardware acceleration
interfaces.
As part of this import, Freescale's Netcomm Software (ncsw) driver is imported.
This was an attempt by Freescale to create an OS-agnostic sub-driver for
managing the hardware, using shims to interface to the OS-specific APIs. This
work was abandoned, and Freescale's primary work is in the Linux driver (dual
BSD/GPL license). Hence, this was imported directly to sys/contrib, rather than
going through the vendor area. Going forward, FreeBSD-specific changes may be
made to the ncsw code, diverging from the upstream in potentially incompatible
ways. An alternative could be to import the Linux driver itself, using the
linuxKPI layer, as that would maintain parity with the vendor-maintained driver.
However, the Linux driver has not been evaluated for reliability yet, and may
have issues with the import, whereas the ncsw-based driver in this commit was
completed by Semihalf 4 years ago, and is very stable.
Other SoC modules based on DPAA, which could be added in the future:
* Security and Encryption engine (SEC4.x, SEC5.x)
* RAID engine
Additional work to be done:
* Implement polling mode
* Test vlan support
* Add support for the Pattern Matching Engine, which can do regular expression
matching on packets.
This driver has been tested on the P5020 QorIQ SoC. Others listed in the
dtsec(4) manual page are expected to work as the same DPAA engine is included in
all.
Obtained from: Semihalf
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
2016-02-29 03:38:00 +00:00
|
|
|
p_Dst8++;p_Src8++;
|
|
|
|
size--;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* dest is aligned and source is not necessarily aligned */
|
|
|
|
leftAlign = (uint32_t)((PTR_TO_UINT(p_Src8) & 3) << 3); /* leftAlign = (pSrc mod 4)*8 */
|
|
|
|
rightAlign = 32 - leftAlign;
|
|
|
|
|
|
|
|
if (leftAlign == 0)
|
|
|
|
{
|
|
|
|
/* source is also aligned */
|
|
|
|
p_Src32 = (uint32_t*)(p_Src8);
|
|
|
|
p_Dst32 = (uint32_t*)(p_Dst8);
|
|
|
|
while (size >> 2) /* size >= 4 */
|
|
|
|
{
|
|
|
|
*p_Dst32 = GET_UINT32(*p_Src32);
|
|
|
|
p_Dst32++;p_Src32++;
|
|
|
|
size -= 4;
|
|
|
|
}
|
|
|
|
p_Src8 = (uint8_t*)(p_Src32);
|
|
|
|
p_Dst8 = (uint8_t*)(p_Dst32);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* source is not aligned (destination is aligned)*/
|
|
|
|
p_Src32 = (uint32_t*)(p_Src8 - (leftAlign >> 3));
|
|
|
|
p_Dst32 = (uint32_t*)(p_Dst8);
|
|
|
|
lastWord = GET_UINT32(*p_Src32);
|
|
|
|
p_Src32++;
|
|
|
|
while(size >> 3) /* size >= 8 */
|
|
|
|
{
|
|
|
|
currWord = GET_UINT32(*p_Src32);
|
|
|
|
*p_Dst32 = (lastWord << leftAlign) | (currWord >> rightAlign);
|
|
|
|
lastWord = currWord;
|
|
|
|
p_Src32++;p_Dst32++;
|
|
|
|
size -= 4;
|
|
|
|
}
|
|
|
|
p_Dst8 = (uint8_t*)(p_Dst32);
|
|
|
|
p_Src8 = (uint8_t*)(p_Src32) - 4 + (leftAlign >> 3);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* complete the left overs */
|
|
|
|
while (size--)
|
|
|
|
{
|
2017-10-30 03:41:04 +00:00
|
|
|
*p_Dst8 = GET_UINT8(*p_Src8);
|
Add support for the Freescale dTSEC DPAA-based ethernet controller.
Freescale's QorIQ line includes a new ethernet controller, based on their
Datapath Acceleration Architecture (DPAA). This uses a combination of a Frame
manager, Buffer manager, and Queue manager to improve performance across all
interfaces by being able to pass data directly between hardware acceleration
interfaces.
As part of this import, Freescale's Netcomm Software (ncsw) driver is imported.
This was an attempt by Freescale to create an OS-agnostic sub-driver for
managing the hardware, using shims to interface to the OS-specific APIs. This
work was abandoned, and Freescale's primary work is in the Linux driver (dual
BSD/GPL license). Hence, this was imported directly to sys/contrib, rather than
going through the vendor area. Going forward, FreeBSD-specific changes may be
made to the ncsw code, diverging from the upstream in potentially incompatible
ways. An alternative could be to import the Linux driver itself, using the
linuxKPI layer, as that would maintain parity with the vendor-maintained driver.
However, the Linux driver has not been evaluated for reliability yet, and may
have issues with the import, whereas the ncsw-based driver in this commit was
completed by Semihalf 4 years ago, and is very stable.
Other SoC modules based on DPAA, which could be added in the future:
* Security and Encryption engine (SEC4.x, SEC5.x)
* RAID engine
Additional work to be done:
* Implement polling mode
* Test vlan support
* Add support for the Pattern Matching Engine, which can do regular expression
matching on packets.
This driver has been tested on the P5020 QorIQ SoC. Others listed in the
dtsec(4) manual page are expected to work as the same DPAA engine is included in
all.
Obtained from: Semihalf
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
2016-02-29 03:38:00 +00:00
|
|
|
p_Dst8++;p_Src8++;
|
|
|
|
}
|
|
|
|
|
|
|
|
return pDst;
|
|
|
|
}
|
|
|
|
|
|
|
|
void * MemCpy64(void* pDst,void* pSrc, uint32_t size)
|
|
|
|
{
|
|
|
|
uint32_t leftAlign;
|
|
|
|
uint32_t rightAlign;
|
|
|
|
uint64_t lastWord;
|
|
|
|
uint64_t currWord;
|
|
|
|
uint64_t *pSrc64;
|
|
|
|
uint64_t *pDst64;
|
|
|
|
uint8_t *p_Src8;
|
|
|
|
uint8_t *p_Dst8;
|
|
|
|
|
|
|
|
p_Src8 = (uint8_t*)(pSrc);
|
|
|
|
p_Dst8 = (uint8_t*)(pDst);
|
|
|
|
/* first copy byte by byte till the source first alignment
|
|
|
|
* this step is necessarily to ensure we do not even try to access
|
|
|
|
* data which is before the source buffer, hence it is not ours.
|
|
|
|
*/
|
|
|
|
while((PTR_TO_UINT(p_Src8) & 7) && size) /* (pSrc mod 8) > 0 and size > 0 */
|
|
|
|
{
|
|
|
|
*p_Dst8++ = *p_Src8++;
|
|
|
|
size--;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* align destination (possibly disaligning source)*/
|
|
|
|
while((PTR_TO_UINT(p_Dst8) & 7) && size) /* (pDst mod 8) > 0 and size > 0 */
|
|
|
|
{
|
|
|
|
*p_Dst8++ = *p_Src8++;
|
|
|
|
size--;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* dest is aligned and source is not necessarily aligned */
|
|
|
|
leftAlign = (uint32_t)((PTR_TO_UINT(p_Src8) & 7) << 3); /* leftAlign = (pSrc mod 8)*8 */
|
|
|
|
rightAlign = 64 - leftAlign;
|
|
|
|
|
|
|
|
|
|
|
|
if (leftAlign == 0)
|
|
|
|
{
|
|
|
|
/* source is also aligned */
|
|
|
|
pSrc64 = (uint64_t*)(p_Src8);
|
|
|
|
pDst64 = (uint64_t*)(p_Dst8);
|
|
|
|
while (size >> 3) /* size >= 8 */
|
|
|
|
{
|
|
|
|
*pDst64++ = *pSrc64++;
|
|
|
|
size -= 8;
|
|
|
|
}
|
|
|
|
p_Src8 = (uint8_t*)(pSrc64);
|
|
|
|
p_Dst8 = (uint8_t*)(pDst64);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* source is not aligned (destination is aligned)*/
|
|
|
|
pSrc64 = (uint64_t*)(p_Src8 - (leftAlign >> 3));
|
|
|
|
pDst64 = (uint64_t*)(p_Dst8);
|
|
|
|
lastWord = *pSrc64++;
|
|
|
|
while(size >> 4) /* size >= 16 */
|
|
|
|
{
|
|
|
|
currWord = *pSrc64;
|
|
|
|
*pDst64 = (lastWord << leftAlign) | (currWord >> rightAlign);
|
|
|
|
lastWord = currWord;
|
|
|
|
pSrc64++;
|
|
|
|
pDst64++;
|
|
|
|
size -= 8;
|
|
|
|
}
|
|
|
|
p_Dst8 = (uint8_t*)(pDst64);
|
|
|
|
p_Src8 = (uint8_t*)(pSrc64) - 8 + (leftAlign >> 3);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* complete the left overs */
|
|
|
|
while (size--)
|
|
|
|
*p_Dst8++ = *p_Src8++;
|
|
|
|
|
|
|
|
return pDst;
|
|
|
|
}
|
|
|
|
|
|
|
|
void * MemSet32(void* pDst, uint8_t val, uint32_t size)
|
|
|
|
{
|
|
|
|
uint32_t val32;
|
|
|
|
uint32_t *p_Dst32;
|
|
|
|
uint8_t *p_Dst8;
|
|
|
|
|
|
|
|
p_Dst8 = (uint8_t*)(pDst);
|
|
|
|
|
|
|
|
/* generate four 8-bit val's in 32-bit container */
|
|
|
|
val32 = (uint32_t) val;
|
|
|
|
val32 |= (val32 << 8);
|
|
|
|
val32 |= (val32 << 16);
|
|
|
|
|
|
|
|
/* align destination to 32 */
|
|
|
|
while((PTR_TO_UINT(p_Dst8) & 3) && size) /* (pDst mod 4) > 0 and size > 0 */
|
|
|
|
{
|
|
|
|
*p_Dst8++ = val;
|
|
|
|
size--;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* 32-bit chunks */
|
|
|
|
p_Dst32 = (uint32_t*)(p_Dst8);
|
|
|
|
while (size >> 2) /* size >= 4 */
|
|
|
|
{
|
|
|
|
*p_Dst32++ = val32;
|
|
|
|
size -= 4;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* complete the leftovers */
|
|
|
|
p_Dst8 = (uint8_t*)(p_Dst32);
|
|
|
|
while (size--)
|
|
|
|
*p_Dst8++ = val;
|
|
|
|
|
|
|
|
return pDst;
|
|
|
|
}
|
|
|
|
|
|
|
|
void * IOMemSet32(void* pDst, uint8_t val, uint32_t size)
|
|
|
|
{
|
|
|
|
uint32_t val32;
|
|
|
|
uint32_t *p_Dst32;
|
|
|
|
uint8_t *p_Dst8;
|
|
|
|
|
|
|
|
p_Dst8 = (uint8_t*)(pDst);
|
|
|
|
|
|
|
|
/* generate four 8-bit val's in 32-bit container */
|
|
|
|
val32 = (uint32_t) val;
|
|
|
|
val32 |= (val32 << 8);
|
|
|
|
val32 |= (val32 << 16);
|
|
|
|
|
|
|
|
/* align destination to 32 */
|
|
|
|
while((PTR_TO_UINT(p_Dst8) & 3) && size) /* (pDst mod 4) > 0 and size > 0 */
|
|
|
|
{
|
2017-10-30 03:41:04 +00:00
|
|
|
WRITE_UINT8(*p_Dst8, val);
|
Add support for the Freescale dTSEC DPAA-based ethernet controller.
Freescale's QorIQ line includes a new ethernet controller, based on their
Datapath Acceleration Architecture (DPAA). This uses a combination of a Frame
manager, Buffer manager, and Queue manager to improve performance across all
interfaces by being able to pass data directly between hardware acceleration
interfaces.
As part of this import, Freescale's Netcomm Software (ncsw) driver is imported.
This was an attempt by Freescale to create an OS-agnostic sub-driver for
managing the hardware, using shims to interface to the OS-specific APIs. This
work was abandoned, and Freescale's primary work is in the Linux driver (dual
BSD/GPL license). Hence, this was imported directly to sys/contrib, rather than
going through the vendor area. Going forward, FreeBSD-specific changes may be
made to the ncsw code, diverging from the upstream in potentially incompatible
ways. An alternative could be to import the Linux driver itself, using the
linuxKPI layer, as that would maintain parity with the vendor-maintained driver.
However, the Linux driver has not been evaluated for reliability yet, and may
have issues with the import, whereas the ncsw-based driver in this commit was
completed by Semihalf 4 years ago, and is very stable.
Other SoC modules based on DPAA, which could be added in the future:
* Security and Encryption engine (SEC4.x, SEC5.x)
* RAID engine
Additional work to be done:
* Implement polling mode
* Test vlan support
* Add support for the Pattern Matching Engine, which can do regular expression
matching on packets.
This driver has been tested on the P5020 QorIQ SoC. Others listed in the
dtsec(4) manual page are expected to work as the same DPAA engine is included in
all.
Obtained from: Semihalf
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
2016-02-29 03:38:00 +00:00
|
|
|
p_Dst8++;
|
|
|
|
size--;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* 32-bit chunks */
|
|
|
|
p_Dst32 = (uint32_t*)(p_Dst8);
|
|
|
|
while (size >> 2) /* size >= 4 */
|
|
|
|
{
|
|
|
|
WRITE_UINT32(*p_Dst32, val32);
|
|
|
|
p_Dst32++;
|
|
|
|
size -= 4;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* complete the leftovers */
|
|
|
|
p_Dst8 = (uint8_t*)(p_Dst32);
|
|
|
|
while (size--)
|
|
|
|
{
|
2017-10-30 03:41:04 +00:00
|
|
|
WRITE_UINT8(*p_Dst8, val);
|
Add support for the Freescale dTSEC DPAA-based ethernet controller.
Freescale's QorIQ line includes a new ethernet controller, based on their
Datapath Acceleration Architecture (DPAA). This uses a combination of a Frame
manager, Buffer manager, and Queue manager to improve performance across all
interfaces by being able to pass data directly between hardware acceleration
interfaces.
As part of this import, Freescale's Netcomm Software (ncsw) driver is imported.
This was an attempt by Freescale to create an OS-agnostic sub-driver for
managing the hardware, using shims to interface to the OS-specific APIs. This
work was abandoned, and Freescale's primary work is in the Linux driver (dual
BSD/GPL license). Hence, this was imported directly to sys/contrib, rather than
going through the vendor area. Going forward, FreeBSD-specific changes may be
made to the ncsw code, diverging from the upstream in potentially incompatible
ways. An alternative could be to import the Linux driver itself, using the
linuxKPI layer, as that would maintain parity with the vendor-maintained driver.
However, the Linux driver has not been evaluated for reliability yet, and may
have issues with the import, whereas the ncsw-based driver in this commit was
completed by Semihalf 4 years ago, and is very stable.
Other SoC modules based on DPAA, which could be added in the future:
* Security and Encryption engine (SEC4.x, SEC5.x)
* RAID engine
Additional work to be done:
* Implement polling mode
* Test vlan support
* Add support for the Pattern Matching Engine, which can do regular expression
matching on packets.
This driver has been tested on the P5020 QorIQ SoC. Others listed in the
dtsec(4) manual page are expected to work as the same DPAA engine is included in
all.
Obtained from: Semihalf
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
2016-02-29 03:38:00 +00:00
|
|
|
p_Dst8++;
|
|
|
|
}
|
|
|
|
|
|
|
|
return pDst;
|
|
|
|
}
|
|
|
|
|
|
|
|
void * MemSet64(void* pDst, uint8_t val, uint32_t size)
|
|
|
|
{
|
|
|
|
uint64_t val64;
|
|
|
|
uint64_t *pDst64;
|
|
|
|
uint8_t *p_Dst8;
|
|
|
|
|
|
|
|
p_Dst8 = (uint8_t*)(pDst);
|
|
|
|
|
|
|
|
/* generate four 8-bit val's in 32-bit container */
|
|
|
|
val64 = (uint64_t) val;
|
|
|
|
val64 |= (val64 << 8);
|
|
|
|
val64 |= (val64 << 16);
|
|
|
|
val64 |= (val64 << 24);
|
|
|
|
val64 |= (val64 << 32);
|
|
|
|
|
|
|
|
/* align destination to 64 */
|
|
|
|
while((PTR_TO_UINT(p_Dst8) & 7) && size) /* (pDst mod 8) > 0 and size > 0 */
|
|
|
|
{
|
|
|
|
*p_Dst8++ = val;
|
|
|
|
size--;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* 64-bit chunks */
|
|
|
|
pDst64 = (uint64_t*)(p_Dst8);
|
|
|
|
while (size >> 4) /* size >= 8 */
|
|
|
|
{
|
|
|
|
*pDst64++ = val64;
|
|
|
|
size -= 8;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* complete the leftovers */
|
|
|
|
p_Dst8 = (uint8_t*)(pDst64);
|
|
|
|
while (size--)
|
|
|
|
*p_Dst8++ = val;
|
|
|
|
|
|
|
|
return pDst;
|
|
|
|
}
|
|
|
|
|
|
|
|
void MemDisp(uint8_t *p, int size)
|
|
|
|
{
|
|
|
|
uint32_t space = (uint32_t)(PTR_TO_UINT(p) & 0x3);
|
|
|
|
uint8_t *p_Limit;
|
|
|
|
|
|
|
|
if (space)
|
|
|
|
{
|
|
|
|
p_Limit = (p - space + 4);
|
|
|
|
|
|
|
|
XX_Print("0x%08X: ", (p - space));
|
|
|
|
|
|
|
|
while (space--)
|
|
|
|
{
|
|
|
|
XX_Print("--");
|
|
|
|
}
|
|
|
|
while (size && (p < p_Limit))
|
|
|
|
{
|
|
|
|
XX_Print("%02x", *(uint8_t*)p);
|
|
|
|
size--;
|
|
|
|
p++;
|
|
|
|
}
|
|
|
|
|
|
|
|
XX_Print(" ");
|
|
|
|
p_Limit += 12;
|
|
|
|
|
|
|
|
while ((size > 3) && (p < p_Limit))
|
|
|
|
{
|
|
|
|
XX_Print("%08x ", *(uint32_t*)p);
|
|
|
|
size -= 4;
|
|
|
|
p += 4;
|
|
|
|
}
|
|
|
|
XX_Print("\r\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
while (size > 15)
|
|
|
|
{
|
|
|
|
XX_Print("0x%08X: %08x %08x %08x %08x\r\n",
|
|
|
|
p, *(uint32_t *)p, *(uint32_t *)(p + 4),
|
|
|
|
*(uint32_t *)(p + 8), *(uint32_t *)(p + 12));
|
|
|
|
size -= 16;
|
|
|
|
p += 16;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (size)
|
|
|
|
{
|
|
|
|
XX_Print("0x%08X: ", p);
|
|
|
|
|
|
|
|
while (size > 3)
|
|
|
|
{
|
|
|
|
XX_Print("%08x ", *(uint32_t *)p);
|
|
|
|
size -= 4;
|
|
|
|
p += 4;
|
|
|
|
}
|
|
|
|
while (size)
|
|
|
|
{
|
|
|
|
XX_Print("%02x", *(uint8_t *)p);
|
|
|
|
size--;
|
|
|
|
p++;
|
|
|
|
}
|
|
|
|
|
|
|
|
XX_Print("\r\n");
|
|
|
|
}
|
|
|
|
}
|