2016-04-06 23:11:03 +00:00
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/*-
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* Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Allwinner CPU clock
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <machine/bus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/ofw/ofw_subr.h>
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#include <dev/extres/clk/clk_mux.h>
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2016-09-07 01:10:16 +00:00
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#define A10_CPU_CLK_SRC_SEL_WIDTH 2
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#define A10_CPU_CLK_SRC_SEL_SHIFT 16
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#define A83T_Cx_CLK_SRC_SEL_WIDTH 1
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#define A83T_C0_CLK_SRC_SEL_SHIFT 12
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#define A83T_C1_CLK_SRC_SEL_SHIFT 28
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struct aw_cpuclk_config {
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u_int width;
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u_int shift;
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};
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static struct aw_cpuclk_config a10_config = {
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.width = A10_CPU_CLK_SRC_SEL_WIDTH,
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.shift = A10_CPU_CLK_SRC_SEL_SHIFT,
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};
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static struct aw_cpuclk_config a83t_c0_config = {
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.width = A83T_Cx_CLK_SRC_SEL_WIDTH,
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.shift = A83T_C0_CLK_SRC_SEL_SHIFT,
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};
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static struct aw_cpuclk_config a83t_c1_config = {
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.width = A83T_Cx_CLK_SRC_SEL_WIDTH,
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.shift = A83T_C1_CLK_SRC_SEL_SHIFT,
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};
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static struct ofw_compat_data compat_data[] = {
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{ "allwinner,sun4i-a10-cpu-clk", (uintptr_t)&a10_config },
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{ "allwinner,sun8i-a83t-c0cpu-clk", (uintptr_t)&a83t_c0_config },
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{ "allwinner,sun8i-a83t-c1cpu-clk", (uintptr_t)&a83t_c1_config },
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{ NULL, (uintptr_t)NULL }
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};
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#define CPUCLK_CONF(d) \
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(void *)ofw_bus_search_compatible((d), compat_data)->ocd_data
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2016-04-06 23:11:03 +00:00
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static int
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aw_cpuclk_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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2016-09-07 01:10:16 +00:00
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if (CPUCLK_CONF(dev) == NULL)
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2016-04-06 23:11:03 +00:00
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return (ENXIO);
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device_set_desc(dev, "Allwinner CPU Clock");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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aw_cpuclk_attach(device_t dev)
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{
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struct clk_mux_def def;
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struct clkdom *clkdom;
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2016-09-07 01:10:16 +00:00
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struct aw_cpuclk_config *conf;
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2016-04-06 23:11:03 +00:00
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bus_addr_t paddr;
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bus_size_t psize;
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phandle_t node;
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int error, ncells, i;
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clk_t clk;
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node = ofw_bus_get_node(dev);
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2016-09-07 01:10:16 +00:00
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conf = CPUCLK_CONF(dev);
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2016-04-06 23:11:03 +00:00
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if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) {
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device_printf(dev, "cannot parse 'reg' property\n");
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return (ENXIO);
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}
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error = ofw_bus_parse_xref_list_get_length(node, "clocks",
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"#clock-cells", &ncells);
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if (error != 0) {
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device_printf(dev, "cannot get clock count\n");
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return (error);
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}
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clkdom = clkdom_create(dev);
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memset(&def, 0, sizeof(def));
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def.clkdef.id = 1;
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def.clkdef.parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP,
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M_WAITOK);
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for (i = 0; i < ncells; i++) {
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2016-07-10 18:28:15 +00:00
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error = clk_get_by_ofw_index(dev, 0, i, &clk);
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2016-04-06 23:11:03 +00:00
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if (error != 0) {
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device_printf(dev, "cannot get clock %d\n", i);
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goto fail;
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}
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def.clkdef.parent_names[i] = clk_get_name(clk);
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clk_release(clk);
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}
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def.clkdef.parent_cnt = ncells;
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def.offset = paddr;
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2016-09-07 01:10:16 +00:00
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def.shift = conf->shift;
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def.width = conf->width;
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2016-04-06 23:11:03 +00:00
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error = clk_parse_ofw_clk_name(dev, node, &def.clkdef.name);
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if (error != 0) {
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device_printf(dev, "cannot parse clock name\n");
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error = ENXIO;
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goto fail;
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}
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error = clknode_mux_register(clkdom, &def);
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if (error != 0) {
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device_printf(dev, "cannot register mux clock\n");
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error = ENXIO;
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goto fail;
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}
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if (clkdom_finit(clkdom) != 0) {
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device_printf(dev, "cannot finalize clkdom initialization\n");
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error = ENXIO;
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goto fail;
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}
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2016-05-13 22:28:02 +00:00
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OF_prop_free(__DECONST(char *, def.clkdef.parent_names));
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OF_prop_free(__DECONST(char *, def.clkdef.name));
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2016-04-06 23:11:03 +00:00
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if (bootverbose)
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clkdom_dump(clkdom);
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return (0);
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fail:
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2016-05-13 22:28:02 +00:00
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OF_prop_free(__DECONST(char *, def.clkdef.name));
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2016-04-06 23:11:03 +00:00
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return (error);
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}
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static device_method_t aw_cpuclk_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, aw_cpuclk_probe),
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DEVMETHOD(device_attach, aw_cpuclk_attach),
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DEVMETHOD_END
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};
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static driver_t aw_cpuclk_driver = {
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"aw_cpuclk",
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aw_cpuclk_methods,
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0
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};
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static devclass_t aw_cpuclk_devclass;
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EARLY_DRIVER_MODULE(aw_cpuclk, simplebus, aw_cpuclk_driver,
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aw_cpuclk_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
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