2005-01-06 01:43:34 +00:00
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/*-
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2001-09-27 23:55:28 +00:00
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* Copyright (c) 2001 Wind River Systems
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* Copyright (c) 1997, 1998, 1999, 2001
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* Bill Paul <wpaul@windriver.com>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Bill Paul.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*/
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2003-08-24 17:55:58 +00:00
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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2001-09-27 23:55:28 +00:00
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/*
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* Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
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2003-04-03 21:36:33 +00:00
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*
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2001-09-27 23:55:28 +00:00
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* The Broadcom BCM5700 is based on technology originally developed by
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* Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
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* MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
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* two on-board MIPS R4000 CPUs and can have as much as 16MB of external
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* SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
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* frames, highly configurable RX filtering, and 16 RX and TX queues
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* (which, along with RX filter rules, can be used for QOS applications).
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* Other features, such as TCP segmentation, may be available as part
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* of value-added firmware updates. Unlike the Tigon I and Tigon II,
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* firmware images can be stored in hardware and need not be compiled
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* into the driver.
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*
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* The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
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* function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
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2004-10-30 14:54:51 +00:00
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*
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2001-09-27 23:55:28 +00:00
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* The BCM5701 is a single-chip solution incorporating both the BCM5700
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2002-03-22 06:45:40 +00:00
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* MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
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2001-09-27 23:55:28 +00:00
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* does not support external SSRAM.
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*
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* Broadcom also produces a variation of the BCM5700 under the "Altima"
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* brand name, which is functionally similar but lacks PCI-X support.
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*
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* Without external SSRAM, you can only have at most 4 TX rings,
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* and the use of the mini RX ring is disabled. This seems to imply
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* that these features are simply not available on the BCM5701. As a
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* result, this driver does not implement any support for the mini RX
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* ring.
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*/
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2005-10-22 14:31:01 +00:00
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#ifdef HAVE_KERNEL_OPTION_HEADERS
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#include "opt_device_polling.h"
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#endif
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2001-09-27 23:55:28 +00:00
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#include <sys/param.h>
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2003-07-25 19:42:44 +00:00
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#include <sys/endian.h>
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2001-09-27 23:55:28 +00:00
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#include <sys/systm.h>
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#include <sys/sockio.h>
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#include <sys/mbuf.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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2004-05-30 20:08:47 +00:00
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#include <sys/module.h>
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2001-09-27 23:55:28 +00:00
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#include <sys/socket.h>
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2006-09-23 18:55:49 +00:00
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#include <sys/sysctl.h>
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2001-09-27 23:55:28 +00:00
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#include <net/if.h>
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#include <net/if_arp.h>
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#include <net/ethernet.h>
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#include <net/if_dl.h>
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#include <net/if_media.h>
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#include <net/bpf.h>
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#include <net/if_types.h>
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#include <net/if_vlan_var.h>
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#include <netinet/in_systm.h>
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#include <netinet/in.h>
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#include <netinet/ip.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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2003-01-19 02:59:34 +00:00
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#include "miidevs.h"
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2001-09-27 23:55:28 +00:00
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#include <dev/mii/brgphyreg.h>
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2003-08-22 05:54:52 +00:00
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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2001-09-27 23:55:28 +00:00
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#include <dev/bge/if_bgereg.h>
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2002-07-04 23:19:20 +00:00
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#define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
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2005-12-22 15:14:42 +00:00
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#define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
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2001-09-27 23:55:28 +00:00
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2003-04-15 06:37:30 +00:00
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MODULE_DEPEND(bge, pci, 1, 1, 1);
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MODULE_DEPEND(bge, ether, 1, 1, 1);
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2001-09-27 23:55:28 +00:00
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MODULE_DEPEND(bge, miibus, 1, 1, 1);
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2005-10-22 05:06:55 +00:00
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/* "device miibus" required. See GENERIC if you get errors here. */
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2001-09-27 23:55:28 +00:00
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#include "miibus_if.h"
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/*
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* Various supported device vendors/types and their names. Note: the
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* spec seems to indicate that the hardware still has Alteon's vendor
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* ID burned into it, though it will always be overriden by the vendor
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* ID in the EEPROM. Just to be safe, we cover all possibilities.
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*/
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2006-06-15 14:31:49 +00:00
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static struct bge_type {
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uint16_t bge_vid;
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uint16_t bge_did;
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} bge_devs[] = {
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{ ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 },
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{ ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 },
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{ ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 },
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{ ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 },
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{ ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 },
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{ APPLE_VENDORID, APPLE_DEVICE_BCM5701 },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5700 },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5701 },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5702 },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5702X },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5703 },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5703X },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5704C },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5704S },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5705 },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5705F },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5705K },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5705M },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5714C },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5714S },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5715 },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5715S },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5720 },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5721 },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5750 },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5750M },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5751 },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5751F },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5751M },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5752 },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5752M },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5753 },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5753F },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5753M },
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2006-06-28 09:12:29 +00:00
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5754 },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5754M },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5755 },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5755M },
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2006-06-15 14:31:49 +00:00
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5780 },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5780S },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5781 },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5782 },
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2006-06-28 09:12:29 +00:00
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5786 },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5787 },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5787M },
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2006-06-15 14:31:49 +00:00
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5788 },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5789 },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5901 },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5903M },
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{ SK_VENDORID, SK_DEVICEID_ALTIMA },
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{ TC_VENDORID, TC_DEVICEID_3C996 },
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{ 0, 0 }
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};
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static const struct bge_vendor {
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uint16_t v_id;
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const char *v_name;
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} bge_vendors[] = {
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{ ALTEON_VENDORID, "Alteon" },
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{ ALTIMA_VENDORID, "Altima" },
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{ APPLE_VENDORID, "Apple" },
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{ BCOM_VENDORID, "Broadcom" },
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{ SK_VENDORID, "SysKonnect" },
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{ TC_VENDORID, "3Com" },
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{ 0, NULL }
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};
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static const struct bge_revision {
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uint32_t br_chipid;
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const char *br_name;
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} bge_revisions[] = {
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{ BGE_CHIPID_BCM5700_A0, "BCM5700 A0" },
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{ BGE_CHIPID_BCM5700_A1, "BCM5700 A1" },
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{ BGE_CHIPID_BCM5700_B0, "BCM5700 B0" },
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{ BGE_CHIPID_BCM5700_B1, "BCM5700 B1" },
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{ BGE_CHIPID_BCM5700_B2, "BCM5700 B2" },
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{ BGE_CHIPID_BCM5700_B3, "BCM5700 B3" },
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{ BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" },
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{ BGE_CHIPID_BCM5700_C0, "BCM5700 C0" },
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{ BGE_CHIPID_BCM5701_A0, "BCM5701 A0" },
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{ BGE_CHIPID_BCM5701_B0, "BCM5701 B0" },
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{ BGE_CHIPID_BCM5701_B2, "BCM5701 B2" },
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{ BGE_CHIPID_BCM5701_B5, "BCM5701 B5" },
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{ BGE_CHIPID_BCM5703_A0, "BCM5703 A0" },
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{ BGE_CHIPID_BCM5703_A1, "BCM5703 A1" },
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{ BGE_CHIPID_BCM5703_A2, "BCM5703 A2" },
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{ BGE_CHIPID_BCM5703_A3, "BCM5703 A3" },
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2006-06-28 09:12:29 +00:00
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{ BGE_CHIPID_BCM5703_B0, "BCM5703 B0" },
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2006-06-15 14:31:49 +00:00
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{ BGE_CHIPID_BCM5704_A0, "BCM5704 A0" },
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{ BGE_CHIPID_BCM5704_A1, "BCM5704 A1" },
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{ BGE_CHIPID_BCM5704_A2, "BCM5704 A2" },
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{ BGE_CHIPID_BCM5704_A3, "BCM5704 A3" },
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{ BGE_CHIPID_BCM5704_B0, "BCM5704 B0" },
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{ BGE_CHIPID_BCM5705_A0, "BCM5705 A0" },
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{ BGE_CHIPID_BCM5705_A1, "BCM5705 A1" },
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{ BGE_CHIPID_BCM5705_A2, "BCM5705 A2" },
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{ BGE_CHIPID_BCM5705_A3, "BCM5705 A3" },
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{ BGE_CHIPID_BCM5750_A0, "BCM5750 A0" },
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{ BGE_CHIPID_BCM5750_A1, "BCM5750 A1" },
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{ BGE_CHIPID_BCM5750_A3, "BCM5750 A3" },
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{ BGE_CHIPID_BCM5750_B0, "BCM5750 B0" },
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{ BGE_CHIPID_BCM5750_B1, "BCM5750 B1" },
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{ BGE_CHIPID_BCM5750_C0, "BCM5750 C0" },
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{ BGE_CHIPID_BCM5750_C1, "BCM5750 C1" },
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2006-08-07 12:51:50 +00:00
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{ BGE_CHIPID_BCM5750_C2, "BCM5750 C2" },
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2006-06-15 14:31:49 +00:00
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{ BGE_CHIPID_BCM5714_A0, "BCM5714 A0" },
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{ BGE_CHIPID_BCM5752_A0, "BCM5752 A0" },
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{ BGE_CHIPID_BCM5752_A1, "BCM5752 A1" },
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{ BGE_CHIPID_BCM5752_A2, "BCM5752 A2" },
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{ BGE_CHIPID_BCM5714_B0, "BCM5714 B0" },
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{ BGE_CHIPID_BCM5714_B3, "BCM5714 B3" },
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{ BGE_CHIPID_BCM5715_A0, "BCM5715 A0" },
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{ BGE_CHIPID_BCM5715_A1, "BCM5715 A1" },
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{ 0, NULL }
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};
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/*
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* Some defaults for major revisions, so that newer steppings
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* that we don't know about have a shot at working.
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*/
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static const struct bge_revision bge_majorrevs[] = {
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2006-06-28 09:12:29 +00:00
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{ BGE_ASICREV_BCM5700, "unknown BCM5700" },
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|
|
{ BGE_ASICREV_BCM5701, "unknown BCM5701" },
|
|
|
|
{ BGE_ASICREV_BCM5703, "unknown BCM5703" },
|
|
|
|
{ BGE_ASICREV_BCM5704, "unknown BCM5704" },
|
|
|
|
{ BGE_ASICREV_BCM5705, "unknown BCM5705" },
|
|
|
|
{ BGE_ASICREV_BCM5750, "unknown BCM5750" },
|
|
|
|
{ BGE_ASICREV_BCM5714_A0, "unknown BCM5714" },
|
|
|
|
{ BGE_ASICREV_BCM5752, "unknown BCM5752" },
|
|
|
|
{ BGE_ASICREV_BCM5780, "unknown BCM5780" },
|
|
|
|
{ BGE_ASICREV_BCM5714, "unknown BCM5714" },
|
|
|
|
{ BGE_ASICREV_BCM5755, "unknown BCM5755" },
|
|
|
|
{ BGE_ASICREV_BCM5787, "unknown BCM5787" },
|
2006-06-15 14:31:49 +00:00
|
|
|
|
|
|
|
{ 0, NULL }
|
2001-09-27 23:55:28 +00:00
|
|
|
};
|
|
|
|
|
2006-06-15 14:31:49 +00:00
|
|
|
#define BGE_IS_5705_OR_BEYOND(sc) \
|
|
|
|
((sc)->bge_asicrev == BGE_ASICREV_BCM5705 || \
|
|
|
|
(sc)->bge_asicrev == BGE_ASICREV_BCM5750 || \
|
|
|
|
(sc)->bge_asicrev == BGE_ASICREV_BCM5714_A0 || \
|
|
|
|
(sc)->bge_asicrev == BGE_ASICREV_BCM5780 || \
|
|
|
|
(sc)->bge_asicrev == BGE_ASICREV_BCM5714 || \
|
2006-06-28 09:12:29 +00:00
|
|
|
(sc)->bge_asicrev == BGE_ASICREV_BCM5752 || \
|
|
|
|
(sc)->bge_asicrev == BGE_ASICREV_BCM5755 || \
|
|
|
|
(sc)->bge_asicrev == BGE_ASICREV_BCM5787)
|
2006-06-15 14:31:49 +00:00
|
|
|
|
|
|
|
#define BGE_IS_575X_PLUS(sc) \
|
|
|
|
((sc)->bge_asicrev == BGE_ASICREV_BCM5750 || \
|
|
|
|
(sc)->bge_asicrev == BGE_ASICREV_BCM5714_A0 || \
|
|
|
|
(sc)->bge_asicrev == BGE_ASICREV_BCM5780 || \
|
|
|
|
(sc)->bge_asicrev == BGE_ASICREV_BCM5714 || \
|
2006-06-28 09:12:29 +00:00
|
|
|
(sc)->bge_asicrev == BGE_ASICREV_BCM5752 || \
|
|
|
|
(sc)->bge_asicrev == BGE_ASICREV_BCM5755 || \
|
|
|
|
(sc)->bge_asicrev == BGE_ASICREV_BCM5787)
|
2006-06-15 14:31:49 +00:00
|
|
|
|
|
|
|
#define BGE_IS_5714_FAMILY(sc) \
|
|
|
|
((sc)->bge_asicrev == BGE_ASICREV_BCM5714_A0 || \
|
|
|
|
(sc)->bge_asicrev == BGE_ASICREV_BCM5780 || \
|
|
|
|
(sc)->bge_asicrev == BGE_ASICREV_BCM5714)
|
|
|
|
|
2006-06-28 09:12:29 +00:00
|
|
|
#define BGE_IS_JUMBO_CAPABLE(sc) \
|
|
|
|
((sc)->bge_asicrev == BGE_ASICREV_BCM5700 || \
|
|
|
|
(sc)->bge_asicrev == BGE_ASICREV_BCM5701 || \
|
|
|
|
(sc)->bge_asicrev == BGE_ASICREV_BCM5703 || \
|
|
|
|
(sc)->bge_asicrev == BGE_ASICREV_BCM5704)
|
2006-06-15 14:31:49 +00:00
|
|
|
|
|
|
|
const struct bge_revision * bge_lookup_rev(uint32_t);
|
|
|
|
const struct bge_vendor * bge_lookup_vendor(uint16_t);
|
2006-06-07 21:03:20 +00:00
|
|
|
static int bge_probe(device_t);
|
|
|
|
static int bge_attach(device_t);
|
|
|
|
static int bge_detach(device_t);
|
|
|
|
static int bge_suspend(device_t);
|
|
|
|
static int bge_resume(device_t);
|
|
|
|
static void bge_release_resources(struct bge_softc *);
|
|
|
|
static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
|
|
|
|
static int bge_dma_alloc(device_t);
|
|
|
|
static void bge_dma_free(struct bge_softc *);
|
|
|
|
|
|
|
|
static void bge_txeof(struct bge_softc *);
|
|
|
|
static void bge_rxeof(struct bge_softc *);
|
|
|
|
|
2006-09-09 03:36:57 +00:00
|
|
|
static void bge_asf_driver_up (struct bge_softc *);
|
2006-06-07 21:03:20 +00:00
|
|
|
static void bge_tick_locked(struct bge_softc *);
|
|
|
|
static void bge_tick(void *);
|
|
|
|
static void bge_stats_update(struct bge_softc *);
|
|
|
|
static void bge_stats_update_regs(struct bge_softc *);
|
2006-08-17 09:53:04 +00:00
|
|
|
static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
|
2006-06-07 21:03:20 +00:00
|
|
|
|
|
|
|
static void bge_intr(void *);
|
|
|
|
static void bge_start_locked(struct ifnet *);
|
|
|
|
static void bge_start(struct ifnet *);
|
|
|
|
static int bge_ioctl(struct ifnet *, u_long, caddr_t);
|
|
|
|
static void bge_init_locked(struct bge_softc *);
|
|
|
|
static void bge_init(void *);
|
|
|
|
static void bge_stop(struct bge_softc *);
|
|
|
|
static void bge_watchdog(struct ifnet *);
|
|
|
|
static void bge_shutdown(device_t);
|
2006-08-24 14:41:16 +00:00
|
|
|
static int bge_ifmedia_upd_locked(struct ifnet *);
|
2006-06-07 21:03:20 +00:00
|
|
|
static int bge_ifmedia_upd(struct ifnet *);
|
|
|
|
static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
|
|
|
|
|
|
|
|
static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
|
|
|
|
static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
|
|
|
|
|
2006-09-18 22:18:21 +00:00
|
|
|
static void bge_setpromisc(struct bge_softc *);
|
2006-06-07 21:03:20 +00:00
|
|
|
static void bge_setmulti(struct bge_softc *);
|
|
|
|
|
|
|
|
static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *);
|
|
|
|
static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
|
|
|
|
static int bge_init_rx_ring_std(struct bge_softc *);
|
|
|
|
static void bge_free_rx_ring_std(struct bge_softc *);
|
|
|
|
static int bge_init_rx_ring_jumbo(struct bge_softc *);
|
|
|
|
static void bge_free_rx_ring_jumbo(struct bge_softc *);
|
|
|
|
static void bge_free_tx_ring(struct bge_softc *);
|
|
|
|
static int bge_init_tx_ring(struct bge_softc *);
|
|
|
|
|
|
|
|
static int bge_chipinit(struct bge_softc *);
|
|
|
|
static int bge_blockinit(struct bge_softc *);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
static uint32_t bge_readmem_ind(struct bge_softc *, int);
|
|
|
|
static void bge_writemem_ind(struct bge_softc *, int, int);
|
2001-09-27 23:55:28 +00:00
|
|
|
#ifdef notdef
|
2006-06-07 21:03:20 +00:00
|
|
|
static uint32_t bge_readreg_ind(struct bge_softc *, int);
|
2001-09-27 23:55:28 +00:00
|
|
|
#endif
|
2006-06-07 21:03:20 +00:00
|
|
|
static void bge_writereg_ind(struct bge_softc *, int, int);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
static int bge_miibus_readreg(device_t, int, int);
|
|
|
|
static int bge_miibus_writereg(device_t, int, int, int);
|
|
|
|
static void bge_miibus_statchg(device_t);
|
2005-10-22 14:31:01 +00:00
|
|
|
#ifdef DEVICE_POLLING
|
2006-06-07 21:03:20 +00:00
|
|
|
static void bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
|
2005-10-22 14:31:01 +00:00
|
|
|
#endif
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2006-09-09 03:36:57 +00:00
|
|
|
#define BGE_RESET_START 1
|
|
|
|
#define BGE_RESET_STOP 2
|
|
|
|
static void bge_sig_post_reset(struct bge_softc *, int);
|
|
|
|
static void bge_sig_legacy(struct bge_softc *, int);
|
|
|
|
static void bge_sig_pre_reset(struct bge_softc *, int);
|
|
|
|
static int bge_reset(struct bge_softc *);
|
2006-06-07 21:03:20 +00:00
|
|
|
static void bge_link_upd(struct bge_softc *);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
static device_method_t bge_methods[] = {
|
|
|
|
/* Device interface */
|
|
|
|
DEVMETHOD(device_probe, bge_probe),
|
|
|
|
DEVMETHOD(device_attach, bge_attach),
|
|
|
|
DEVMETHOD(device_detach, bge_detach),
|
|
|
|
DEVMETHOD(device_shutdown, bge_shutdown),
|
2005-09-28 19:20:49 +00:00
|
|
|
DEVMETHOD(device_suspend, bge_suspend),
|
|
|
|
DEVMETHOD(device_resume, bge_resume),
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
/* bus interface */
|
|
|
|
DEVMETHOD(bus_print_child, bus_generic_print_child),
|
|
|
|
DEVMETHOD(bus_driver_added, bus_generic_driver_added),
|
|
|
|
|
|
|
|
/* MII interface */
|
|
|
|
DEVMETHOD(miibus_readreg, bge_miibus_readreg),
|
|
|
|
DEVMETHOD(miibus_writereg, bge_miibus_writereg),
|
|
|
|
DEVMETHOD(miibus_statchg, bge_miibus_statchg),
|
|
|
|
|
|
|
|
{ 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static driver_t bge_driver = {
|
|
|
|
"bge",
|
|
|
|
bge_methods,
|
|
|
|
sizeof(struct bge_softc)
|
|
|
|
};
|
|
|
|
|
|
|
|
static devclass_t bge_devclass;
|
|
|
|
|
2003-04-15 06:37:30 +00:00
|
|
|
DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0);
|
2001-09-27 23:55:28 +00:00
|
|
|
DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
|
|
|
|
|
2006-04-25 15:56:52 +00:00
|
|
|
static int bge_fake_autoneg = 0;
|
2006-09-23 18:55:49 +00:00
|
|
|
static int bge_allow_asf = 1;
|
|
|
|
|
2006-04-25 15:56:52 +00:00
|
|
|
TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
|
2006-09-23 18:55:49 +00:00
|
|
|
TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf);
|
|
|
|
|
|
|
|
SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters");
|
|
|
|
SYSCTL_INT(_hw_bge, OID_AUTO, fake_autoneg, CTLFLAG_RD, &bge_fake_autoneg, 0,
|
|
|
|
"Enable fake autonegotiation for certain blade systems");
|
|
|
|
SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0,
|
|
|
|
"Allow ASF mode if available");
|
2006-04-25 15:56:52 +00:00
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
static uint32_t
|
|
|
|
bge_readmem_ind(struct bge_softc *sc, int off)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
|
|
|
device_t dev;
|
|
|
|
|
|
|
|
dev = sc->bge_dev;
|
|
|
|
|
|
|
|
pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
|
2006-06-07 21:03:20 +00:00
|
|
|
return (pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4));
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_writemem_ind(struct bge_softc *sc, int off, int val)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
|
|
|
device_t dev;
|
|
|
|
|
|
|
|
dev = sc->bge_dev;
|
|
|
|
|
|
|
|
pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
|
|
|
|
pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef notdef
|
2006-06-07 21:03:20 +00:00
|
|
|
static uint32_t
|
|
|
|
bge_readreg_ind(struct bge_softc *sc, int off)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
|
|
|
device_t dev;
|
|
|
|
|
|
|
|
dev = sc->bge_dev;
|
|
|
|
|
|
|
|
pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
|
2006-06-07 21:03:20 +00:00
|
|
|
return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static void
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_writereg_ind(struct bge_softc *sc, int off, int val)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
|
|
|
device_t dev;
|
|
|
|
|
|
|
|
dev = sc->bge_dev;
|
|
|
|
|
|
|
|
pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
|
|
|
|
pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
|
|
|
|
}
|
|
|
|
|
2003-07-25 19:42:44 +00:00
|
|
|
/*
|
|
|
|
* Map a single buffer address.
|
|
|
|
*/
|
|
|
|
|
|
|
|
static void
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
|
2003-07-25 19:42:44 +00:00
|
|
|
{
|
|
|
|
struct bge_dmamap_arg *ctx;
|
|
|
|
|
|
|
|
if (error)
|
|
|
|
return;
|
|
|
|
|
|
|
|
ctx = arg;
|
|
|
|
|
|
|
|
if (nseg > ctx->bge_maxsegs) {
|
|
|
|
ctx->bge_maxsegs = 0;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
ctx->bge_busaddr = segs->ds_addr;
|
|
|
|
}
|
|
|
|
|
2001-09-27 23:55:28 +00:00
|
|
|
/*
|
|
|
|
* Read a byte of data stored in the EEPROM at address 'addr.' The
|
|
|
|
* BCM570x supports both the traditional bitbang interface and an
|
|
|
|
* auto access interface for reading the EEPROM. We use the auto
|
|
|
|
* access method.
|
|
|
|
*/
|
2006-06-07 21:03:20 +00:00
|
|
|
static uint8_t
|
|
|
|
bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
|
|
|
int i;
|
2006-06-07 21:03:20 +00:00
|
|
|
uint32_t byte = 0;
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable use of auto EEPROM access so we can avoid
|
|
|
|
* having to use the bitbang method.
|
|
|
|
*/
|
|
|
|
BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
|
|
|
|
|
|
|
|
/* Reset the EEPROM, load the clock period. */
|
|
|
|
CSR_WRITE_4(sc, BGE_EE_ADDR,
|
|
|
|
BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
|
|
|
|
DELAY(20);
|
|
|
|
|
|
|
|
/* Issue the read EEPROM command. */
|
|
|
|
CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
|
|
|
|
|
|
|
|
/* Wait for completion */
|
|
|
|
for(i = 0; i < BGE_TIMEOUT * 10; i++) {
|
|
|
|
DELAY(10);
|
|
|
|
if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (i == BGE_TIMEOUT) {
|
2005-12-23 02:04:41 +00:00
|
|
|
device_printf(sc->bge_dev, "EEPROM read timed out\n");
|
2006-06-07 21:03:20 +00:00
|
|
|
return (1);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Get result. */
|
|
|
|
byte = CSR_READ_4(sc, BGE_EE_DATA);
|
|
|
|
|
2004-10-30 14:54:51 +00:00
|
|
|
*dest = (byte >> ((addr % 4) * 8)) & 0xFF;
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
return (0);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Read a sequence of bytes from the EEPROM.
|
|
|
|
*/
|
|
|
|
static int
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
2006-06-07 21:03:20 +00:00
|
|
|
int i, error = 0;
|
|
|
|
uint8_t byte = 0;
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
for (i = 0; i < cnt; i++) {
|
2006-06-07 21:03:20 +00:00
|
|
|
error = bge_eeprom_getbyte(sc, off + i, &byte);
|
|
|
|
if (error)
|
2001-09-27 23:55:28 +00:00
|
|
|
break;
|
|
|
|
*(dest + i) = byte;
|
|
|
|
}
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
return (error ? 1 : 0);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_miibus_readreg(device_t dev, int phy, int reg)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
|
|
|
struct bge_softc *sc;
|
2006-06-07 21:03:20 +00:00
|
|
|
uint32_t val, autopoll;
|
2001-09-27 23:55:28 +00:00
|
|
|
int i;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
|
2003-07-16 00:09:56 +00:00
|
|
|
/*
|
|
|
|
* Broadcom's own driver always assumes the internal
|
|
|
|
* PHY is at GMII address 1. On some chips, the PHY responds
|
|
|
|
* to accesses at all addresses, which could cause us to
|
|
|
|
* bogusly attach the PHY 32 times at probe type. Always
|
|
|
|
* restricting the lookup to address 1 is simpler than
|
|
|
|
* trying to figure out which chips revisions should be
|
|
|
|
* special-cased.
|
|
|
|
*/
|
2002-09-08 19:12:02 +00:00
|
|
|
if (phy != 1)
|
2006-06-07 21:03:20 +00:00
|
|
|
return (0);
|
2002-03-22 06:45:40 +00:00
|
|
|
|
2003-05-03 19:06:50 +00:00
|
|
|
/* Reading with autopolling on may trigger PCI errors */
|
|
|
|
autopoll = CSR_READ_4(sc, BGE_MI_MODE);
|
|
|
|
if (autopoll & BGE_MIMODE_AUTOPOLL) {
|
|
|
|
BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
|
|
|
|
DELAY(40);
|
|
|
|
}
|
|
|
|
|
2001-09-27 23:55:28 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
|
|
|
|
BGE_MIPHY(phy)|BGE_MIREG(reg));
|
|
|
|
|
|
|
|
for (i = 0; i < BGE_TIMEOUT; i++) {
|
|
|
|
val = CSR_READ_4(sc, BGE_MI_COMM);
|
|
|
|
if (!(val & BGE_MICOMM_BUSY))
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (i == BGE_TIMEOUT) {
|
2006-09-15 15:16:12 +00:00
|
|
|
device_printf(sc->bge_dev, "PHY read timed out\n");
|
2003-05-03 19:06:50 +00:00
|
|
|
val = 0;
|
|
|
|
goto done;
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
val = CSR_READ_4(sc, BGE_MI_COMM);
|
|
|
|
|
2003-05-03 19:06:50 +00:00
|
|
|
done:
|
|
|
|
if (autopoll & BGE_MIMODE_AUTOPOLL) {
|
|
|
|
BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
|
|
|
|
DELAY(40);
|
|
|
|
}
|
|
|
|
|
2001-09-27 23:55:28 +00:00
|
|
|
if (val & BGE_MICOMM_READFAIL)
|
2006-06-07 21:03:20 +00:00
|
|
|
return (0);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
return (val & 0xFFFF);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_miibus_writereg(device_t dev, int phy, int reg, int val)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
|
|
|
struct bge_softc *sc;
|
2006-06-07 21:03:20 +00:00
|
|
|
uint32_t autopoll;
|
2001-09-27 23:55:28 +00:00
|
|
|
int i;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
|
2003-05-03 19:06:50 +00:00
|
|
|
/* Reading with autopolling on may trigger PCI errors */
|
|
|
|
autopoll = CSR_READ_4(sc, BGE_MI_MODE);
|
|
|
|
if (autopoll & BGE_MIMODE_AUTOPOLL) {
|
|
|
|
BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
|
|
|
|
DELAY(40);
|
|
|
|
}
|
|
|
|
|
2001-09-27 23:55:28 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
|
|
|
|
BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
|
|
|
|
|
|
|
|
for (i = 0; i < BGE_TIMEOUT; i++) {
|
|
|
|
if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY))
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2003-05-03 19:06:50 +00:00
|
|
|
if (autopoll & BGE_MIMODE_AUTOPOLL) {
|
|
|
|
BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
|
|
|
|
DELAY(40);
|
|
|
|
}
|
|
|
|
|
2001-09-27 23:55:28 +00:00
|
|
|
if (i == BGE_TIMEOUT) {
|
2006-09-15 15:16:12 +00:00
|
|
|
device_printf(sc->bge_dev, "PHY read timed out\n");
|
2006-06-07 21:03:20 +00:00
|
|
|
return (0);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
return (0);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_miibus_statchg(device_t dev)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
|
|
|
struct bge_softc *sc;
|
|
|
|
struct mii_data *mii;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
mii = device_get_softc(sc->bge_miibus);
|
|
|
|
|
|
|
|
BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
|
2006-06-07 21:03:20 +00:00
|
|
|
if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)
|
2001-09-27 23:55:28 +00:00
|
|
|
BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
|
2006-06-07 21:03:20 +00:00
|
|
|
else
|
2001-09-27 23:55:28 +00:00
|
|
|
BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
|
2001-09-27 23:55:28 +00:00
|
|
|
BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
|
2006-06-07 21:03:20 +00:00
|
|
|
else
|
2001-09-27 23:55:28 +00:00
|
|
|
BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Intialize a standard receive ring descriptor.
|
|
|
|
*/
|
|
|
|
static int
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
2006-06-07 21:03:20 +00:00
|
|
|
struct mbuf *m_new = NULL;
|
|
|
|
struct bge_rx_bd *r;
|
|
|
|
struct bge_dmamap_arg ctx;
|
|
|
|
int error;
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
if (m == NULL) {
|
2006-01-23 15:57:02 +00:00
|
|
|
m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
|
|
|
|
if (m_new == NULL)
|
2006-06-07 21:03:20 +00:00
|
|
|
return (ENOBUFS);
|
2001-09-27 23:55:28 +00:00
|
|
|
m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
|
|
|
|
} else {
|
|
|
|
m_new = m;
|
|
|
|
m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
|
|
|
|
m_new->m_data = m_new->m_ext.ext_buf;
|
|
|
|
}
|
|
|
|
|
2006-08-23 11:32:54 +00:00
|
|
|
if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
|
2002-06-24 22:04:15 +00:00
|
|
|
m_adj(m_new, ETHER_ALIGN);
|
2001-09-27 23:55:28 +00:00
|
|
|
sc->bge_cdata.bge_rx_std_chain[i] = m_new;
|
2003-07-25 19:42:44 +00:00
|
|
|
r = &sc->bge_ldata.bge_rx_std_ring[i];
|
|
|
|
ctx.bge_maxsegs = 1;
|
|
|
|
ctx.sc = sc;
|
|
|
|
error = bus_dmamap_load(sc->bge_cdata.bge_mtag,
|
|
|
|
sc->bge_cdata.bge_rx_std_dmamap[i], mtod(m_new, void *),
|
|
|
|
m_new->m_len, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
|
|
|
|
if (error || ctx.bge_maxsegs == 0) {
|
2005-11-30 12:37:07 +00:00
|
|
|
if (m == NULL) {
|
|
|
|
sc->bge_cdata.bge_rx_std_chain[i] = NULL;
|
2003-07-25 19:42:44 +00:00
|
|
|
m_freem(m_new);
|
2005-11-30 12:37:07 +00:00
|
|
|
}
|
2006-06-07 21:03:20 +00:00
|
|
|
return (ENOMEM);
|
2003-07-25 19:42:44 +00:00
|
|
|
}
|
2005-12-15 05:48:49 +00:00
|
|
|
r->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_busaddr);
|
|
|
|
r->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_busaddr);
|
|
|
|
r->bge_flags = BGE_RXBDFLAG_END;
|
|
|
|
r->bge_len = m_new->m_len;
|
|
|
|
r->bge_idx = i;
|
2003-07-25 19:42:44 +00:00
|
|
|
|
|
|
|
bus_dmamap_sync(sc->bge_cdata.bge_mtag,
|
|
|
|
sc->bge_cdata.bge_rx_std_dmamap[i],
|
|
|
|
BUS_DMASYNC_PREREAD);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
return (0);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize a jumbo receive ring descriptor. This allocates
|
|
|
|
* a jumbo buffer from the pool managed internally by the driver.
|
|
|
|
*/
|
|
|
|
static int
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
A big rewrite of receive Jumbo frame handling. Remove the local Jumbo
cluster allocator, that wasn't MPSAFE. Instead, utilize our new generic
UMA jumbo cluster allocator. Since UMA gives us a 9k piece that is contigous
in virtual memory, but isn't contigous in physical memory we need to handle
a few segments. To deal with this we utilize Tigon chip feature - extended
RX descriptors, that can handle up to four DMA segments for one frame.
Details:
o Remove bge_alloc_jumbo_mem(), bge_free_jumbo_mem(),
bge_jalloc(), bge_jfree() functions.
o Remove SLIST heads, bge_jumbo_tag, bge_jumbo_map from softc.
o Use extended RX BDs for Jumbo receive producer ring, and
initialize it appropriately.
o New bge_newbuf_jumbo():
- Allocate an mbuf with Jumbo cluster with help of m_cljget().
- Load the cluster for DMA with help of bus_dmamap_load_mbuf_sg().
- Assert that we got 3 segments in the DMA mapping.
- Fill in these 3 segments into the extended RX descriptor.
2005-12-08 16:11:45 +00:00
|
|
|
bus_dma_segment_t segs[BGE_NSEG_JUMBO];
|
|
|
|
struct bge_extrx_bd *r;
|
2001-09-27 23:55:28 +00:00
|
|
|
struct mbuf *m_new = NULL;
|
A big rewrite of receive Jumbo frame handling. Remove the local Jumbo
cluster allocator, that wasn't MPSAFE. Instead, utilize our new generic
UMA jumbo cluster allocator. Since UMA gives us a 9k piece that is contigous
in virtual memory, but isn't contigous in physical memory we need to handle
a few segments. To deal with this we utilize Tigon chip feature - extended
RX descriptors, that can handle up to four DMA segments for one frame.
Details:
o Remove bge_alloc_jumbo_mem(), bge_free_jumbo_mem(),
bge_jalloc(), bge_jfree() functions.
o Remove SLIST heads, bge_jumbo_tag, bge_jumbo_map from softc.
o Use extended RX BDs for Jumbo receive producer ring, and
initialize it appropriately.
o New bge_newbuf_jumbo():
- Allocate an mbuf with Jumbo cluster with help of m_cljget().
- Load the cluster for DMA with help of bus_dmamap_load_mbuf_sg().
- Assert that we got 3 segments in the DMA mapping.
- Fill in these 3 segments into the extended RX descriptor.
2005-12-08 16:11:45 +00:00
|
|
|
int nsegs;
|
2003-07-25 19:42:44 +00:00
|
|
|
int error;
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
if (m == NULL) {
|
2003-02-19 05:47:46 +00:00
|
|
|
MGETHDR(m_new, M_DONTWAIT, MT_DATA);
|
A big rewrite of receive Jumbo frame handling. Remove the local Jumbo
cluster allocator, that wasn't MPSAFE. Instead, utilize our new generic
UMA jumbo cluster allocator. Since UMA gives us a 9k piece that is contigous
in virtual memory, but isn't contigous in physical memory we need to handle
a few segments. To deal with this we utilize Tigon chip feature - extended
RX descriptors, that can handle up to four DMA segments for one frame.
Details:
o Remove bge_alloc_jumbo_mem(), bge_free_jumbo_mem(),
bge_jalloc(), bge_jfree() functions.
o Remove SLIST heads, bge_jumbo_tag, bge_jumbo_map from softc.
o Use extended RX BDs for Jumbo receive producer ring, and
initialize it appropriately.
o New bge_newbuf_jumbo():
- Allocate an mbuf with Jumbo cluster with help of m_cljget().
- Load the cluster for DMA with help of bus_dmamap_load_mbuf_sg().
- Assert that we got 3 segments in the DMA mapping.
- Fill in these 3 segments into the extended RX descriptor.
2005-12-08 16:11:45 +00:00
|
|
|
if (m_new == NULL)
|
2006-06-07 21:03:20 +00:00
|
|
|
return (ENOBUFS);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
A big rewrite of receive Jumbo frame handling. Remove the local Jumbo
cluster allocator, that wasn't MPSAFE. Instead, utilize our new generic
UMA jumbo cluster allocator. Since UMA gives us a 9k piece that is contigous
in virtual memory, but isn't contigous in physical memory we need to handle
a few segments. To deal with this we utilize Tigon chip feature - extended
RX descriptors, that can handle up to four DMA segments for one frame.
Details:
o Remove bge_alloc_jumbo_mem(), bge_free_jumbo_mem(),
bge_jalloc(), bge_jfree() functions.
o Remove SLIST heads, bge_jumbo_tag, bge_jumbo_map from softc.
o Use extended RX BDs for Jumbo receive producer ring, and
initialize it appropriately.
o New bge_newbuf_jumbo():
- Allocate an mbuf with Jumbo cluster with help of m_cljget().
- Load the cluster for DMA with help of bus_dmamap_load_mbuf_sg().
- Assert that we got 3 segments in the DMA mapping.
- Fill in these 3 segments into the extended RX descriptor.
2005-12-08 16:11:45 +00:00
|
|
|
m_cljget(m_new, M_DONTWAIT, MJUM9BYTES);
|
|
|
|
if (!(m_new->m_flags & M_EXT)) {
|
2001-09-27 23:55:28 +00:00
|
|
|
m_freem(m_new);
|
2006-06-07 21:03:20 +00:00
|
|
|
return (ENOBUFS);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
A big rewrite of receive Jumbo frame handling. Remove the local Jumbo
cluster allocator, that wasn't MPSAFE. Instead, utilize our new generic
UMA jumbo cluster allocator. Since UMA gives us a 9k piece that is contigous
in virtual memory, but isn't contigous in physical memory we need to handle
a few segments. To deal with this we utilize Tigon chip feature - extended
RX descriptors, that can handle up to four DMA segments for one frame.
Details:
o Remove bge_alloc_jumbo_mem(), bge_free_jumbo_mem(),
bge_jalloc(), bge_jfree() functions.
o Remove SLIST heads, bge_jumbo_tag, bge_jumbo_map from softc.
o Use extended RX BDs for Jumbo receive producer ring, and
initialize it appropriately.
o New bge_newbuf_jumbo():
- Allocate an mbuf with Jumbo cluster with help of m_cljget().
- Load the cluster for DMA with help of bus_dmamap_load_mbuf_sg().
- Assert that we got 3 segments in the DMA mapping.
- Fill in these 3 segments into the extended RX descriptor.
2005-12-08 16:11:45 +00:00
|
|
|
m_new->m_len = m_new->m_pkthdr.len = MJUM9BYTES;
|
2001-09-27 23:55:28 +00:00
|
|
|
} else {
|
|
|
|
m_new = m;
|
A big rewrite of receive Jumbo frame handling. Remove the local Jumbo
cluster allocator, that wasn't MPSAFE. Instead, utilize our new generic
UMA jumbo cluster allocator. Since UMA gives us a 9k piece that is contigous
in virtual memory, but isn't contigous in physical memory we need to handle
a few segments. To deal with this we utilize Tigon chip feature - extended
RX descriptors, that can handle up to four DMA segments for one frame.
Details:
o Remove bge_alloc_jumbo_mem(), bge_free_jumbo_mem(),
bge_jalloc(), bge_jfree() functions.
o Remove SLIST heads, bge_jumbo_tag, bge_jumbo_map from softc.
o Use extended RX BDs for Jumbo receive producer ring, and
initialize it appropriately.
o New bge_newbuf_jumbo():
- Allocate an mbuf with Jumbo cluster with help of m_cljget().
- Load the cluster for DMA with help of bus_dmamap_load_mbuf_sg().
- Assert that we got 3 segments in the DMA mapping.
- Fill in these 3 segments into the extended RX descriptor.
2005-12-08 16:11:45 +00:00
|
|
|
m_new->m_len = m_new->m_pkthdr.len = MJUM9BYTES;
|
2001-09-27 23:55:28 +00:00
|
|
|
m_new->m_data = m_new->m_ext.ext_buf;
|
|
|
|
}
|
|
|
|
|
2006-08-23 11:32:54 +00:00
|
|
|
if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
|
2002-06-24 22:04:15 +00:00
|
|
|
m_adj(m_new, ETHER_ALIGN);
|
A big rewrite of receive Jumbo frame handling. Remove the local Jumbo
cluster allocator, that wasn't MPSAFE. Instead, utilize our new generic
UMA jumbo cluster allocator. Since UMA gives us a 9k piece that is contigous
in virtual memory, but isn't contigous in physical memory we need to handle
a few segments. To deal with this we utilize Tigon chip feature - extended
RX descriptors, that can handle up to four DMA segments for one frame.
Details:
o Remove bge_alloc_jumbo_mem(), bge_free_jumbo_mem(),
bge_jalloc(), bge_jfree() functions.
o Remove SLIST heads, bge_jumbo_tag, bge_jumbo_map from softc.
o Use extended RX BDs for Jumbo receive producer ring, and
initialize it appropriately.
o New bge_newbuf_jumbo():
- Allocate an mbuf with Jumbo cluster with help of m_cljget().
- Load the cluster for DMA with help of bus_dmamap_load_mbuf_sg().
- Assert that we got 3 segments in the DMA mapping.
- Fill in these 3 segments into the extended RX descriptor.
2005-12-08 16:11:45 +00:00
|
|
|
|
|
|
|
error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
|
|
|
|
sc->bge_cdata.bge_rx_jumbo_dmamap[i],
|
|
|
|
m_new, segs, &nsegs, BUS_DMA_NOWAIT);
|
|
|
|
if (error) {
|
|
|
|
if (m == NULL)
|
2003-07-25 19:42:44 +00:00
|
|
|
m_freem(m_new);
|
2006-06-07 21:03:20 +00:00
|
|
|
return (error);
|
2003-07-25 19:42:44 +00:00
|
|
|
}
|
A big rewrite of receive Jumbo frame handling. Remove the local Jumbo
cluster allocator, that wasn't MPSAFE. Instead, utilize our new generic
UMA jumbo cluster allocator. Since UMA gives us a 9k piece that is contigous
in virtual memory, but isn't contigous in physical memory we need to handle
a few segments. To deal with this we utilize Tigon chip feature - extended
RX descriptors, that can handle up to four DMA segments for one frame.
Details:
o Remove bge_alloc_jumbo_mem(), bge_free_jumbo_mem(),
bge_jalloc(), bge_jfree() functions.
o Remove SLIST heads, bge_jumbo_tag, bge_jumbo_map from softc.
o Use extended RX BDs for Jumbo receive producer ring, and
initialize it appropriately.
o New bge_newbuf_jumbo():
- Allocate an mbuf with Jumbo cluster with help of m_cljget().
- Load the cluster for DMA with help of bus_dmamap_load_mbuf_sg().
- Assert that we got 3 segments in the DMA mapping.
- Fill in these 3 segments into the extended RX descriptor.
2005-12-08 16:11:45 +00:00
|
|
|
sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Fill in the extended RX buffer descriptor.
|
|
|
|
*/
|
|
|
|
r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
|
2005-12-15 05:48:49 +00:00
|
|
|
r->bge_flags = BGE_RXBDFLAG_JUMBO_RING|BGE_RXBDFLAG_END;
|
|
|
|
r->bge_idx = i;
|
2006-01-18 14:31:21 +00:00
|
|
|
r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
|
|
|
|
switch (nsegs) {
|
|
|
|
case 4:
|
|
|
|
r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr);
|
|
|
|
r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr);
|
|
|
|
r->bge_len3 = segs[3].ds_len;
|
|
|
|
case 3:
|
|
|
|
r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
|
|
|
|
r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
|
|
|
|
r->bge_len2 = segs[2].ds_len;
|
|
|
|
case 2:
|
|
|
|
r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
|
|
|
|
r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
|
|
|
|
r->bge_len1 = segs[1].ds_len;
|
|
|
|
case 1:
|
|
|
|
r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
|
|
|
|
r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
|
|
|
|
r->bge_len0 = segs[0].ds_len;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
panic("%s: %d segments\n", __func__, nsegs);
|
|
|
|
}
|
2003-07-25 19:42:44 +00:00
|
|
|
|
|
|
|
bus_dmamap_sync(sc->bge_cdata.bge_mtag,
|
|
|
|
sc->bge_cdata.bge_rx_jumbo_dmamap[i],
|
|
|
|
BUS_DMASYNC_PREREAD);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
A big rewrite of receive Jumbo frame handling. Remove the local Jumbo
cluster allocator, that wasn't MPSAFE. Instead, utilize our new generic
UMA jumbo cluster allocator. Since UMA gives us a 9k piece that is contigous
in virtual memory, but isn't contigous in physical memory we need to handle
a few segments. To deal with this we utilize Tigon chip feature - extended
RX descriptors, that can handle up to four DMA segments for one frame.
Details:
o Remove bge_alloc_jumbo_mem(), bge_free_jumbo_mem(),
bge_jalloc(), bge_jfree() functions.
o Remove SLIST heads, bge_jumbo_tag, bge_jumbo_map from softc.
o Use extended RX BDs for Jumbo receive producer ring, and
initialize it appropriately.
o New bge_newbuf_jumbo():
- Allocate an mbuf with Jumbo cluster with help of m_cljget().
- Load the cluster for DMA with help of bus_dmamap_load_mbuf_sg().
- Assert that we got 3 segments in the DMA mapping.
- Fill in these 3 segments into the extended RX descriptor.
2005-12-08 16:11:45 +00:00
|
|
|
return (0);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
|
|
|
|
* that's 1MB or memory, which is a lot. For now, we fill only the first
|
|
|
|
* 256 ring entries and hope that our CPU is fast enough to keep up with
|
|
|
|
* the NIC.
|
|
|
|
*/
|
|
|
|
static int
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_init_rx_ring_std(struct bge_softc *sc)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < BGE_SSLOTS; i++) {
|
|
|
|
if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
|
2006-06-07 21:03:20 +00:00
|
|
|
return (ENOBUFS);
|
2001-09-27 23:55:28 +00:00
|
|
|
};
|
|
|
|
|
2003-07-25 19:42:44 +00:00
|
|
|
bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
|
|
|
|
sc->bge_cdata.bge_rx_std_ring_map,
|
|
|
|
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
|
|
|
|
|
2001-09-27 23:55:28 +00:00
|
|
|
sc->bge_std = i - 1;
|
|
|
|
CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
return (0);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_free_rx_ring_std(struct bge_softc *sc)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
|
|
|
|
if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
|
2005-12-22 01:44:27 +00:00
|
|
|
bus_dmamap_sync(sc->bge_cdata.bge_mtag,
|
|
|
|
sc->bge_cdata.bge_rx_std_dmamap[i],
|
|
|
|
BUS_DMASYNC_POSTREAD);
|
2003-07-25 19:42:44 +00:00
|
|
|
bus_dmamap_unload(sc->bge_cdata.bge_mtag,
|
|
|
|
sc->bge_cdata.bge_rx_std_dmamap[i]);
|
2005-12-22 01:44:27 +00:00
|
|
|
m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
|
|
|
|
sc->bge_cdata.bge_rx_std_chain[i] = NULL;
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
2003-07-25 19:42:44 +00:00
|
|
|
bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
|
2001-09-27 23:55:28 +00:00
|
|
|
sizeof(struct bge_rx_bd));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_init_rx_ring_jumbo(struct bge_softc *sc)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
|
|
|
struct bge_rcb *rcb;
|
A big rewrite of receive Jumbo frame handling. Remove the local Jumbo
cluster allocator, that wasn't MPSAFE. Instead, utilize our new generic
UMA jumbo cluster allocator. Since UMA gives us a 9k piece that is contigous
in virtual memory, but isn't contigous in physical memory we need to handle
a few segments. To deal with this we utilize Tigon chip feature - extended
RX descriptors, that can handle up to four DMA segments for one frame.
Details:
o Remove bge_alloc_jumbo_mem(), bge_free_jumbo_mem(),
bge_jalloc(), bge_jfree() functions.
o Remove SLIST heads, bge_jumbo_tag, bge_jumbo_map from softc.
o Use extended RX BDs for Jumbo receive producer ring, and
initialize it appropriately.
o New bge_newbuf_jumbo():
- Allocate an mbuf with Jumbo cluster with help of m_cljget().
- Load the cluster for DMA with help of bus_dmamap_load_mbuf_sg().
- Assert that we got 3 segments in the DMA mapping.
- Fill in these 3 segments into the extended RX descriptor.
2005-12-08 16:11:45 +00:00
|
|
|
int i;
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
|
|
|
|
if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
|
2006-06-07 21:03:20 +00:00
|
|
|
return (ENOBUFS);
|
2001-09-27 23:55:28 +00:00
|
|
|
};
|
|
|
|
|
2003-07-25 19:42:44 +00:00
|
|
|
bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
|
|
|
|
sc->bge_cdata.bge_rx_jumbo_ring_map,
|
|
|
|
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
|
|
|
|
|
2001-09-27 23:55:28 +00:00
|
|
|
sc->bge_jumbo = i - 1;
|
|
|
|
|
2003-07-25 19:42:44 +00:00
|
|
|
rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
|
A big rewrite of receive Jumbo frame handling. Remove the local Jumbo
cluster allocator, that wasn't MPSAFE. Instead, utilize our new generic
UMA jumbo cluster allocator. Since UMA gives us a 9k piece that is contigous
in virtual memory, but isn't contigous in physical memory we need to handle
a few segments. To deal with this we utilize Tigon chip feature - extended
RX descriptors, that can handle up to four DMA segments for one frame.
Details:
o Remove bge_alloc_jumbo_mem(), bge_free_jumbo_mem(),
bge_jalloc(), bge_jfree() functions.
o Remove SLIST heads, bge_jumbo_tag, bge_jumbo_map from softc.
o Use extended RX BDs for Jumbo receive producer ring, and
initialize it appropriately.
o New bge_newbuf_jumbo():
- Allocate an mbuf with Jumbo cluster with help of m_cljget().
- Load the cluster for DMA with help of bus_dmamap_load_mbuf_sg().
- Assert that we got 3 segments in the DMA mapping.
- Fill in these 3 segments into the extended RX descriptor.
2005-12-08 16:11:45 +00:00
|
|
|
rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
|
|
|
|
BGE_RCB_FLAG_USE_EXT_RX_BD);
|
2003-01-06 23:46:47 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
return (0);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_free_rx_ring_jumbo(struct bge_softc *sc)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
|
|
|
|
if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
|
2005-12-22 01:44:27 +00:00
|
|
|
bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
|
|
|
|
sc->bge_cdata.bge_rx_jumbo_dmamap[i],
|
|
|
|
BUS_DMASYNC_POSTREAD);
|
2003-07-25 19:42:44 +00:00
|
|
|
bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
|
|
|
|
sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
|
2005-12-22 01:44:27 +00:00
|
|
|
m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
|
|
|
|
sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
2003-07-25 19:42:44 +00:00
|
|
|
bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
|
A big rewrite of receive Jumbo frame handling. Remove the local Jumbo
cluster allocator, that wasn't MPSAFE. Instead, utilize our new generic
UMA jumbo cluster allocator. Since UMA gives us a 9k piece that is contigous
in virtual memory, but isn't contigous in physical memory we need to handle
a few segments. To deal with this we utilize Tigon chip feature - extended
RX descriptors, that can handle up to four DMA segments for one frame.
Details:
o Remove bge_alloc_jumbo_mem(), bge_free_jumbo_mem(),
bge_jalloc(), bge_jfree() functions.
o Remove SLIST heads, bge_jumbo_tag, bge_jumbo_map from softc.
o Use extended RX BDs for Jumbo receive producer ring, and
initialize it appropriately.
o New bge_newbuf_jumbo():
- Allocate an mbuf with Jumbo cluster with help of m_cljget().
- Load the cluster for DMA with help of bus_dmamap_load_mbuf_sg().
- Assert that we got 3 segments in the DMA mapping.
- Fill in these 3 segments into the extended RX descriptor.
2005-12-08 16:11:45 +00:00
|
|
|
sizeof(struct bge_extrx_bd));
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_free_tx_ring(struct bge_softc *sc)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
2003-07-25 19:42:44 +00:00
|
|
|
if (sc->bge_ldata.bge_tx_ring == NULL)
|
2001-09-27 23:55:28 +00:00
|
|
|
return;
|
|
|
|
|
|
|
|
for (i = 0; i < BGE_TX_RING_CNT; i++) {
|
|
|
|
if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
|
2005-12-22 01:44:27 +00:00
|
|
|
bus_dmamap_sync(sc->bge_cdata.bge_mtag,
|
|
|
|
sc->bge_cdata.bge_tx_dmamap[i],
|
|
|
|
BUS_DMASYNC_POSTWRITE);
|
2003-07-25 19:42:44 +00:00
|
|
|
bus_dmamap_unload(sc->bge_cdata.bge_mtag,
|
|
|
|
sc->bge_cdata.bge_tx_dmamap[i]);
|
2005-12-22 01:44:27 +00:00
|
|
|
m_freem(sc->bge_cdata.bge_tx_chain[i]);
|
|
|
|
sc->bge_cdata.bge_tx_chain[i] = NULL;
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
2003-07-25 19:42:44 +00:00
|
|
|
bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
|
2001-09-27 23:55:28 +00:00
|
|
|
sizeof(struct bge_tx_bd));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_init_tx_ring(struct bge_softc *sc)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
|
|
|
sc->bge_txcnt = 0;
|
|
|
|
sc->bge_tx_saved_considx = 0;
|
2003-05-04 00:07:21 +00:00
|
|
|
|
2005-12-18 20:26:12 +00:00
|
|
|
/* Initialize transmit producer index for host-memory send ring. */
|
|
|
|
sc->bge_tx_prodidx = 0;
|
|
|
|
CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
|
|
|
|
|
2003-05-04 00:07:21 +00:00
|
|
|
/* 5700 b2 errata */
|
2003-05-07 21:51:13 +00:00
|
|
|
if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
|
2005-12-18 20:26:12 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
|
2003-05-04 00:07:21 +00:00
|
|
|
|
2005-12-18 20:26:12 +00:00
|
|
|
/* NIC-memory send ring not used; initialize to zero. */
|
2001-09-27 23:55:28 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
|
2003-05-04 00:07:21 +00:00
|
|
|
/* 5700 b2 errata */
|
2003-05-07 21:51:13 +00:00
|
|
|
if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
|
2003-05-04 00:07:21 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
return (0);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
2006-09-18 22:18:21 +00:00
|
|
|
static void
|
|
|
|
bge_setpromisc(struct bge_softc *sc)
|
|
|
|
{
|
|
|
|
struct ifnet *ifp;
|
|
|
|
|
|
|
|
BGE_LOCK_ASSERT(sc);
|
|
|
|
|
|
|
|
ifp = sc->bge_ifp;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable or disable promiscuous mode as needed.
|
|
|
|
* Do not strip VLAN tag when promiscuous mode is enabled.
|
|
|
|
*/
|
|
|
|
if (ifp->if_flags & IFF_PROMISC)
|
|
|
|
BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC |
|
|
|
|
BGE_RXMODE_RX_KEEP_VLAN_DIAG);
|
|
|
|
else
|
|
|
|
BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC |
|
|
|
|
BGE_RXMODE_RX_KEEP_VLAN_DIAG);
|
|
|
|
}
|
|
|
|
|
2001-09-27 23:55:28 +00:00
|
|
|
static void
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_setmulti(struct bge_softc *sc)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
|
|
|
struct ifnet *ifp;
|
|
|
|
struct ifmultiaddr *ifma;
|
2006-06-07 21:03:20 +00:00
|
|
|
uint32_t hashes[4] = { 0, 0, 0, 0 };
|
2001-09-27 23:55:28 +00:00
|
|
|
int h, i;
|
|
|
|
|
2003-11-11 17:57:03 +00:00
|
|
|
BGE_LOCK_ASSERT(sc);
|
|
|
|
|
2005-06-10 16:49:24 +00:00
|
|
|
ifp = sc->bge_ifp;
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
|
|
|
|
for (i = 0; i < 4; i++)
|
|
|
|
CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* First, zot all the existing filters. */
|
|
|
|
for (i = 0; i < 4; i++)
|
|
|
|
CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
|
|
|
|
|
|
|
|
/* Now program new ones. */
|
2005-08-03 00:18:35 +00:00
|
|
|
IF_ADDR_LOCK(ifp);
|
2001-09-27 23:55:28 +00:00
|
|
|
TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
|
|
|
|
if (ifma->ifma_addr->sa_family != AF_LINK)
|
|
|
|
continue;
|
2004-06-09 14:34:04 +00:00
|
|
|
h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
|
|
|
|
ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F;
|
2001-09-27 23:55:28 +00:00
|
|
|
hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
|
|
|
|
}
|
2005-08-03 00:18:35 +00:00
|
|
|
IF_ADDR_UNLOCK(ifp);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
for (i = 0; i < 4; i++)
|
|
|
|
CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
|
|
|
|
}
|
|
|
|
|
2006-09-09 03:36:57 +00:00
|
|
|
static void
|
|
|
|
bge_sig_pre_reset(sc, type)
|
|
|
|
struct bge_softc *sc;
|
|
|
|
int type;
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* Some chips don't like this so only do this if ASF is enabled
|
|
|
|
*/
|
|
|
|
if (sc->bge_asf_mode)
|
|
|
|
bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
|
|
|
|
|
|
|
|
if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
|
|
|
|
switch (type) {
|
|
|
|
case BGE_RESET_START:
|
|
|
|
bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
|
|
|
|
break;
|
|
|
|
case BGE_RESET_STOP:
|
|
|
|
bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
bge_sig_post_reset(sc, type)
|
|
|
|
struct bge_softc *sc;
|
|
|
|
int type;
|
|
|
|
{
|
|
|
|
if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
|
|
|
|
switch (type) {
|
|
|
|
case BGE_RESET_START:
|
|
|
|
bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001);
|
|
|
|
/* START DONE */
|
|
|
|
break;
|
|
|
|
case BGE_RESET_STOP:
|
|
|
|
bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
bge_sig_legacy(sc, type)
|
|
|
|
struct bge_softc *sc;
|
|
|
|
int type;
|
|
|
|
{
|
|
|
|
if (sc->bge_asf_mode) {
|
|
|
|
switch (type) {
|
|
|
|
case BGE_RESET_START:
|
|
|
|
bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
|
|
|
|
break;
|
|
|
|
case BGE_RESET_STOP:
|
|
|
|
bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void bge_stop_fw(struct bge_softc *);
|
|
|
|
void
|
|
|
|
bge_stop_fw(sc)
|
|
|
|
struct bge_softc *sc;
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
if (sc->bge_asf_mode) {
|
|
|
|
bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE);
|
|
|
|
CSR_WRITE_4(sc, BGE_CPU_EVENT,
|
|
|
|
CSR_READ_4(sc, BGE_CPU_EVENT) != (1 << 14));
|
|
|
|
|
|
|
|
for (i = 0; i < 100; i++ ) {
|
|
|
|
if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14)))
|
|
|
|
break;
|
|
|
|
DELAY(10);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2001-09-27 23:55:28 +00:00
|
|
|
/*
|
|
|
|
* Do endian, PCI and DMA initialization. Also check the on-board ROM
|
|
|
|
* self-test results.
|
|
|
|
*/
|
|
|
|
static int
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_chipinit(struct bge_softc *sc)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
2006-06-07 21:03:20 +00:00
|
|
|
uint32_t dma_rw_ctl;
|
|
|
|
int i;
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2006-09-09 03:36:57 +00:00
|
|
|
/* Set endianness before we access any non-PCI registers. */
|
2005-12-15 05:48:49 +00:00
|
|
|
pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Check the 'ROM failed' bit on the RX CPU to see if
|
|
|
|
* self-tests passed.
|
|
|
|
*/
|
|
|
|
if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
|
2005-12-23 02:04:41 +00:00
|
|
|
device_printf(sc->bge_dev, "RX CPU self-diagnostics failed!\n");
|
2006-06-07 21:03:20 +00:00
|
|
|
return (ENODEV);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Clear the MAC control register */
|
|
|
|
CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Clear the MAC statistics block in the NIC's
|
|
|
|
* internal memory.
|
|
|
|
*/
|
|
|
|
for (i = BGE_STATS_BLOCK;
|
2006-06-07 21:03:20 +00:00
|
|
|
i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
|
2001-09-27 23:55:28 +00:00
|
|
|
BGE_MEMWIN_WRITE(sc, i, 0);
|
|
|
|
|
|
|
|
for (i = BGE_STATUS_BLOCK;
|
2006-06-07 21:03:20 +00:00
|
|
|
i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
|
2001-09-27 23:55:28 +00:00
|
|
|
BGE_MEMWIN_WRITE(sc, i, 0);
|
|
|
|
|
|
|
|
/* Set up the PCI DMA control register. */
|
2006-08-23 11:32:54 +00:00
|
|
|
if (sc->bge_flags & BGE_FLAG_PCIE) {
|
2006-06-15 14:31:49 +00:00
|
|
|
/* PCI Express bus */
|
2004-09-24 22:24:33 +00:00
|
|
|
dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
|
|
|
|
(0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
|
|
|
|
(0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
|
2006-08-23 11:32:54 +00:00
|
|
|
} else if (sc->bge_flags & BGE_FLAG_PCIX) {
|
2002-09-22 18:27:29 +00:00
|
|
|
/* PCI-X bus */
|
2006-06-15 14:31:49 +00:00
|
|
|
if (BGE_IS_5714_FAMILY(sc)) {
|
|
|
|
dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
|
|
|
|
dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
|
|
|
|
/* XXX magic values, Broadcom-supplied Linux driver */
|
|
|
|
if (sc->bge_asicrev == BGE_ASICREV_BCM5780)
|
|
|
|
dma_rw_ctl |= (1 << 20) | (1 << 18) |
|
|
|
|
BGE_PCIDMARWCTL_ONEDMA_ATONCE;
|
|
|
|
else
|
|
|
|
dma_rw_ctl |= (1 << 20) | (1 << 18) | (1 << 15);
|
|
|
|
|
|
|
|
} else if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
|
|
|
|
/*
|
|
|
|
* The 5704 uses a different encoding of read/write
|
|
|
|
* watermarks.
|
|
|
|
*/
|
2003-05-03 22:58:45 +00:00
|
|
|
dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
|
|
|
|
(0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
|
|
|
|
(0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
|
|
|
|
else
|
|
|
|
dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
|
|
|
|
(0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
|
|
|
|
(0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
|
|
|
|
(0x0F);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
|
|
|
|
* for hardware bugs.
|
|
|
|
*/
|
2003-05-07 21:51:13 +00:00
|
|
|
if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
|
|
|
|
sc->bge_asicrev == BGE_ASICREV_BCM5704) {
|
2006-06-07 21:03:20 +00:00
|
|
|
uint32_t tmp;
|
2003-05-03 22:58:45 +00:00
|
|
|
|
|
|
|
tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
|
|
|
|
if (tmp == 0x6 || tmp == 0x7)
|
|
|
|
dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
|
|
|
|
}
|
2006-06-15 14:31:49 +00:00
|
|
|
} else
|
|
|
|
/* Conventional PCI bus */
|
|
|
|
dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
|
|
|
|
(0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
|
|
|
|
(0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
|
|
|
|
(0x0F);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2003-05-07 21:51:13 +00:00
|
|
|
if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
|
2003-07-16 00:09:56 +00:00
|
|
|
sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
|
2006-06-15 14:31:49 +00:00
|
|
|
sc->bge_asicrev == BGE_ASICREV_BCM5705)
|
2003-05-03 22:58:45 +00:00
|
|
|
dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
|
|
|
|
pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
|
|
|
|
|
2001-09-27 23:55:28 +00:00
|
|
|
/*
|
|
|
|
* Set up general mode register.
|
|
|
|
*/
|
2005-12-15 05:48:49 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
|
2001-09-27 23:55:28 +00:00
|
|
|
BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
|
2006-02-02 09:58:31 +00:00
|
|
|
BGE_MODECTL_TX_NO_PHDR_CSUM);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2006-09-09 03:36:57 +00:00
|
|
|
/*
|
|
|
|
* Tell the firmware the driver is running
|
|
|
|
*/
|
|
|
|
if (sc->bge_asf_mode & ASF_STACKUP)
|
|
|
|
BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
|
|
|
|
|
2001-09-27 23:55:28 +00:00
|
|
|
/*
|
2002-09-22 18:58:58 +00:00
|
|
|
* Disable memory write invalidate. Apparently it is not supported
|
|
|
|
* properly by these devices.
|
2001-09-27 23:55:28 +00:00
|
|
|
*/
|
2002-09-22 18:58:58 +00:00
|
|
|
PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
#ifdef __brokenalpha__
|
|
|
|
/*
|
|
|
|
* Must insure that we do not cross an 8K (bytes) boundary
|
2004-10-30 14:54:51 +00:00
|
|
|
* for DMA reads. Our highest limit is 1K bytes. This is a
|
|
|
|
* restriction on some ALPHA platforms with early revision
|
|
|
|
* 21174 PCI chipsets, such as the AlphaPC 164lx
|
2001-09-27 23:55:28 +00:00
|
|
|
*/
|
2002-09-22 19:27:07 +00:00
|
|
|
PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
|
|
|
|
BGE_PCI_READ_BNDRY_1024BYTES, 4);
|
2001-09-27 23:55:28 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
/* Set the timer prescaler (always 66Mhz) */
|
|
|
|
CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
return (0);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_blockinit(struct bge_softc *sc)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
|
|
|
struct bge_rcb *rcb;
|
2005-12-15 05:48:49 +00:00
|
|
|
bus_size_t vrcb;
|
|
|
|
bge_hostaddr taddr;
|
2001-09-27 23:55:28 +00:00
|
|
|
int i;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize the memory window pointer register so that
|
|
|
|
* we can access the first 32K of internal NIC RAM. This will
|
|
|
|
* allow us to set up the TX send ring RCBs and the RX return
|
|
|
|
* ring RCBs, plus other things which live in NIC memory.
|
|
|
|
*/
|
|
|
|
CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
|
|
|
|
|
2003-08-10 18:04:35 +00:00
|
|
|
/* Note: the BCM5704 has a smaller mbuf space than other chips. */
|
|
|
|
|
2006-06-15 14:31:49 +00:00
|
|
|
if (!(BGE_IS_5705_OR_BEYOND(sc))) {
|
2003-07-16 00:09:56 +00:00
|
|
|
/* Configure mbuf memory pool */
|
2006-08-23 11:32:54 +00:00
|
|
|
if (sc->bge_flags & BGE_FLAG_EXTRAM) {
|
2003-07-16 00:09:56 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
|
|
|
|
BGE_EXT_SSRAM);
|
2003-08-10 18:04:35 +00:00
|
|
|
if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
|
|
|
|
CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
|
|
|
|
else
|
|
|
|
CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
|
2003-07-16 00:09:56 +00:00
|
|
|
} else {
|
|
|
|
CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
|
|
|
|
BGE_BUFFPOOL_1);
|
2003-08-10 18:04:35 +00:00
|
|
|
if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
|
|
|
|
CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
|
|
|
|
else
|
|
|
|
CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
|
2003-07-16 00:09:56 +00:00
|
|
|
}
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2003-07-16 00:09:56 +00:00
|
|
|
/* Configure DMA resource pool */
|
|
|
|
CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
|
|
|
|
BGE_DMA_DESCRIPTORS);
|
|
|
|
CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
|
|
|
|
}
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
/* Configure mbuf pool watermarks */
|
2006-06-15 14:31:49 +00:00
|
|
|
if (!(BGE_IS_5705_OR_BEYOND(sc))) {
|
2003-07-16 00:09:56 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
|
|
|
|
CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
|
|
|
|
} else {
|
|
|
|
CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
|
|
|
|
CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
|
|
|
|
}
|
2003-04-26 18:26:29 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
/* Configure DMA resource watermarks */
|
|
|
|
CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
|
|
|
|
CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
|
|
|
|
|
|
|
|
/* Enable buffer manager */
|
2006-06-15 14:31:49 +00:00
|
|
|
if (!(BGE_IS_5705_OR_BEYOND(sc))) {
|
2003-07-16 00:09:56 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_BMAN_MODE,
|
|
|
|
BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2003-07-16 00:09:56 +00:00
|
|
|
/* Poll for buffer manager start indication */
|
|
|
|
for (i = 0; i < BGE_TIMEOUT; i++) {
|
|
|
|
if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
|
|
|
|
break;
|
|
|
|
DELAY(10);
|
|
|
|
}
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2003-07-16 00:09:56 +00:00
|
|
|
if (i == BGE_TIMEOUT) {
|
2005-12-23 02:04:41 +00:00
|
|
|
device_printf(sc->bge_dev,
|
|
|
|
"buffer manager failed to start\n");
|
2006-06-07 21:03:20 +00:00
|
|
|
return (ENXIO);
|
2003-07-16 00:09:56 +00:00
|
|
|
}
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Enable flow-through queues */
|
|
|
|
CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
|
|
|
|
CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
|
|
|
|
|
|
|
|
/* Wait until queue initialization is complete */
|
|
|
|
for (i = 0; i < BGE_TIMEOUT; i++) {
|
|
|
|
if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
|
|
|
|
break;
|
|
|
|
DELAY(10);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (i == BGE_TIMEOUT) {
|
2005-12-23 02:04:41 +00:00
|
|
|
device_printf(sc->bge_dev, "flow-through queue init failed\n");
|
2006-06-07 21:03:20 +00:00
|
|
|
return (ENXIO);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Initialize the standard RX ring control block */
|
2003-07-25 19:42:44 +00:00
|
|
|
rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
|
|
|
|
rcb->bge_hostaddr.bge_addr_lo =
|
|
|
|
BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
|
|
|
|
rcb->bge_hostaddr.bge_addr_hi =
|
|
|
|
BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
|
|
|
|
bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
|
|
|
|
sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
|
2006-06-15 14:31:49 +00:00
|
|
|
if (BGE_IS_5705_OR_BEYOND(sc))
|
2003-07-16 00:09:56 +00:00
|
|
|
rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
|
|
|
|
else
|
|
|
|
rcb->bge_maxlen_flags =
|
|
|
|
BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
|
2006-08-23 11:32:54 +00:00
|
|
|
if (sc->bge_flags & BGE_FLAG_EXTRAM)
|
2001-09-27 23:55:28 +00:00
|
|
|
rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS;
|
|
|
|
else
|
|
|
|
rcb->bge_nicaddr = BGE_STD_RX_RINGS;
|
2003-01-06 23:46:47 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
|
|
|
|
CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
|
2003-07-25 19:42:44 +00:00
|
|
|
|
2003-01-06 23:46:47 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
|
|
|
|
CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize the jumbo RX ring control block
|
|
|
|
* We set the 'ring disabled' bit in the flags
|
|
|
|
* field until we're actually ready to start
|
|
|
|
* using this ring (i.e. once we set the MTU
|
|
|
|
* high enough to require it).
|
|
|
|
*/
|
2006-06-15 14:31:49 +00:00
|
|
|
if (BGE_IS_JUMBO_CAPABLE(sc)) {
|
2003-07-25 19:42:44 +00:00
|
|
|
rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
|
|
|
|
|
|
|
|
rcb->bge_hostaddr.bge_addr_lo =
|
|
|
|
BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
|
|
|
|
rcb->bge_hostaddr.bge_addr_hi =
|
|
|
|
BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
|
|
|
|
bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
|
|
|
|
sc->bge_cdata.bge_rx_jumbo_ring_map,
|
|
|
|
BUS_DMASYNC_PREREAD);
|
A big rewrite of receive Jumbo frame handling. Remove the local Jumbo
cluster allocator, that wasn't MPSAFE. Instead, utilize our new generic
UMA jumbo cluster allocator. Since UMA gives us a 9k piece that is contigous
in virtual memory, but isn't contigous in physical memory we need to handle
a few segments. To deal with this we utilize Tigon chip feature - extended
RX descriptors, that can handle up to four DMA segments for one frame.
Details:
o Remove bge_alloc_jumbo_mem(), bge_free_jumbo_mem(),
bge_jalloc(), bge_jfree() functions.
o Remove SLIST heads, bge_jumbo_tag, bge_jumbo_map from softc.
o Use extended RX BDs for Jumbo receive producer ring, and
initialize it appropriately.
o New bge_newbuf_jumbo():
- Allocate an mbuf with Jumbo cluster with help of m_cljget().
- Load the cluster for DMA with help of bus_dmamap_load_mbuf_sg().
- Assert that we got 3 segments in the DMA mapping.
- Fill in these 3 segments into the extended RX descriptor.
2005-12-08 16:11:45 +00:00
|
|
|
rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
|
|
|
|
BGE_RCB_FLAG_USE_EXT_RX_BD|BGE_RCB_FLAG_RING_DISABLED);
|
2006-08-23 11:32:54 +00:00
|
|
|
if (sc->bge_flags & BGE_FLAG_EXTRAM)
|
2003-07-16 00:09:56 +00:00
|
|
|
rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS;
|
|
|
|
else
|
|
|
|
rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
|
|
|
|
CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
|
|
|
|
rcb->bge_hostaddr.bge_addr_hi);
|
|
|
|
CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
|
|
|
|
rcb->bge_hostaddr.bge_addr_lo);
|
2003-07-25 19:42:44 +00:00
|
|
|
|
2003-07-16 00:09:56 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
|
|
|
|
rcb->bge_maxlen_flags);
|
|
|
|
CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
|
|
|
|
|
|
|
|
/* Set up dummy disabled mini ring RCB */
|
2003-07-25 19:42:44 +00:00
|
|
|
rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
|
2003-07-16 00:09:56 +00:00
|
|
|
rcb->bge_maxlen_flags =
|
|
|
|
BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
|
|
|
|
CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
|
|
|
|
rcb->bge_maxlen_flags);
|
|
|
|
}
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Set the BD ring replentish thresholds. The recommended
|
|
|
|
* values are 1/8th the number of descriptors allocated to
|
|
|
|
* each ring.
|
|
|
|
*/
|
|
|
|
CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8);
|
|
|
|
CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Disable all unused send rings by setting the 'ring disabled'
|
|
|
|
* bit in the flags field of all the TX send ring control blocks.
|
|
|
|
* These are located in NIC memory.
|
|
|
|
*/
|
2005-12-15 05:48:49 +00:00
|
|
|
vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
|
2001-09-27 23:55:28 +00:00
|
|
|
for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
|
2005-12-15 05:48:49 +00:00
|
|
|
RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
|
|
|
|
BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
|
|
|
|
RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
|
|
|
|
vrcb += sizeof(struct bge_rcb);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Configure TX RCB 0 (we use only the first ring) */
|
2005-12-15 05:48:49 +00:00
|
|
|
vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
|
|
|
|
BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
|
|
|
|
RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
|
|
|
|
RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
|
|
|
|
RCB_WRITE_4(sc, vrcb, bge_nicaddr,
|
|
|
|
BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
|
2006-06-15 14:31:49 +00:00
|
|
|
if (!(BGE_IS_5705_OR_BEYOND(sc)))
|
2005-12-15 05:48:49 +00:00
|
|
|
RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
|
|
|
|
BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
/* Disable all unused RX return rings */
|
2005-12-15 05:48:49 +00:00
|
|
|
vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
|
2001-09-27 23:55:28 +00:00
|
|
|
for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
|
2005-12-15 05:48:49 +00:00
|
|
|
RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
|
|
|
|
RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
|
|
|
|
RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
|
2003-07-16 00:09:56 +00:00
|
|
|
BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
|
2005-12-15 05:48:49 +00:00
|
|
|
BGE_RCB_FLAG_RING_DISABLED));
|
|
|
|
RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
|
2001-09-27 23:55:28 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
|
2006-06-07 21:03:20 +00:00
|
|
|
(i * (sizeof(uint64_t))), 0);
|
2005-12-15 05:48:49 +00:00
|
|
|
vrcb += sizeof(struct bge_rcb);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Initialize RX ring indexes */
|
|
|
|
CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
|
|
|
|
CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
|
|
|
|
CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Set up RX return ring 0
|
|
|
|
* Note that the NIC address for RX return rings is 0x00000000.
|
|
|
|
* The return rings live entirely within the host, so the
|
|
|
|
* nicaddr field in the RCB isn't used.
|
|
|
|
*/
|
2005-12-15 05:48:49 +00:00
|
|
|
vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
|
|
|
|
BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
|
|
|
|
RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
|
|
|
|
RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
|
|
|
|
RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
|
|
|
|
RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
|
|
|
|
BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
/* Set random backoff seed for TX */
|
|
|
|
CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
|
2005-11-11 16:04:59 +00:00
|
|
|
IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
|
|
|
|
IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
|
|
|
|
IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] +
|
2001-09-27 23:55:28 +00:00
|
|
|
BGE_TX_BACKOFF_SEED_MASK);
|
|
|
|
|
|
|
|
/* Set inter-packet gap */
|
|
|
|
CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Specify which ring to use for packets that don't match
|
|
|
|
* any RX rules.
|
|
|
|
*/
|
|
|
|
CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Configure number of RX lists. One interrupt distribution
|
|
|
|
* list, sixteen active lists, one bad frames class.
|
|
|
|
*/
|
|
|
|
CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
|
|
|
|
|
|
|
|
/* Inialize RX list placement stats mask. */
|
|
|
|
CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
|
|
|
|
CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
|
|
|
|
|
|
|
|
/* Disable host coalescing until we get it set up */
|
|
|
|
CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
|
|
|
|
|
|
|
|
/* Poll to make sure it's shut down. */
|
|
|
|
for (i = 0; i < BGE_TIMEOUT; i++) {
|
|
|
|
if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
|
|
|
|
break;
|
|
|
|
DELAY(10);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (i == BGE_TIMEOUT) {
|
2005-12-23 02:04:41 +00:00
|
|
|
device_printf(sc->bge_dev,
|
|
|
|
"host coalescing engine failed to idle\n");
|
2006-06-07 21:03:20 +00:00
|
|
|
return (ENXIO);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Set up host coalescing defaults */
|
|
|
|
CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
|
|
|
|
CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
|
|
|
|
CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
|
|
|
|
CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
|
2006-06-15 14:31:49 +00:00
|
|
|
if (!(BGE_IS_5705_OR_BEYOND(sc))) {
|
2003-07-16 00:09:56 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
|
|
|
|
CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
|
|
|
|
}
|
2001-09-27 23:55:28 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
|
|
|
|
CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
|
|
|
|
|
|
|
|
/* Set up address of statistics block */
|
2006-06-15 14:31:49 +00:00
|
|
|
if (!(BGE_IS_5705_OR_BEYOND(sc))) {
|
2003-07-25 19:42:44 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
|
|
|
|
BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
|
2003-07-16 00:09:56 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
|
2003-07-25 19:42:44 +00:00
|
|
|
BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
|
2003-07-16 00:09:56 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
|
|
|
|
CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
|
|
|
|
CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
|
|
|
|
}
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
/* Set up address of status block */
|
2003-07-25 19:42:44 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
|
|
|
|
BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
|
2001-09-27 23:55:28 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
|
2003-07-25 19:42:44 +00:00
|
|
|
BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
|
|
|
|
sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
|
|
|
|
sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
/* Turn on host coalescing state machine */
|
|
|
|
CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
|
|
|
|
|
|
|
|
/* Turn on RX BD completion state machine and enable attentions */
|
|
|
|
CSR_WRITE_4(sc, BGE_RBDC_MODE,
|
|
|
|
BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
|
|
|
|
|
|
|
|
/* Turn on RX list placement state machine */
|
|
|
|
CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
|
|
|
|
|
|
|
|
/* Turn on RX list selector state machine. */
|
2006-06-15 14:31:49 +00:00
|
|
|
if (!(BGE_IS_5705_OR_BEYOND(sc)))
|
2003-07-16 00:09:56 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
/* Turn on DMA, clear stats */
|
|
|
|
CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
|
|
|
|
BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
|
|
|
|
BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
|
|
|
|
BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
|
2006-08-23 11:32:54 +00:00
|
|
|
((sc->bge_flags & BGE_FLAG_TBI) ?
|
|
|
|
BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
/* Set misc. local control, enable interrupts on attentions */
|
|
|
|
CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
|
|
|
|
|
|
|
|
#ifdef notdef
|
|
|
|
/* Assert GPIO pins for PHY reset */
|
|
|
|
BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
|
|
|
|
BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
|
|
|
|
BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
|
|
|
|
BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* Turn on DMA completion state machine */
|
2006-06-15 14:31:49 +00:00
|
|
|
if (!(BGE_IS_5705_OR_BEYOND(sc)))
|
2003-07-16 00:09:56 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
/* Turn on write DMA state machine */
|
|
|
|
CSR_WRITE_4(sc, BGE_WDMA_MODE,
|
|
|
|
BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS);
|
2004-10-30 14:54:51 +00:00
|
|
|
|
2001-09-27 23:55:28 +00:00
|
|
|
/* Turn on read DMA state machine */
|
|
|
|
CSR_WRITE_4(sc, BGE_RDMA_MODE,
|
|
|
|
BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS);
|
|
|
|
|
|
|
|
/* Turn on RX data completion state machine */
|
|
|
|
CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
|
|
|
|
|
|
|
|
/* Turn on RX BD initiator state machine */
|
|
|
|
CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
|
|
|
|
|
|
|
|
/* Turn on RX data and RX BD initiator state machine */
|
|
|
|
CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
|
|
|
|
|
|
|
|
/* Turn on Mbuf cluster free state machine */
|
2006-06-15 14:31:49 +00:00
|
|
|
if (!(BGE_IS_5705_OR_BEYOND(sc)))
|
2003-07-16 00:09:56 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
/* Turn on send BD completion state machine */
|
|
|
|
CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
|
|
|
|
|
|
|
|
/* Turn on send data completion state machine */
|
|
|
|
CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
|
|
|
|
|
|
|
|
/* Turn on send data initiator state machine */
|
|
|
|
CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
|
|
|
|
|
|
|
|
/* Turn on send BD initiator state machine */
|
|
|
|
CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
|
|
|
|
|
|
|
|
/* Turn on send BD selector state machine */
|
|
|
|
CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
|
|
|
|
|
|
|
|
CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
|
|
|
|
CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
|
|
|
|
BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
|
|
|
|
|
|
|
|
/* ack/clear link change events */
|
|
|
|
CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
|
2003-07-16 00:09:56 +00:00
|
|
|
BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
|
|
|
|
BGE_MACSTAT_LINK_CHANGED);
|
2003-07-25 19:42:44 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_MI_STS, 0);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
/* Enable PHY auto polling (for MII/GMII only) */
|
2006-08-23 11:32:54 +00:00
|
|
|
if (sc->bge_flags & BGE_FLAG_TBI) {
|
2001-09-27 23:55:28 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
|
2004-10-30 14:54:51 +00:00
|
|
|
} else {
|
2001-09-27 23:55:28 +00:00
|
|
|
BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
|
2006-01-13 08:59:40 +00:00
|
|
|
if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
|
2006-06-15 14:31:49 +00:00
|
|
|
sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
|
Try to sort out the correct way to generate async link state change
interrupts. This is a bit harder than it needs to be because there's
more than one way to generate link attentions, at least one of which
does not work on the BCM5700, but does on the 5701.
For the 5701, we can safely use the 'link changed' bit in the status
block, and we enable link change attentions in the mac event register.
For the 5700, we have to use MII interrupts, which require checking
the MAC status register rather than the status block. This requires
doing an extra register access on each interrupt which I'd prefer to
avoid, but them's the breaks. Testing with both a 3c996-T and 3c996B-T
shows that we do in fact detect the link going up and down properly
on cable insertions/disconnections.
Also, avoid twiddling the autopoll enable bit in the MI mode register
when doing a PHY read. I think this coupled with the other changes
will stop the interrupt storms Paul Saab has been harassing me about.
Manually setting the link to 100baseTX full duplex seems to work ok
for me. (I'm typing over the 3c996B-T right now.)
Lastly, teach the driver how to recognize a 3c996B-SX by checking
the hardware config word in the EEPROM in order to detect the media.
We attach 5701 fiber cards correctly now, but I haven't verified that
they send/receive packets yet since I don't have a second fiber
interface at home. (I know that fiber 5700 cards work, so I'm
keeping my fingers crossed.)
2002-04-04 06:01:31 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
|
|
|
|
BGE_EVTENB_MI_INTERRUPT);
|
|
|
|
}
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2006-01-13 08:59:40 +00:00
|
|
|
/*
|
|
|
|
* Clear any pending link state attention.
|
|
|
|
* Otherwise some link state change events may be lost until attention
|
|
|
|
* is cleared by bge_intr() -> bge_link_upd() sequence.
|
|
|
|
* It's not necessary on newer BCM chips - perhaps enabling link
|
|
|
|
* state change attentions implies clearing pending attention.
|
|
|
|
*/
|
|
|
|
CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
|
|
|
|
BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
|
|
|
|
BGE_MACSTAT_LINK_CHANGED);
|
|
|
|
|
2001-09-27 23:55:28 +00:00
|
|
|
/* Enable link state change attentions. */
|
|
|
|
BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
return (0);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
2006-06-15 14:31:49 +00:00
|
|
|
const struct bge_revision *
|
|
|
|
bge_lookup_rev(uint32_t chipid)
|
|
|
|
{
|
|
|
|
const struct bge_revision *br;
|
|
|
|
|
|
|
|
for (br = bge_revisions; br->br_name != NULL; br++) {
|
|
|
|
if (br->br_chipid == chipid)
|
|
|
|
return (br);
|
|
|
|
}
|
|
|
|
|
|
|
|
for (br = bge_majorrevs; br->br_name != NULL; br++) {
|
|
|
|
if (br->br_chipid == BGE_ASICREV(chipid))
|
|
|
|
return (br);
|
|
|
|
}
|
|
|
|
|
|
|
|
return (NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
const struct bge_vendor *
|
|
|
|
bge_lookup_vendor(uint16_t vid)
|
|
|
|
{
|
|
|
|
const struct bge_vendor *v;
|
|
|
|
|
|
|
|
for (v = bge_vendors; v->v_name != NULL; v++)
|
|
|
|
if (v->v_id == vid)
|
|
|
|
return (v);
|
|
|
|
|
|
|
|
panic("%s: unknown vendor %d", __func__, vid);
|
|
|
|
return (NULL);
|
|
|
|
}
|
|
|
|
|
2001-09-27 23:55:28 +00:00
|
|
|
/*
|
|
|
|
* Probe for a Broadcom chip. Check the PCI vendor and device IDs
|
2006-06-15 14:31:49 +00:00
|
|
|
* against our list and return its name if we find a match.
|
|
|
|
*
|
|
|
|
* Note that since the Broadcom controller contains VPD support, we
|
2001-09-27 23:55:28 +00:00
|
|
|
* can get the device name string from the controller itself instead
|
|
|
|
* of the compiled-in string. This is a little slow, but it guarantees
|
2006-06-15 14:31:49 +00:00
|
|
|
* we'll always announce the right product name. Unfortunately, this
|
|
|
|
* is possible only later in bge_attach(), when we have established
|
|
|
|
* access to EEPROM.
|
2001-09-27 23:55:28 +00:00
|
|
|
*/
|
|
|
|
static int
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_probe(device_t dev)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
2006-06-15 14:31:49 +00:00
|
|
|
struct bge_type *t = bge_devs;
|
|
|
|
struct bge_softc *sc = device_get_softc(dev);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
bzero(sc, sizeof(struct bge_softc));
|
|
|
|
sc->bge_dev = dev;
|
|
|
|
|
2006-06-15 14:31:49 +00:00
|
|
|
while(t->bge_vid != 0) {
|
2001-09-27 23:55:28 +00:00
|
|
|
if ((pci_get_vendor(dev) == t->bge_vid) &&
|
|
|
|
(pci_get_device(dev) == t->bge_did)) {
|
2006-06-15 14:31:49 +00:00
|
|
|
char buf[64];
|
|
|
|
const struct bge_revision *br;
|
|
|
|
const struct bge_vendor *v;
|
|
|
|
uint32_t id;
|
|
|
|
|
|
|
|
id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
|
|
|
|
BGE_PCIMISCCTL_ASICREV;
|
|
|
|
br = bge_lookup_rev(id);
|
|
|
|
id >>= 16;
|
|
|
|
v = bge_lookup_vendor(t->bge_vid);
|
|
|
|
if (br == NULL)
|
|
|
|
snprintf(buf, 64, "%s unknown ASIC (%#04x)",
|
|
|
|
v->v_name, id);
|
|
|
|
else
|
|
|
|
snprintf(buf, 64, "%s %s, ASIC rev. %#04x",
|
|
|
|
v->v_name, br->br_name, id);
|
|
|
|
device_set_desc_copy(dev, buf);
|
2003-08-20 04:06:00 +00:00
|
|
|
if (pci_get_subvendor(dev) == DELL_VENDORID)
|
2006-08-23 11:32:54 +00:00
|
|
|
sc->bge_flags |= BGE_FLAG_NO3LED;
|
2006-06-07 21:03:20 +00:00
|
|
|
return (0);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
t++;
|
|
|
|
}
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
return (ENXIO);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
2003-07-25 19:42:44 +00:00
|
|
|
static void
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_dma_free(struct bge_softc *sc)
|
2003-07-25 19:42:44 +00:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Destroy DMA maps for RX buffers. */
|
2003-07-25 19:42:44 +00:00
|
|
|
for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
|
|
|
|
if (sc->bge_cdata.bge_rx_std_dmamap[i])
|
|
|
|
bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
|
|
|
|
sc->bge_cdata.bge_rx_std_dmamap[i]);
|
|
|
|
}
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Destroy DMA maps for jumbo RX buffers. */
|
2003-07-25 19:42:44 +00:00
|
|
|
for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
|
|
|
|
if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
|
|
|
|
bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
|
|
|
|
sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
|
|
|
|
}
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Destroy DMA maps for TX buffers. */
|
2003-07-25 19:42:44 +00:00
|
|
|
for (i = 0; i < BGE_TX_RING_CNT; i++) {
|
|
|
|
if (sc->bge_cdata.bge_tx_dmamap[i])
|
|
|
|
bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
|
|
|
|
sc->bge_cdata.bge_tx_dmamap[i]);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (sc->bge_cdata.bge_mtag)
|
|
|
|
bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
|
|
|
|
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Destroy standard RX ring. */
|
2005-12-22 01:44:27 +00:00
|
|
|
if (sc->bge_cdata.bge_rx_std_ring_map)
|
2003-07-25 19:42:44 +00:00
|
|
|
bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
|
|
|
|
sc->bge_cdata.bge_rx_std_ring_map);
|
2005-12-22 01:44:27 +00:00
|
|
|
if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring)
|
|
|
|
bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
|
|
|
|
sc->bge_ldata.bge_rx_std_ring,
|
2003-07-25 19:42:44 +00:00
|
|
|
sc->bge_cdata.bge_rx_std_ring_map);
|
|
|
|
|
|
|
|
if (sc->bge_cdata.bge_rx_std_ring_tag)
|
|
|
|
bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Destroy jumbo RX ring. */
|
2005-12-22 01:44:27 +00:00
|
|
|
if (sc->bge_cdata.bge_rx_jumbo_ring_map)
|
2003-07-25 19:42:44 +00:00
|
|
|
bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
|
|
|
|
sc->bge_cdata.bge_rx_jumbo_ring_map);
|
2005-12-22 01:44:27 +00:00
|
|
|
|
|
|
|
if (sc->bge_cdata.bge_rx_jumbo_ring_map &&
|
|
|
|
sc->bge_ldata.bge_rx_jumbo_ring)
|
|
|
|
bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
|
|
|
|
sc->bge_ldata.bge_rx_jumbo_ring,
|
2003-07-25 19:42:44 +00:00
|
|
|
sc->bge_cdata.bge_rx_jumbo_ring_map);
|
|
|
|
|
|
|
|
if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
|
|
|
|
bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Destroy RX return ring. */
|
2005-12-22 01:44:27 +00:00
|
|
|
if (sc->bge_cdata.bge_rx_return_ring_map)
|
2003-07-25 19:42:44 +00:00
|
|
|
bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
|
|
|
|
sc->bge_cdata.bge_rx_return_ring_map);
|
2005-12-22 01:44:27 +00:00
|
|
|
|
|
|
|
if (sc->bge_cdata.bge_rx_return_ring_map &&
|
|
|
|
sc->bge_ldata.bge_rx_return_ring)
|
|
|
|
bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
|
|
|
|
sc->bge_ldata.bge_rx_return_ring,
|
2003-07-25 19:42:44 +00:00
|
|
|
sc->bge_cdata.bge_rx_return_ring_map);
|
|
|
|
|
|
|
|
if (sc->bge_cdata.bge_rx_return_ring_tag)
|
|
|
|
bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Destroy TX ring. */
|
2005-12-22 01:44:27 +00:00
|
|
|
if (sc->bge_cdata.bge_tx_ring_map)
|
2003-07-25 19:42:44 +00:00
|
|
|
bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
|
|
|
|
sc->bge_cdata.bge_tx_ring_map);
|
2005-12-22 01:44:27 +00:00
|
|
|
|
|
|
|
if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring)
|
|
|
|
bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
|
|
|
|
sc->bge_ldata.bge_tx_ring,
|
2003-07-25 19:42:44 +00:00
|
|
|
sc->bge_cdata.bge_tx_ring_map);
|
|
|
|
|
|
|
|
if (sc->bge_cdata.bge_tx_ring_tag)
|
|
|
|
bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Destroy status block. */
|
2005-12-22 01:44:27 +00:00
|
|
|
if (sc->bge_cdata.bge_status_map)
|
2003-07-25 19:42:44 +00:00
|
|
|
bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
|
|
|
|
sc->bge_cdata.bge_status_map);
|
2005-12-22 01:44:27 +00:00
|
|
|
|
|
|
|
if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block)
|
|
|
|
bus_dmamem_free(sc->bge_cdata.bge_status_tag,
|
|
|
|
sc->bge_ldata.bge_status_block,
|
2003-07-25 19:42:44 +00:00
|
|
|
sc->bge_cdata.bge_status_map);
|
|
|
|
|
|
|
|
if (sc->bge_cdata.bge_status_tag)
|
|
|
|
bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Destroy statistics block. */
|
2005-12-22 01:44:27 +00:00
|
|
|
if (sc->bge_cdata.bge_stats_map)
|
2003-07-25 19:42:44 +00:00
|
|
|
bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
|
|
|
|
sc->bge_cdata.bge_stats_map);
|
2005-12-22 01:44:27 +00:00
|
|
|
|
|
|
|
if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats)
|
|
|
|
bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
|
|
|
|
sc->bge_ldata.bge_stats,
|
2003-07-25 19:42:44 +00:00
|
|
|
sc->bge_cdata.bge_stats_map);
|
|
|
|
|
|
|
|
if (sc->bge_cdata.bge_stats_tag)
|
|
|
|
bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Destroy the parent tag. */
|
2003-07-25 19:42:44 +00:00
|
|
|
if (sc->bge_cdata.bge_parent_tag)
|
|
|
|
bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_dma_alloc(device_t dev)
|
2003-07-25 19:42:44 +00:00
|
|
|
{
|
2006-06-07 21:03:20 +00:00
|
|
|
struct bge_dmamap_arg ctx;
|
2003-07-25 19:42:44 +00:00
|
|
|
struct bge_softc *sc;
|
A big rewrite of receive Jumbo frame handling. Remove the local Jumbo
cluster allocator, that wasn't MPSAFE. Instead, utilize our new generic
UMA jumbo cluster allocator. Since UMA gives us a 9k piece that is contigous
in virtual memory, but isn't contigous in physical memory we need to handle
a few segments. To deal with this we utilize Tigon chip feature - extended
RX descriptors, that can handle up to four DMA segments for one frame.
Details:
o Remove bge_alloc_jumbo_mem(), bge_free_jumbo_mem(),
bge_jalloc(), bge_jfree() functions.
o Remove SLIST heads, bge_jumbo_tag, bge_jumbo_map from softc.
o Use extended RX BDs for Jumbo receive producer ring, and
initialize it appropriately.
o New bge_newbuf_jumbo():
- Allocate an mbuf with Jumbo cluster with help of m_cljget().
- Load the cluster for DMA with help of bus_dmamap_load_mbuf_sg().
- Assert that we got 3 segments in the DMA mapping.
- Fill in these 3 segments into the extended RX descriptor.
2005-12-08 16:11:45 +00:00
|
|
|
int i, error;
|
2003-07-25 19:42:44 +00:00
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Allocate the parent bus DMA tag appropriate for PCI.
|
|
|
|
*/
|
2006-09-03 00:27:42 +00:00
|
|
|
error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),/* parent */
|
2006-10-19 08:03:22 +00:00
|
|
|
1, 0, /* alignment, boundary */
|
2003-07-25 19:42:44 +00:00
|
|
|
BUS_SPACE_MAXADDR, /* lowaddr */
|
2005-04-24 02:45:27 +00:00
|
|
|
BUS_SPACE_MAXADDR, /* highaddr */
|
2003-07-25 19:42:44 +00:00
|
|
|
NULL, NULL, /* filter, filterarg */
|
|
|
|
MAXBSIZE, BGE_NSEG_NEW, /* maxsize, nsegments */
|
|
|
|
BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
|
2004-11-21 04:02:36 +00:00
|
|
|
0, /* flags */
|
2003-07-25 19:42:44 +00:00
|
|
|
NULL, NULL, /* lockfunc, lockarg */
|
|
|
|
&sc->bge_cdata.bge_parent_tag);
|
|
|
|
|
2005-12-22 01:44:27 +00:00
|
|
|
if (error != 0) {
|
2005-12-23 02:04:41 +00:00
|
|
|
device_printf(sc->bge_dev,
|
|
|
|
"could not allocate parent dma tag\n");
|
2005-12-22 01:44:27 +00:00
|
|
|
return (ENOMEM);
|
|
|
|
}
|
|
|
|
|
2003-07-25 19:42:44 +00:00
|
|
|
/*
|
|
|
|
* Create tag for RX mbufs.
|
|
|
|
*/
|
2004-10-19 02:42:49 +00:00
|
|
|
error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1,
|
2003-07-25 19:42:44 +00:00
|
|
|
0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
|
A big rewrite of receive Jumbo frame handling. Remove the local Jumbo
cluster allocator, that wasn't MPSAFE. Instead, utilize our new generic
UMA jumbo cluster allocator. Since UMA gives us a 9k piece that is contigous
in virtual memory, but isn't contigous in physical memory we need to handle
a few segments. To deal with this we utilize Tigon chip feature - extended
RX descriptors, that can handle up to four DMA segments for one frame.
Details:
o Remove bge_alloc_jumbo_mem(), bge_free_jumbo_mem(),
bge_jalloc(), bge_jfree() functions.
o Remove SLIST heads, bge_jumbo_tag, bge_jumbo_map from softc.
o Use extended RX BDs for Jumbo receive producer ring, and
initialize it appropriately.
o New bge_newbuf_jumbo():
- Allocate an mbuf with Jumbo cluster with help of m_cljget().
- Load the cluster for DMA with help of bus_dmamap_load_mbuf_sg().
- Assert that we got 3 segments in the DMA mapping.
- Fill in these 3 segments into the extended RX descriptor.
2005-12-08 16:11:45 +00:00
|
|
|
NULL, MCLBYTES * BGE_NSEG_NEW, BGE_NSEG_NEW, MCLBYTES,
|
|
|
|
BUS_DMA_ALLOCNOW, NULL, NULL, &sc->bge_cdata.bge_mtag);
|
2003-07-25 19:42:44 +00:00
|
|
|
|
|
|
|
if (error) {
|
2005-12-23 02:04:41 +00:00
|
|
|
device_printf(sc->bge_dev, "could not allocate dma tag\n");
|
2003-07-25 19:42:44 +00:00
|
|
|
return (ENOMEM);
|
|
|
|
}
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Create DMA maps for RX buffers. */
|
2003-07-25 19:42:44 +00:00
|
|
|
for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
|
|
|
|
error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
|
|
|
|
&sc->bge_cdata.bge_rx_std_dmamap[i]);
|
|
|
|
if (error) {
|
2005-12-23 02:04:41 +00:00
|
|
|
device_printf(sc->bge_dev,
|
|
|
|
"can't create DMA map for RX\n");
|
2006-06-07 21:03:20 +00:00
|
|
|
return (ENOMEM);
|
2003-07-25 19:42:44 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Create DMA maps for TX buffers. */
|
2003-07-25 19:42:44 +00:00
|
|
|
for (i = 0; i < BGE_TX_RING_CNT; i++) {
|
|
|
|
error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
|
|
|
|
&sc->bge_cdata.bge_tx_dmamap[i]);
|
|
|
|
if (error) {
|
2005-12-23 02:04:41 +00:00
|
|
|
device_printf(sc->bge_dev,
|
|
|
|
"can't create DMA map for RX\n");
|
2006-06-07 21:03:20 +00:00
|
|
|
return (ENOMEM);
|
2003-07-25 19:42:44 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Create tag for standard RX ring. */
|
2003-07-25 19:42:44 +00:00
|
|
|
error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
|
|
|
|
PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
|
|
|
|
NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0,
|
|
|
|
NULL, NULL, &sc->bge_cdata.bge_rx_std_ring_tag);
|
|
|
|
|
|
|
|
if (error) {
|
2005-12-23 02:04:41 +00:00
|
|
|
device_printf(sc->bge_dev, "could not allocate dma tag\n");
|
2003-07-25 19:42:44 +00:00
|
|
|
return (ENOMEM);
|
|
|
|
}
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Allocate DMA'able memory for standard RX ring. */
|
2003-07-25 19:42:44 +00:00
|
|
|
error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag,
|
|
|
|
(void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT,
|
|
|
|
&sc->bge_cdata.bge_rx_std_ring_map);
|
2004-10-30 14:54:51 +00:00
|
|
|
if (error)
|
|
|
|
return (ENOMEM);
|
2003-07-25 19:42:44 +00:00
|
|
|
|
2004-10-30 14:54:51 +00:00
|
|
|
bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
|
2003-07-25 19:42:44 +00:00
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Load the address of the standard RX ring. */
|
2003-07-25 19:42:44 +00:00
|
|
|
ctx.bge_maxsegs = 1;
|
|
|
|
ctx.sc = sc;
|
|
|
|
|
|
|
|
error = bus_dmamap_load(sc->bge_cdata.bge_rx_std_ring_tag,
|
|
|
|
sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring,
|
|
|
|
BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
|
|
|
|
|
|
|
|
if (error)
|
|
|
|
return (ENOMEM);
|
|
|
|
|
|
|
|
sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr;
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Create tags for jumbo mbufs. */
|
2006-06-15 14:31:49 +00:00
|
|
|
if (BGE_IS_JUMBO_CAPABLE(sc)) {
|
2003-07-25 19:42:44 +00:00
|
|
|
error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
|
2004-10-19 02:42:49 +00:00
|
|
|
1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
|
A big rewrite of receive Jumbo frame handling. Remove the local Jumbo
cluster allocator, that wasn't MPSAFE. Instead, utilize our new generic
UMA jumbo cluster allocator. Since UMA gives us a 9k piece that is contigous
in virtual memory, but isn't contigous in physical memory we need to handle
a few segments. To deal with this we utilize Tigon chip feature - extended
RX descriptors, that can handle up to four DMA segments for one frame.
Details:
o Remove bge_alloc_jumbo_mem(), bge_free_jumbo_mem(),
bge_jalloc(), bge_jfree() functions.
o Remove SLIST heads, bge_jumbo_tag, bge_jumbo_map from softc.
o Use extended RX BDs for Jumbo receive producer ring, and
initialize it appropriately.
o New bge_newbuf_jumbo():
- Allocate an mbuf with Jumbo cluster with help of m_cljget().
- Load the cluster for DMA with help of bus_dmamap_load_mbuf_sg().
- Assert that we got 3 segments in the DMA mapping.
- Fill in these 3 segments into the extended RX descriptor.
2005-12-08 16:11:45 +00:00
|
|
|
NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
|
|
|
|
0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
|
2003-07-25 19:42:44 +00:00
|
|
|
if (error) {
|
2005-12-23 02:04:41 +00:00
|
|
|
device_printf(sc->bge_dev,
|
2006-06-07 21:03:20 +00:00
|
|
|
"could not allocate jumbo dma tag\n");
|
2003-07-25 19:42:44 +00:00
|
|
|
return (ENOMEM);
|
|
|
|
}
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Create tag for jumbo RX ring. */
|
2003-07-25 19:42:44 +00:00
|
|
|
error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
|
|
|
|
PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
|
|
|
|
NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0,
|
|
|
|
NULL, NULL, &sc->bge_cdata.bge_rx_jumbo_ring_tag);
|
|
|
|
|
|
|
|
if (error) {
|
2005-12-23 02:04:41 +00:00
|
|
|
device_printf(sc->bge_dev,
|
2006-06-07 21:03:20 +00:00
|
|
|
"could not allocate jumbo ring dma tag\n");
|
2003-07-25 19:42:44 +00:00
|
|
|
return (ENOMEM);
|
|
|
|
}
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Allocate DMA'able memory for jumbo RX ring. */
|
2003-07-25 19:42:44 +00:00
|
|
|
error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag,
|
A big rewrite of receive Jumbo frame handling. Remove the local Jumbo
cluster allocator, that wasn't MPSAFE. Instead, utilize our new generic
UMA jumbo cluster allocator. Since UMA gives us a 9k piece that is contigous
in virtual memory, but isn't contigous in physical memory we need to handle
a few segments. To deal with this we utilize Tigon chip feature - extended
RX descriptors, that can handle up to four DMA segments for one frame.
Details:
o Remove bge_alloc_jumbo_mem(), bge_free_jumbo_mem(),
bge_jalloc(), bge_jfree() functions.
o Remove SLIST heads, bge_jumbo_tag, bge_jumbo_map from softc.
o Use extended RX BDs for Jumbo receive producer ring, and
initialize it appropriately.
o New bge_newbuf_jumbo():
- Allocate an mbuf with Jumbo cluster with help of m_cljget().
- Load the cluster for DMA with help of bus_dmamap_load_mbuf_sg().
- Assert that we got 3 segments in the DMA mapping.
- Fill in these 3 segments into the extended RX descriptor.
2005-12-08 16:11:45 +00:00
|
|
|
(void **)&sc->bge_ldata.bge_rx_jumbo_ring,
|
|
|
|
BUS_DMA_NOWAIT | BUS_DMA_ZERO,
|
2003-07-25 19:42:44 +00:00
|
|
|
&sc->bge_cdata.bge_rx_jumbo_ring_map);
|
|
|
|
if (error)
|
|
|
|
return (ENOMEM);
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Load the address of the jumbo RX ring. */
|
2003-07-25 19:42:44 +00:00
|
|
|
ctx.bge_maxsegs = 1;
|
|
|
|
ctx.sc = sc;
|
|
|
|
|
|
|
|
error = bus_dmamap_load(sc->bge_cdata.bge_rx_jumbo_ring_tag,
|
|
|
|
sc->bge_cdata.bge_rx_jumbo_ring_map,
|
|
|
|
sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ,
|
|
|
|
bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
|
|
|
|
|
|
|
|
if (error)
|
|
|
|
return (ENOMEM);
|
|
|
|
|
|
|
|
sc->bge_ldata.bge_rx_jumbo_ring_paddr = ctx.bge_busaddr;
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Create DMA maps for jumbo RX buffers. */
|
2003-07-25 19:42:44 +00:00
|
|
|
for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
|
|
|
|
error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
|
|
|
|
0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
|
|
|
|
if (error) {
|
2005-12-23 02:04:41 +00:00
|
|
|
device_printf(sc->bge_dev,
|
2006-06-07 21:03:20 +00:00
|
|
|
"can't create DMA map for jumbo RX\n");
|
|
|
|
return (ENOMEM);
|
2003-07-25 19:42:44 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Create tag for RX return ring. */
|
2003-07-25 19:42:44 +00:00
|
|
|
error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
|
|
|
|
PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
|
|
|
|
NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0,
|
|
|
|
NULL, NULL, &sc->bge_cdata.bge_rx_return_ring_tag);
|
|
|
|
|
|
|
|
if (error) {
|
2005-12-23 02:04:41 +00:00
|
|
|
device_printf(sc->bge_dev, "could not allocate dma tag\n");
|
2003-07-25 19:42:44 +00:00
|
|
|
return (ENOMEM);
|
|
|
|
}
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Allocate DMA'able memory for RX return ring. */
|
2003-07-25 19:42:44 +00:00
|
|
|
error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag,
|
|
|
|
(void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT,
|
|
|
|
&sc->bge_cdata.bge_rx_return_ring_map);
|
2004-10-30 14:54:51 +00:00
|
|
|
if (error)
|
|
|
|
return (ENOMEM);
|
2003-07-25 19:42:44 +00:00
|
|
|
|
2004-10-30 14:54:51 +00:00
|
|
|
bzero((char *)sc->bge_ldata.bge_rx_return_ring,
|
2003-07-25 19:42:44 +00:00
|
|
|
BGE_RX_RTN_RING_SZ(sc));
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Load the address of the RX return ring. */
|
2003-07-25 19:42:44 +00:00
|
|
|
ctx.bge_maxsegs = 1;
|
|
|
|
ctx.sc = sc;
|
|
|
|
|
|
|
|
error = bus_dmamap_load(sc->bge_cdata.bge_rx_return_ring_tag,
|
|
|
|
sc->bge_cdata.bge_rx_return_ring_map,
|
|
|
|
sc->bge_ldata.bge_rx_return_ring, BGE_RX_RTN_RING_SZ(sc),
|
|
|
|
bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
|
|
|
|
|
|
|
|
if (error)
|
|
|
|
return (ENOMEM);
|
|
|
|
|
|
|
|
sc->bge_ldata.bge_rx_return_ring_paddr = ctx.bge_busaddr;
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Create tag for TX ring. */
|
2003-07-25 19:42:44 +00:00
|
|
|
error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
|
|
|
|
PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
|
|
|
|
NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL,
|
|
|
|
&sc->bge_cdata.bge_tx_ring_tag);
|
|
|
|
|
|
|
|
if (error) {
|
2005-12-23 02:04:41 +00:00
|
|
|
device_printf(sc->bge_dev, "could not allocate dma tag\n");
|
2003-07-25 19:42:44 +00:00
|
|
|
return (ENOMEM);
|
|
|
|
}
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Allocate DMA'able memory for TX ring. */
|
2003-07-25 19:42:44 +00:00
|
|
|
error = bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag,
|
|
|
|
(void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT,
|
|
|
|
&sc->bge_cdata.bge_tx_ring_map);
|
2004-10-30 14:54:51 +00:00
|
|
|
if (error)
|
|
|
|
return (ENOMEM);
|
2003-07-25 19:42:44 +00:00
|
|
|
|
2004-10-30 14:54:51 +00:00
|
|
|
bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
|
2003-07-25 19:42:44 +00:00
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Load the address of the TX ring. */
|
2003-07-25 19:42:44 +00:00
|
|
|
ctx.bge_maxsegs = 1;
|
|
|
|
ctx.sc = sc;
|
|
|
|
|
|
|
|
error = bus_dmamap_load(sc->bge_cdata.bge_tx_ring_tag,
|
|
|
|
sc->bge_cdata.bge_tx_ring_map, sc->bge_ldata.bge_tx_ring,
|
|
|
|
BGE_TX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
|
|
|
|
|
|
|
|
if (error)
|
|
|
|
return (ENOMEM);
|
|
|
|
|
|
|
|
sc->bge_ldata.bge_tx_ring_paddr = ctx.bge_busaddr;
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Create tag for status block. */
|
2003-07-25 19:42:44 +00:00
|
|
|
error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
|
|
|
|
PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
|
|
|
|
NULL, BGE_STATUS_BLK_SZ, 1, BGE_STATUS_BLK_SZ, 0,
|
|
|
|
NULL, NULL, &sc->bge_cdata.bge_status_tag);
|
|
|
|
|
|
|
|
if (error) {
|
2005-12-23 02:04:41 +00:00
|
|
|
device_printf(sc->bge_dev, "could not allocate dma tag\n");
|
2003-07-25 19:42:44 +00:00
|
|
|
return (ENOMEM);
|
|
|
|
}
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Allocate DMA'able memory for status block. */
|
2003-07-25 19:42:44 +00:00
|
|
|
error = bus_dmamem_alloc(sc->bge_cdata.bge_status_tag,
|
|
|
|
(void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT,
|
|
|
|
&sc->bge_cdata.bge_status_map);
|
2004-10-30 14:54:51 +00:00
|
|
|
if (error)
|
|
|
|
return (ENOMEM);
|
2003-07-25 19:42:44 +00:00
|
|
|
|
2004-10-30 14:54:51 +00:00
|
|
|
bzero((char *)sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
|
2003-07-25 19:42:44 +00:00
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Load the address of the status block. */
|
2003-07-25 19:42:44 +00:00
|
|
|
ctx.sc = sc;
|
|
|
|
ctx.bge_maxsegs = 1;
|
|
|
|
|
|
|
|
error = bus_dmamap_load(sc->bge_cdata.bge_status_tag,
|
|
|
|
sc->bge_cdata.bge_status_map, sc->bge_ldata.bge_status_block,
|
|
|
|
BGE_STATUS_BLK_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
|
|
|
|
|
|
|
|
if (error)
|
|
|
|
return (ENOMEM);
|
|
|
|
|
|
|
|
sc->bge_ldata.bge_status_block_paddr = ctx.bge_busaddr;
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Create tag for statistics block. */
|
2003-07-25 19:42:44 +00:00
|
|
|
error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
|
|
|
|
PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
|
2004-10-30 14:54:51 +00:00
|
|
|
NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL,
|
2003-07-25 19:42:44 +00:00
|
|
|
&sc->bge_cdata.bge_stats_tag);
|
|
|
|
|
|
|
|
if (error) {
|
2005-12-23 02:04:41 +00:00
|
|
|
device_printf(sc->bge_dev, "could not allocate dma tag\n");
|
2003-07-25 19:42:44 +00:00
|
|
|
return (ENOMEM);
|
|
|
|
}
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Allocate DMA'able memory for statistics block. */
|
2003-07-25 19:42:44 +00:00
|
|
|
error = bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag,
|
|
|
|
(void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT,
|
|
|
|
&sc->bge_cdata.bge_stats_map);
|
2004-10-30 14:54:51 +00:00
|
|
|
if (error)
|
|
|
|
return (ENOMEM);
|
2003-07-25 19:42:44 +00:00
|
|
|
|
2004-10-30 14:54:51 +00:00
|
|
|
bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ);
|
2003-07-25 19:42:44 +00:00
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Load the address of the statstics block. */
|
2003-07-25 19:42:44 +00:00
|
|
|
ctx.sc = sc;
|
|
|
|
ctx.bge_maxsegs = 1;
|
|
|
|
|
|
|
|
error = bus_dmamap_load(sc->bge_cdata.bge_stats_tag,
|
|
|
|
sc->bge_cdata.bge_stats_map, sc->bge_ldata.bge_stats,
|
|
|
|
BGE_STATS_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
|
|
|
|
|
|
|
|
if (error)
|
|
|
|
return (ENOMEM);
|
|
|
|
|
|
|
|
sc->bge_ldata.bge_stats_paddr = ctx.bge_busaddr;
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
return (0);
|
2003-07-25 19:42:44 +00:00
|
|
|
}
|
|
|
|
|
2001-09-27 23:55:28 +00:00
|
|
|
static int
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_attach(device_t dev)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
|
|
|
struct ifnet *ifp;
|
|
|
|
struct bge_softc *sc;
|
2006-06-07 21:03:20 +00:00
|
|
|
uint32_t hwcfg = 0;
|
|
|
|
uint32_t mac_tmp = 0;
|
2005-06-10 16:49:24 +00:00
|
|
|
u_char eaddr[6];
|
2005-12-23 02:04:41 +00:00
|
|
|
int error = 0, rid;
|
2006-09-09 03:36:57 +00:00
|
|
|
int trys;
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
sc->bge_dev = dev;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Map control/status registers.
|
|
|
|
*/
|
|
|
|
pci_enable_busmaster(dev);
|
|
|
|
|
|
|
|
rid = BGE_PCI_BAR0;
|
2004-03-17 17:50:55 +00:00
|
|
|
sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
|
|
|
|
RF_ACTIVE|PCI_RF_DENSE);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
if (sc->bge_res == NULL) {
|
2005-12-23 02:04:41 +00:00
|
|
|
device_printf (sc->bge_dev, "couldn't map memory\n");
|
2001-09-27 23:55:28 +00:00
|
|
|
error = ENXIO;
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
sc->bge_btag = rman_get_bustag(sc->bge_res);
|
|
|
|
sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Allocate interrupt. */
|
2001-09-27 23:55:28 +00:00
|
|
|
rid = 0;
|
2004-10-30 14:54:51 +00:00
|
|
|
|
2004-03-17 17:50:55 +00:00
|
|
|
sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
|
2001-09-27 23:55:28 +00:00
|
|
|
RF_SHAREABLE | RF_ACTIVE);
|
|
|
|
|
|
|
|
if (sc->bge_irq == NULL) {
|
2005-12-23 02:04:41 +00:00
|
|
|
device_printf(sc->bge_dev, "couldn't map interrupt\n");
|
2001-09-27 23:55:28 +00:00
|
|
|
error = ENXIO;
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
2003-11-11 17:57:03 +00:00
|
|
|
BGE_LOCK_INIT(sc, device_get_nameunit(dev));
|
|
|
|
|
2004-09-24 22:24:33 +00:00
|
|
|
/* Save ASIC rev. */
|
|
|
|
|
|
|
|
sc->bge_chipid =
|
|
|
|
pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
|
|
|
|
BGE_PCIMISCCTL_ASICREV;
|
|
|
|
sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
|
|
|
|
sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* XXX: Broadcom Linux driver. Not in specs or eratta.
|
|
|
|
* PCI-Express?
|
|
|
|
*/
|
2006-06-15 14:31:49 +00:00
|
|
|
if (BGE_IS_5705_OR_BEYOND(sc)) {
|
2006-06-07 21:03:20 +00:00
|
|
|
uint32_t v;
|
2004-09-24 22:24:33 +00:00
|
|
|
|
|
|
|
v = pci_read_config(dev, BGE_PCI_MSI_CAPID, 4);
|
|
|
|
if (((v >> 8) & 0xff) == BGE_PCIE_CAPID_REG) {
|
|
|
|
v = pci_read_config(dev, BGE_PCIE_CAPID_REG, 4);
|
|
|
|
if ((v & 0xff) == BGE_PCIE_CAPID)
|
2006-08-23 11:32:54 +00:00
|
|
|
sc->bge_flags |= BGE_FLAG_PCIE;
|
2004-09-24 22:24:33 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-06-15 14:31:49 +00:00
|
|
|
/*
|
|
|
|
* PCI-X ?
|
|
|
|
*/
|
|
|
|
if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
|
|
|
|
BGE_PCISTATE_PCI_BUSMODE) == 0)
|
2006-08-23 11:32:54 +00:00
|
|
|
sc->bge_flags |= BGE_FLAG_PCIX;
|
2006-06-15 14:31:49 +00:00
|
|
|
|
2001-09-27 23:55:28 +00:00
|
|
|
/* Try to reset the chip. */
|
2006-09-09 03:36:57 +00:00
|
|
|
if (bge_reset(sc)) {
|
|
|
|
device_printf(sc->bge_dev, "chip reset failed\n");
|
|
|
|
bge_release_resources(sc);
|
|
|
|
error = ENXIO;
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
sc->bge_asf_mode = 0;
|
2006-09-23 18:55:49 +00:00
|
|
|
if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG)
|
|
|
|
== BGE_MAGIC_NUMBER)) {
|
2006-09-09 03:36:57 +00:00
|
|
|
if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG)
|
|
|
|
& BGE_HWCFG_ASF) {
|
|
|
|
sc->bge_asf_mode |= ASF_ENABLE;
|
|
|
|
sc->bge_asf_mode |= ASF_STACKUP;
|
|
|
|
if (sc->bge_asicrev == BGE_ASICREV_BCM5750) {
|
|
|
|
sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Try to reset the chip again the nice way. */
|
|
|
|
bge_stop_fw(sc);
|
|
|
|
bge_sig_pre_reset(sc, BGE_RESET_STOP);
|
|
|
|
if (bge_reset(sc)) {
|
|
|
|
device_printf(sc->bge_dev, "chip reset failed\n");
|
|
|
|
bge_release_resources(sc);
|
|
|
|
error = ENXIO;
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
bge_sig_legacy(sc, BGE_RESET_STOP);
|
|
|
|
bge_sig_post_reset(sc, BGE_RESET_STOP);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
if (bge_chipinit(sc)) {
|
2005-12-23 02:04:41 +00:00
|
|
|
device_printf(sc->bge_dev, "chip initialization failed\n");
|
2001-09-27 23:55:28 +00:00
|
|
|
bge_release_resources(sc);
|
|
|
|
error = ENXIO;
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Get station address from the EEPROM.
|
|
|
|
*/
|
2005-06-10 16:49:24 +00:00
|
|
|
mac_tmp = bge_readmem_ind(sc, 0x0c14);
|
|
|
|
if ((mac_tmp >> 16) == 0x484b) {
|
|
|
|
eaddr[0] = (u_char)(mac_tmp >> 8);
|
|
|
|
eaddr[1] = (u_char)mac_tmp;
|
|
|
|
mac_tmp = bge_readmem_ind(sc, 0x0c18);
|
|
|
|
eaddr[2] = (u_char)(mac_tmp >> 24);
|
|
|
|
eaddr[3] = (u_char)(mac_tmp >> 16);
|
|
|
|
eaddr[4] = (u_char)(mac_tmp >> 8);
|
|
|
|
eaddr[5] = (u_char)mac_tmp;
|
|
|
|
} else if (bge_read_eeprom(sc, eaddr,
|
2001-09-27 23:55:28 +00:00
|
|
|
BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
|
2005-12-23 02:04:41 +00:00
|
|
|
device_printf(sc->bge_dev, "failed to read station address\n");
|
2001-09-27 23:55:28 +00:00
|
|
|
bge_release_resources(sc);
|
|
|
|
error = ENXIO;
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
2003-07-25 19:42:44 +00:00
|
|
|
/* 5705 limits RX return ring to 512 entries. */
|
2006-06-15 14:31:49 +00:00
|
|
|
if (BGE_IS_5705_OR_BEYOND(sc))
|
2003-07-25 19:42:44 +00:00
|
|
|
sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
|
|
|
|
else
|
|
|
|
sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
|
|
|
|
|
|
|
|
if (bge_dma_alloc(dev)) {
|
2005-12-23 02:04:41 +00:00
|
|
|
device_printf(sc->bge_dev,
|
|
|
|
"failed to allocate DMA resources\n");
|
2003-07-25 19:42:44 +00:00
|
|
|
bge_release_resources(sc);
|
|
|
|
error = ENXIO;
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
2001-09-27 23:55:28 +00:00
|
|
|
/* Set default tuneable values. */
|
|
|
|
sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
|
|
|
|
sc->bge_rx_coal_ticks = 150;
|
|
|
|
sc->bge_tx_coal_ticks = 150;
|
|
|
|
sc->bge_rx_max_coal_bds = 64;
|
|
|
|
sc->bge_tx_max_coal_bds = 128;
|
|
|
|
|
|
|
|
/* Set up ifnet structure */
|
2005-06-10 16:49:24 +00:00
|
|
|
ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
|
|
|
|
if (ifp == NULL) {
|
2005-12-23 02:04:41 +00:00
|
|
|
device_printf(sc->bge_dev, "failed to if_alloc()\n");
|
2005-06-10 16:49:24 +00:00
|
|
|
bge_release_resources(sc);
|
|
|
|
error = ENXIO;
|
|
|
|
goto fail;
|
|
|
|
}
|
2001-09-27 23:55:28 +00:00
|
|
|
ifp->if_softc = sc;
|
2003-10-31 18:32:15 +00:00
|
|
|
if_initname(ifp, device_get_name(dev), device_get_unit(dev));
|
2001-09-27 23:55:28 +00:00
|
|
|
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
|
|
|
|
ifp->if_ioctl = bge_ioctl;
|
|
|
|
ifp->if_start = bge_start;
|
|
|
|
ifp->if_watchdog = bge_watchdog;
|
|
|
|
ifp->if_init = bge_init;
|
|
|
|
ifp->if_mtu = ETHERMTU;
|
2004-10-30 21:21:10 +00:00
|
|
|
ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1;
|
|
|
|
IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
|
|
|
|
IFQ_SET_READY(&ifp->if_snd);
|
2001-09-27 23:55:28 +00:00
|
|
|
ifp->if_hwassist = BGE_CSUM_FEATURES;
|
2005-12-22 15:14:42 +00:00
|
|
|
ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
|
2006-01-30 13:45:55 +00:00
|
|
|
IFCAP_VLAN_MTU | IFCAP_VLAN_HWCSUM;
|
2001-09-27 23:55:28 +00:00
|
|
|
ifp->if_capenable = ifp->if_capabilities;
|
2005-10-22 14:31:01 +00:00
|
|
|
#ifdef DEVICE_POLLING
|
|
|
|
ifp->if_capabilities |= IFCAP_POLLING;
|
|
|
|
#endif
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2006-06-08 10:19:16 +00:00
|
|
|
/*
|
2005-12-22 15:14:42 +00:00
|
|
|
* 5700 B0 chips do not support checksumming correctly due
|
|
|
|
* to hardware bugs.
|
|
|
|
*/
|
|
|
|
if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
|
|
|
|
ifp->if_capabilities &= ~IFCAP_HWCSUM;
|
|
|
|
ifp->if_capenable &= IFCAP_HWCSUM;
|
|
|
|
ifp->if_hwassist = 0;
|
|
|
|
}
|
|
|
|
|
Try to sort out the correct way to generate async link state change
interrupts. This is a bit harder than it needs to be because there's
more than one way to generate link attentions, at least one of which
does not work on the BCM5700, but does on the 5701.
For the 5701, we can safely use the 'link changed' bit in the status
block, and we enable link change attentions in the mac event register.
For the 5700, we have to use MII interrupts, which require checking
the MAC status register rather than the status block. This requires
doing an extra register access on each interrupt which I'd prefer to
avoid, but them's the breaks. Testing with both a 3c996-T and 3c996B-T
shows that we do in fact detect the link going up and down properly
on cable insertions/disconnections.
Also, avoid twiddling the autopoll enable bit in the MI mode register
when doing a PHY read. I think this coupled with the other changes
will stop the interrupt storms Paul Saab has been harassing me about.
Manually setting the link to 100baseTX full duplex seems to work ok
for me. (I'm typing over the 3c996B-T right now.)
Lastly, teach the driver how to recognize a 3c996B-SX by checking
the hardware config word in the EEPROM in order to detect the media.
We attach 5701 fiber cards correctly now, but I haven't verified that
they send/receive packets yet since I don't have a second fiber
interface at home. (I know that fiber 5700 cards work, so I'm
keeping my fingers crossed.)
2002-04-04 06:01:31 +00:00
|
|
|
/*
|
|
|
|
* Figure out what sort of media we have by checking the
|
2003-02-05 08:54:36 +00:00
|
|
|
* hardware config word in the first 32k of NIC internal memory,
|
|
|
|
* or fall back to examining the EEPROM if necessary.
|
|
|
|
* Note: on some BCM5700 cards, this value appears to be unset.
|
|
|
|
* If that's the case, we have to rely on identifying the NIC
|
|
|
|
* by its PCI subsystem ID, as we do below for the SysKonnect
|
|
|
|
* SK-9D41.
|
Try to sort out the correct way to generate async link state change
interrupts. This is a bit harder than it needs to be because there's
more than one way to generate link attentions, at least one of which
does not work on the BCM5700, but does on the 5701.
For the 5701, we can safely use the 'link changed' bit in the status
block, and we enable link change attentions in the mac event register.
For the 5700, we have to use MII interrupts, which require checking
the MAC status register rather than the status block. This requires
doing an extra register access on each interrupt which I'd prefer to
avoid, but them's the breaks. Testing with both a 3c996-T and 3c996B-T
shows that we do in fact detect the link going up and down properly
on cable insertions/disconnections.
Also, avoid twiddling the autopoll enable bit in the MI mode register
when doing a PHY read. I think this coupled with the other changes
will stop the interrupt storms Paul Saab has been harassing me about.
Manually setting the link to 100baseTX full duplex seems to work ok
for me. (I'm typing over the 3c996B-T right now.)
Lastly, teach the driver how to recognize a 3c996B-SX by checking
the hardware config word in the EEPROM in order to detect the media.
We attach 5701 fiber cards correctly now, but I haven't verified that
they send/receive packets yet since I don't have a second fiber
interface at home. (I know that fiber 5700 cards work, so I'm
keeping my fingers crossed.)
2002-04-04 06:01:31 +00:00
|
|
|
*/
|
2003-02-05 08:54:36 +00:00
|
|
|
if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
|
|
|
|
hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
|
|
|
|
else {
|
2005-12-22 02:03:57 +00:00
|
|
|
if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
|
|
|
|
sizeof(hwcfg))) {
|
2005-12-23 02:04:41 +00:00
|
|
|
device_printf(sc->bge_dev, "failed to read EEPROM\n");
|
2005-12-22 02:03:57 +00:00
|
|
|
bge_release_resources(sc);
|
|
|
|
error = ENXIO;
|
|
|
|
goto fail;
|
|
|
|
}
|
2003-02-05 08:54:36 +00:00
|
|
|
hwcfg = ntohl(hwcfg);
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
|
2006-08-23 11:32:54 +00:00
|
|
|
sc->bge_flags |= BGE_FLAG_TBI;
|
Try to sort out the correct way to generate async link state change
interrupts. This is a bit harder than it needs to be because there's
more than one way to generate link attentions, at least one of which
does not work on the BCM5700, but does on the 5701.
For the 5701, we can safely use the 'link changed' bit in the status
block, and we enable link change attentions in the mac event register.
For the 5700, we have to use MII interrupts, which require checking
the MAC status register rather than the status block. This requires
doing an extra register access on each interrupt which I'd prefer to
avoid, but them's the breaks. Testing with both a 3c996-T and 3c996B-T
shows that we do in fact detect the link going up and down properly
on cable insertions/disconnections.
Also, avoid twiddling the autopoll enable bit in the MI mode register
when doing a PHY read. I think this coupled with the other changes
will stop the interrupt storms Paul Saab has been harassing me about.
Manually setting the link to 100baseTX full duplex seems to work ok
for me. (I'm typing over the 3c996B-T right now.)
Lastly, teach the driver how to recognize a 3c996B-SX by checking
the hardware config word in the EEPROM in order to detect the media.
We attach 5701 fiber cards correctly now, but I haven't verified that
they send/receive packets yet since I don't have a second fiber
interface at home. (I know that fiber 5700 cards work, so I'm
keeping my fingers crossed.)
2002-04-04 06:01:31 +00:00
|
|
|
|
2001-09-27 23:55:28 +00:00
|
|
|
/* The SysKonnect SK-9D41 is a 1000baseSX card. */
|
|
|
|
if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41)
|
2006-08-23 11:32:54 +00:00
|
|
|
sc->bge_flags |= BGE_FLAG_TBI;
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2006-08-23 11:32:54 +00:00
|
|
|
if (sc->bge_flags & BGE_FLAG_TBI) {
|
2001-09-27 23:55:28 +00:00
|
|
|
ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
|
|
|
|
bge_ifmedia_upd, bge_ifmedia_sts);
|
|
|
|
ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
|
|
|
|
ifmedia_add(&sc->bge_ifmedia,
|
|
|
|
IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
|
|
|
|
ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
|
|
|
|
ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
|
2004-06-09 16:01:59 +00:00
|
|
|
sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
|
2001-09-27 23:55:28 +00:00
|
|
|
} else {
|
|
|
|
/*
|
2006-09-09 03:36:57 +00:00
|
|
|
* Do transceiver setup and tell the firmware the
|
|
|
|
* driver is down so we can try to get access the
|
|
|
|
* probe if ASF is running. Retry a couple of times
|
|
|
|
* if we get a conflict with the ASF firmware accessing
|
|
|
|
* the PHY.
|
2001-09-27 23:55:28 +00:00
|
|
|
*/
|
2006-09-09 03:36:57 +00:00
|
|
|
BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
|
|
|
|
again:
|
|
|
|
bge_asf_driver_up(sc);
|
|
|
|
|
|
|
|
trys = 0;
|
2001-09-27 23:55:28 +00:00
|
|
|
if (mii_phy_probe(dev, &sc->bge_miibus,
|
|
|
|
bge_ifmedia_upd, bge_ifmedia_sts)) {
|
2006-09-09 03:36:57 +00:00
|
|
|
if (trys++ < 4) {
|
|
|
|
device_printf(sc->bge_dev, "Try again\n");
|
|
|
|
bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR, BMCR_RESET);
|
|
|
|
goto again;
|
|
|
|
}
|
|
|
|
|
2005-12-23 02:04:41 +00:00
|
|
|
device_printf(sc->bge_dev, "MII without any PHY!\n");
|
2001-09-27 23:55:28 +00:00
|
|
|
bge_release_resources(sc);
|
|
|
|
error = ENXIO;
|
|
|
|
goto fail;
|
|
|
|
}
|
2006-09-09 03:36:57 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Now tell the firmware we are going up after probing the PHY
|
|
|
|
*/
|
|
|
|
if (sc->bge_asf_mode & ASF_STACKUP)
|
|
|
|
BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
2002-06-24 22:04:15 +00:00
|
|
|
/*
|
|
|
|
* When using the BCM5701 in PCI-X mode, data corruption has
|
|
|
|
* been observed in the first few bytes of some received packets.
|
|
|
|
* Aligning the packet buffer in memory eliminates the corruption.
|
|
|
|
* Unfortunately, this misaligns the packet payloads. On platforms
|
|
|
|
* which do not support unaligned accesses, we will realign the
|
|
|
|
* payloads by copying the received packets.
|
|
|
|
*/
|
2006-08-23 11:32:54 +00:00
|
|
|
if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
|
|
|
|
sc->bge_flags & BGE_FLAG_PCIX)
|
|
|
|
sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
|
2002-06-24 22:04:15 +00:00
|
|
|
|
2001-09-27 23:55:28 +00:00
|
|
|
/*
|
|
|
|
* Call MI attach routine.
|
|
|
|
*/
|
2005-06-10 16:49:24 +00:00
|
|
|
ether_ifattach(ifp, eaddr);
|
2003-11-11 17:57:03 +00:00
|
|
|
callout_init(&sc->bge_stat_ch, CALLOUT_MPSAFE);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2003-11-11 17:57:03 +00:00
|
|
|
/*
|
|
|
|
* Hookup IRQ last.
|
|
|
|
*/
|
|
|
|
error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE,
|
|
|
|
bge_intr, sc, &sc->bge_intrhand);
|
|
|
|
|
|
|
|
if (error) {
|
2005-06-10 16:49:24 +00:00
|
|
|
bge_detach(dev);
|
2005-12-23 02:04:41 +00:00
|
|
|
device_printf(sc->bge_dev, "couldn't set up irq\n");
|
2003-11-11 17:57:03 +00:00
|
|
|
}
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2003-11-11 17:57:03 +00:00
|
|
|
fail:
|
2006-06-07 21:03:20 +00:00
|
|
|
return (error);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_detach(device_t dev)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
|
|
|
struct bge_softc *sc;
|
|
|
|
struct ifnet *ifp;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
2005-06-10 16:49:24 +00:00
|
|
|
ifp = sc->bge_ifp;
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2005-10-22 14:31:01 +00:00
|
|
|
#ifdef DEVICE_POLLING
|
|
|
|
if (ifp->if_capenable & IFCAP_POLLING)
|
|
|
|
ether_poll_deregister(ifp);
|
|
|
|
#endif
|
|
|
|
|
2003-11-11 17:57:03 +00:00
|
|
|
BGE_LOCK(sc);
|
2001-09-27 23:55:28 +00:00
|
|
|
bge_stop(sc);
|
|
|
|
bge_reset(sc);
|
2003-11-11 17:57:03 +00:00
|
|
|
BGE_UNLOCK(sc);
|
|
|
|
|
|
|
|
ether_ifdetach(ifp);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2006-08-23 11:32:54 +00:00
|
|
|
if (sc->bge_flags & BGE_FLAG_TBI) {
|
2001-09-27 23:55:28 +00:00
|
|
|
ifmedia_removeall(&sc->bge_ifmedia);
|
|
|
|
} else {
|
|
|
|
bus_generic_detach(dev);
|
|
|
|
device_delete_child(dev, sc->bge_miibus);
|
|
|
|
}
|
|
|
|
|
|
|
|
bge_release_resources(sc);
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
return (0);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_release_resources(struct bge_softc *sc)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
2004-10-30 14:54:51 +00:00
|
|
|
device_t dev;
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2004-10-30 14:54:51 +00:00
|
|
|
dev = sc->bge_dev;
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
if (sc->bge_vpd_prodname != NULL)
|
|
|
|
free(sc->bge_vpd_prodname, M_DEVBUF);
|
|
|
|
|
|
|
|
if (sc->bge_vpd_readonly != NULL)
|
|
|
|
free(sc->bge_vpd_readonly, M_DEVBUF);
|
|
|
|
|
2004-10-30 14:54:51 +00:00
|
|
|
if (sc->bge_intrhand != NULL)
|
|
|
|
bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2004-10-30 14:54:51 +00:00
|
|
|
if (sc->bge_irq != NULL)
|
2001-09-27 23:55:28 +00:00
|
|
|
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
|
|
|
|
|
2004-10-30 14:54:51 +00:00
|
|
|
if (sc->bge_res != NULL)
|
2001-09-27 23:55:28 +00:00
|
|
|
bus_release_resource(dev, SYS_RES_MEMORY,
|
|
|
|
BGE_PCI_BAR0, sc->bge_res);
|
|
|
|
|
2005-09-16 11:25:19 +00:00
|
|
|
if (sc->bge_ifp != NULL)
|
|
|
|
if_free(sc->bge_ifp);
|
|
|
|
|
2003-07-25 19:42:44 +00:00
|
|
|
bge_dma_free(sc);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2003-11-11 17:57:03 +00:00
|
|
|
if (mtx_initialized(&sc->bge_mtx)) /* XXX */
|
|
|
|
BGE_LOCK_DESTROY(sc);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
2006-09-09 03:36:57 +00:00
|
|
|
static int
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_reset(struct bge_softc *sc)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
|
|
|
device_t dev;
|
2006-06-07 21:03:20 +00:00
|
|
|
uint32_t cachesize, command, pcistate, reset;
|
2001-09-27 23:55:28 +00:00
|
|
|
int i, val = 0;
|
|
|
|
|
|
|
|
dev = sc->bge_dev;
|
|
|
|
|
|
|
|
/* Save some important PCI state. */
|
|
|
|
cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
|
|
|
|
command = pci_read_config(dev, BGE_PCI_CMD, 4);
|
|
|
|
pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
|
|
|
|
|
|
|
|
pci_write_config(dev, BGE_PCI_MISC_CTL,
|
|
|
|
BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
|
2005-12-15 05:48:49 +00:00
|
|
|
BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2004-09-24 22:24:33 +00:00
|
|
|
reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
|
|
|
|
|
|
|
|
/* XXX: Broadcom Linux driver. */
|
2006-08-23 11:32:54 +00:00
|
|
|
if (sc->bge_flags & BGE_FLAG_PCIE) {
|
2004-09-24 22:24:33 +00:00
|
|
|
if (CSR_READ_4(sc, 0x7e2c) == 0x60) /* PCIE 1.0 */
|
|
|
|
CSR_WRITE_4(sc, 0x7e2c, 0x20);
|
|
|
|
if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
|
|
|
|
/* Prevent PCIE link training during global reset */
|
|
|
|
CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
|
|
|
|
reset |= (1<<29);
|
|
|
|
}
|
|
|
|
}
|
2004-10-30 14:54:51 +00:00
|
|
|
|
2006-09-01 22:30:56 +00:00
|
|
|
/*
|
|
|
|
* Write the magic number to the firmware mailbox at 0xb50
|
|
|
|
* so that the driver can synchronize with the firmware.
|
|
|
|
*/
|
|
|
|
bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
|
|
|
|
|
2001-09-27 23:55:28 +00:00
|
|
|
/* Issue global reset */
|
2004-09-24 22:24:33 +00:00
|
|
|
bge_writereg_ind(sc, BGE_MISC_CFG, reset);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
DELAY(1000);
|
|
|
|
|
2004-09-24 22:24:33 +00:00
|
|
|
/* XXX: Broadcom Linux driver. */
|
2006-08-23 11:32:54 +00:00
|
|
|
if (sc->bge_flags & BGE_FLAG_PCIE) {
|
2004-09-24 22:24:33 +00:00
|
|
|
if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
|
|
|
|
uint32_t v;
|
|
|
|
|
|
|
|
DELAY(500000); /* wait for link training to complete */
|
|
|
|
v = pci_read_config(dev, 0xc4, 4);
|
|
|
|
pci_write_config(dev, 0xc4, v | (1<<15), 4);
|
|
|
|
}
|
|
|
|
/* Set PCIE max payload size and clear error status. */
|
|
|
|
pci_write_config(dev, 0xd8, 0xf5000, 4);
|
|
|
|
}
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Reset some of the PCI state that got zapped by reset. */
|
2001-09-27 23:55:28 +00:00
|
|
|
pci_write_config(dev, BGE_PCI_MISC_CTL,
|
|
|
|
BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
|
2005-12-15 05:48:49 +00:00
|
|
|
BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
|
2001-09-27 23:55:28 +00:00
|
|
|
pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
|
|
|
|
pci_write_config(dev, BGE_PCI_CMD, command, 4);
|
|
|
|
bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1));
|
|
|
|
|
2004-04-06 18:28:15 +00:00
|
|
|
/* Enable memory arbiter. */
|
2006-06-15 14:31:49 +00:00
|
|
|
if (BGE_IS_5714_FAMILY(sc)) {
|
|
|
|
uint32_t val;
|
|
|
|
|
|
|
|
val = CSR_READ_4(sc, BGE_MARB_MODE);
|
|
|
|
CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
|
|
|
|
} else
|
2004-04-06 18:28:15 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
|
|
|
|
|
2001-09-27 23:55:28 +00:00
|
|
|
/*
|
|
|
|
* Poll the value location we just wrote until
|
|
|
|
* we see the 1's complement of the magic number.
|
|
|
|
* This indicates that the firmware initialization
|
|
|
|
* is complete.
|
|
|
|
*/
|
|
|
|
for (i = 0; i < BGE_TIMEOUT; i++) {
|
|
|
|
val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
|
|
|
|
if (val == ~BGE_MAGIC_NUMBER)
|
|
|
|
break;
|
|
|
|
DELAY(10);
|
|
|
|
}
|
2004-10-30 14:54:51 +00:00
|
|
|
|
2001-09-27 23:55:28 +00:00
|
|
|
if (i == BGE_TIMEOUT) {
|
2005-12-23 02:04:41 +00:00
|
|
|
device_printf(sc->bge_dev, "firmware handshake timed out\n");
|
2006-09-09 03:36:57 +00:00
|
|
|
return(0);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* XXX Wait for the value of the PCISTATE register to
|
|
|
|
* return to its original pre-reset state. This is a
|
|
|
|
* fairly good indicator of reset completion. If we don't
|
|
|
|
* wait for the reset to fully complete, trying to read
|
|
|
|
* from the device's non-PCI registers may yield garbage
|
|
|
|
* results.
|
|
|
|
*/
|
|
|
|
for (i = 0; i < BGE_TIMEOUT; i++) {
|
|
|
|
if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
|
|
|
|
break;
|
|
|
|
DELAY(10);
|
|
|
|
}
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Fix up byte swapping. */
|
2005-12-15 05:48:49 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
|
2001-09-27 23:55:28 +00:00
|
|
|
BGE_MODECTL_BYTESWAP_DATA);
|
|
|
|
|
2006-09-09 03:36:57 +00:00
|
|
|
/* Tell the ASF firmware we are up */
|
|
|
|
if (sc->bge_asf_mode & ASF_STACKUP)
|
|
|
|
BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
|
|
|
|
|
2001-09-27 23:55:28 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
|
|
|
|
|
2004-06-09 16:01:59 +00:00
|
|
|
/*
|
|
|
|
* The 5704 in TBI mode apparently needs some special
|
|
|
|
* adjustment to insure the SERDES drive level is set
|
|
|
|
* to 1.2V.
|
|
|
|
*/
|
2006-08-23 11:32:54 +00:00
|
|
|
if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
|
|
|
|
sc->bge_flags & BGE_FLAG_TBI) {
|
2004-06-09 16:01:59 +00:00
|
|
|
uint32_t serdescfg;
|
2006-08-23 11:32:54 +00:00
|
|
|
|
2004-06-09 16:01:59 +00:00
|
|
|
serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
|
|
|
|
serdescfg = (serdescfg & ~0xFFF) | 0x880;
|
|
|
|
CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
|
|
|
|
}
|
|
|
|
|
2004-09-24 22:24:33 +00:00
|
|
|
/* XXX: Broadcom Linux driver. */
|
2006-08-23 11:32:54 +00:00
|
|
|
if (sc->bge_flags & BGE_FLAG_PCIE &&
|
|
|
|
sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
|
2004-09-24 22:24:33 +00:00
|
|
|
uint32_t v;
|
|
|
|
|
|
|
|
v = CSR_READ_4(sc, 0x7c00);
|
|
|
|
CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
|
|
|
|
}
|
2001-09-27 23:55:28 +00:00
|
|
|
DELAY(10000);
|
2006-09-09 03:36:57 +00:00
|
|
|
|
|
|
|
return(0);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Frame reception handling. This is called if there's a frame
|
|
|
|
* on the receive return list.
|
|
|
|
*
|
|
|
|
* Note: we have to be able to handle two possibilities here:
|
A big rewrite of receive Jumbo frame handling. Remove the local Jumbo
cluster allocator, that wasn't MPSAFE. Instead, utilize our new generic
UMA jumbo cluster allocator. Since UMA gives us a 9k piece that is contigous
in virtual memory, but isn't contigous in physical memory we need to handle
a few segments. To deal with this we utilize Tigon chip feature - extended
RX descriptors, that can handle up to four DMA segments for one frame.
Details:
o Remove bge_alloc_jumbo_mem(), bge_free_jumbo_mem(),
bge_jalloc(), bge_jfree() functions.
o Remove SLIST heads, bge_jumbo_tag, bge_jumbo_map from softc.
o Use extended RX BDs for Jumbo receive producer ring, and
initialize it appropriately.
o New bge_newbuf_jumbo():
- Allocate an mbuf with Jumbo cluster with help of m_cljget().
- Load the cluster for DMA with help of bus_dmamap_load_mbuf_sg().
- Assert that we got 3 segments in the DMA mapping.
- Fill in these 3 segments into the extended RX descriptor.
2005-12-08 16:11:45 +00:00
|
|
|
* 1) the frame is from the jumbo receive ring
|
2001-09-27 23:55:28 +00:00
|
|
|
* 2) the frame is from the standard receive ring
|
|
|
|
*/
|
|
|
|
|
|
|
|
static void
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_rxeof(struct bge_softc *sc)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
|
|
|
struct ifnet *ifp;
|
|
|
|
int stdcnt = 0, jumbocnt = 0;
|
|
|
|
|
2003-11-11 17:57:03 +00:00
|
|
|
BGE_LOCK_ASSERT(sc);
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Nothing to do. */
|
2006-02-01 15:16:03 +00:00
|
|
|
if (sc->bge_rx_saved_considx ==
|
|
|
|
sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx)
|
|
|
|
return;
|
|
|
|
|
2005-06-10 16:49:24 +00:00
|
|
|
ifp = sc->bge_ifp;
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2003-07-25 19:42:44 +00:00
|
|
|
bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
|
2005-12-22 01:44:27 +00:00
|
|
|
sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
|
2003-07-25 19:42:44 +00:00
|
|
|
bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
|
|
|
|
sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTREAD);
|
2006-06-15 14:31:49 +00:00
|
|
|
if (BGE_IS_JUMBO_CAPABLE(sc))
|
2003-07-25 19:42:44 +00:00
|
|
|
bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
|
2006-06-15 14:31:49 +00:00
|
|
|
sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTREAD);
|
2003-07-25 19:42:44 +00:00
|
|
|
|
2001-09-27 23:55:28 +00:00
|
|
|
while(sc->bge_rx_saved_considx !=
|
2003-07-25 19:42:44 +00:00
|
|
|
sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
|
2001-09-27 23:55:28 +00:00
|
|
|
struct bge_rx_bd *cur_rx;
|
2006-06-07 21:03:20 +00:00
|
|
|
uint32_t rxidx;
|
2001-09-27 23:55:28 +00:00
|
|
|
struct mbuf *m = NULL;
|
2006-06-07 21:03:20 +00:00
|
|
|
uint16_t vlan_tag = 0;
|
2001-09-27 23:55:28 +00:00
|
|
|
int have_tag = 0;
|
|
|
|
|
2005-10-22 14:31:01 +00:00
|
|
|
#ifdef DEVICE_POLLING
|
|
|
|
if (ifp->if_capenable & IFCAP_POLLING) {
|
|
|
|
if (sc->rxcycles <= 0)
|
|
|
|
break;
|
|
|
|
sc->rxcycles--;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2001-09-27 23:55:28 +00:00
|
|
|
cur_rx =
|
2003-07-25 19:42:44 +00:00
|
|
|
&sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
rxidx = cur_rx->bge_idx;
|
2003-07-16 00:09:56 +00:00
|
|
|
BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2006-09-18 22:18:21 +00:00
|
|
|
if (!(ifp->if_flags & IFF_PROMISC) &&
|
|
|
|
(cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG)) {
|
2001-09-27 23:55:28 +00:00
|
|
|
have_tag = 1;
|
|
|
|
vlan_tag = cur_rx->bge_vlan_tag;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
|
|
|
|
BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
|
2003-07-25 19:42:44 +00:00
|
|
|
bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
|
|
|
|
sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx],
|
|
|
|
BUS_DMASYNC_POSTREAD);
|
|
|
|
bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
|
|
|
|
sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx]);
|
2001-09-27 23:55:28 +00:00
|
|
|
m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
|
|
|
|
sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
|
|
|
|
jumbocnt++;
|
|
|
|
if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
|
|
|
|
ifp->if_ierrors++;
|
|
|
|
bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
if (bge_newbuf_jumbo(sc,
|
|
|
|
sc->bge_jumbo, NULL) == ENOBUFS) {
|
|
|
|
ifp->if_ierrors++;
|
|
|
|
bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
|
2003-07-25 19:42:44 +00:00
|
|
|
bus_dmamap_sync(sc->bge_cdata.bge_mtag,
|
|
|
|
sc->bge_cdata.bge_rx_std_dmamap[rxidx],
|
|
|
|
BUS_DMASYNC_POSTREAD);
|
|
|
|
bus_dmamap_unload(sc->bge_cdata.bge_mtag,
|
|
|
|
sc->bge_cdata.bge_rx_std_dmamap[rxidx]);
|
2001-09-27 23:55:28 +00:00
|
|
|
m = sc->bge_cdata.bge_rx_std_chain[rxidx];
|
|
|
|
sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
|
|
|
|
stdcnt++;
|
|
|
|
if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
|
|
|
|
ifp->if_ierrors++;
|
|
|
|
bge_newbuf_std(sc, sc->bge_std, m);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
if (bge_newbuf_std(sc, sc->bge_std,
|
|
|
|
NULL) == ENOBUFS) {
|
|
|
|
ifp->if_ierrors++;
|
|
|
|
bge_newbuf_std(sc, sc->bge_std, m);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
ifp->if_ipackets++;
|
2005-12-22 01:44:27 +00:00
|
|
|
#ifndef __NO_STRICT_ALIGNMENT
|
2002-06-24 22:04:15 +00:00
|
|
|
/*
|
2005-12-22 01:44:27 +00:00
|
|
|
* For architectures with strict alignment we must make sure
|
|
|
|
* the payload is aligned.
|
2002-06-24 22:04:15 +00:00
|
|
|
*/
|
2006-08-23 11:32:54 +00:00
|
|
|
if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
|
2002-06-24 22:04:15 +00:00
|
|
|
bcopy(m->m_data, m->m_data + ETHER_ALIGN,
|
|
|
|
cur_rx->bge_len);
|
|
|
|
m->m_data += ETHER_ALIGN;
|
|
|
|
}
|
|
|
|
#endif
|
2003-09-23 19:54:32 +00:00
|
|
|
m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
|
2001-09-27 23:55:28 +00:00
|
|
|
m->m_pkthdr.rcvif = ifp;
|
|
|
|
|
2004-07-24 13:45:38 +00:00
|
|
|
if (ifp->if_capenable & IFCAP_RXCSUM) {
|
2006-01-21 09:54:32 +00:00
|
|
|
if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
|
|
|
|
m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
|
|
|
|
if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
|
|
|
|
m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
|
|
|
|
}
|
2005-12-22 15:14:42 +00:00
|
|
|
if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
|
|
|
|
m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
|
2001-09-27 23:55:28 +00:00
|
|
|
m->m_pkthdr.csum_data =
|
|
|
|
cur_rx->bge_tcp_udp_csum;
|
2006-02-02 09:58:31 +00:00
|
|
|
m->m_pkthdr.csum_flags |=
|
|
|
|
CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
2002-11-14 23:54:55 +00:00
|
|
|
* If we received a packet with a vlan tag,
|
|
|
|
* attach that information to the packet.
|
2001-09-27 23:55:28 +00:00
|
|
|
*/
|
2005-12-18 18:24:27 +00:00
|
|
|
if (have_tag) {
|
2006-09-17 13:33:30 +00:00
|
|
|
m->m_pkthdr.ether_vtag = vlan_tag;
|
|
|
|
m->m_flags |= M_VLANTAG;
|
2005-12-18 18:24:27 +00:00
|
|
|
}
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2003-11-11 17:57:03 +00:00
|
|
|
BGE_UNLOCK(sc);
|
2002-11-14 23:54:55 +00:00
|
|
|
(*ifp->if_input)(ifp, m);
|
2003-11-11 17:57:03 +00:00
|
|
|
BGE_LOCK(sc);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
2005-12-22 01:44:27 +00:00
|
|
|
if (stdcnt > 0)
|
|
|
|
bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
|
|
|
|
sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
|
2006-06-15 14:31:49 +00:00
|
|
|
|
|
|
|
if (BGE_IS_JUMBO_CAPABLE(sc) && jumbocnt > 0)
|
|
|
|
bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
|
|
|
|
sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
|
2003-07-25 19:42:44 +00:00
|
|
|
|
2001-09-27 23:55:28 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
|
|
|
|
if (stdcnt)
|
|
|
|
CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
|
|
|
|
if (jumbocnt)
|
|
|
|
CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_txeof(struct bge_softc *sc)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
|
|
|
struct bge_tx_bd *cur_tx = NULL;
|
|
|
|
struct ifnet *ifp;
|
|
|
|
|
2003-11-11 17:57:03 +00:00
|
|
|
BGE_LOCK_ASSERT(sc);
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Nothing to do. */
|
2006-02-01 15:16:03 +00:00
|
|
|
if (sc->bge_tx_saved_considx ==
|
|
|
|
sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx)
|
|
|
|
return;
|
|
|
|
|
2005-06-10 16:49:24 +00:00
|
|
|
ifp = sc->bge_ifp;
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2005-12-22 01:44:27 +00:00
|
|
|
bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
|
|
|
|
sc->bge_cdata.bge_tx_ring_map,
|
|
|
|
BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
|
2001-09-27 23:55:28 +00:00
|
|
|
/*
|
|
|
|
* Go through our tx ring and free mbufs for those
|
|
|
|
* frames that have been sent.
|
|
|
|
*/
|
|
|
|
while (sc->bge_tx_saved_considx !=
|
2003-07-25 19:42:44 +00:00
|
|
|
sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {
|
2006-06-07 21:03:20 +00:00
|
|
|
uint32_t idx = 0;
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
idx = sc->bge_tx_saved_considx;
|
2003-07-25 19:42:44 +00:00
|
|
|
cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
|
2001-09-27 23:55:28 +00:00
|
|
|
if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
|
|
|
|
ifp->if_opackets++;
|
|
|
|
if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
|
2005-12-22 01:44:27 +00:00
|
|
|
bus_dmamap_sync(sc->bge_cdata.bge_mtag,
|
|
|
|
sc->bge_cdata.bge_tx_dmamap[idx],
|
|
|
|
BUS_DMASYNC_POSTWRITE);
|
2003-07-25 19:42:44 +00:00
|
|
|
bus_dmamap_unload(sc->bge_cdata.bge_mtag,
|
|
|
|
sc->bge_cdata.bge_tx_dmamap[idx]);
|
2005-12-22 01:44:27 +00:00
|
|
|
m_freem(sc->bge_cdata.bge_tx_chain[idx]);
|
|
|
|
sc->bge_cdata.bge_tx_chain[idx] = NULL;
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
sc->bge_txcnt--;
|
|
|
|
BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
|
|
|
|
ifp->if_timer = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cur_tx != NULL)
|
2005-08-09 10:20:02 +00:00
|
|
|
ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
2005-10-22 14:31:01 +00:00
|
|
|
#ifdef DEVICE_POLLING
|
|
|
|
static void
|
|
|
|
bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
|
|
|
|
{
|
|
|
|
struct bge_softc *sc = ifp->if_softc;
|
2006-06-07 21:03:20 +00:00
|
|
|
uint32_t statusword;
|
2005-10-22 14:31:01 +00:00
|
|
|
|
|
|
|
BGE_LOCK(sc);
|
2006-06-07 21:03:20 +00:00
|
|
|
if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
|
|
|
|
BGE_UNLOCK(sc);
|
|
|
|
return;
|
|
|
|
}
|
2005-10-22 14:31:01 +00:00
|
|
|
|
2006-02-01 14:41:08 +00:00
|
|
|
bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
|
|
|
|
sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTREAD);
|
2005-10-22 14:31:01 +00:00
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
statusword = atomic_readandclear_32(
|
|
|
|
&sc->bge_ldata.bge_status_block->bge_status);
|
2005-10-22 14:31:01 +00:00
|
|
|
|
2006-02-01 14:41:08 +00:00
|
|
|
bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
|
|
|
|
sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREREAD);
|
2005-12-08 13:31:52 +00:00
|
|
|
|
2006-02-01 14:41:08 +00:00
|
|
|
/* Note link event. It will be processed by POLL_AND_CHECK_STATUS cmd */
|
|
|
|
if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
|
|
|
|
sc->bge_link_evt++;
|
2005-12-08 13:31:52 +00:00
|
|
|
|
2006-02-01 14:41:08 +00:00
|
|
|
if (cmd == POLL_AND_CHECK_STATUS)
|
2006-01-13 08:59:40 +00:00
|
|
|
if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
|
2006-06-15 14:31:49 +00:00
|
|
|
sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
|
2006-08-23 11:32:54 +00:00
|
|
|
sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
|
2005-12-08 13:31:52 +00:00
|
|
|
bge_link_upd(sc);
|
|
|
|
|
2006-02-01 14:41:08 +00:00
|
|
|
sc->rxcycles = count;
|
|
|
|
bge_rxeof(sc);
|
|
|
|
bge_txeof(sc);
|
|
|
|
if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
|
|
|
|
bge_start_locked(ifp);
|
2006-06-07 21:03:20 +00:00
|
|
|
|
|
|
|
BGE_UNLOCK(sc);
|
2005-10-22 14:31:01 +00:00
|
|
|
}
|
|
|
|
#endif /* DEVICE_POLLING */
|
|
|
|
|
2001-09-27 23:55:28 +00:00
|
|
|
static void
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_intr(void *xsc)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
|
|
|
struct bge_softc *sc;
|
|
|
|
struct ifnet *ifp;
|
2005-12-08 13:31:52 +00:00
|
|
|
uint32_t statusword;
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
sc = xsc;
|
2003-07-25 19:42:44 +00:00
|
|
|
|
2003-11-11 17:57:03 +00:00
|
|
|
BGE_LOCK(sc);
|
|
|
|
|
2005-12-08 13:31:52 +00:00
|
|
|
ifp = sc->bge_ifp;
|
|
|
|
|
2005-10-22 14:31:01 +00:00
|
|
|
#ifdef DEVICE_POLLING
|
|
|
|
if (ifp->if_capenable & IFCAP_POLLING) {
|
|
|
|
BGE_UNLOCK(sc);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2006-04-15 08:13:06 +00:00
|
|
|
/*
|
|
|
|
* Do the mandatory PCI flush as well as get the link status.
|
|
|
|
*/
|
|
|
|
statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
|
2003-07-25 19:42:44 +00:00
|
|
|
|
2006-04-15 08:13:06 +00:00
|
|
|
/* Ack interrupt and stop others from occuring. */
|
|
|
|
CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2006-04-15 08:13:06 +00:00
|
|
|
/* Make sure the descriptor ring indexes are coherent. */
|
|
|
|
bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
|
|
|
|
sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTREAD);
|
2006-02-01 14:26:35 +00:00
|
|
|
bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
|
|
|
|
sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREREAD);
|
|
|
|
|
2006-01-13 08:59:40 +00:00
|
|
|
if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
|
2006-06-15 14:31:49 +00:00
|
|
|
sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
|
2006-04-15 08:13:06 +00:00
|
|
|
statusword || sc->bge_link_evt)
|
2005-12-08 13:31:52 +00:00
|
|
|
bge_link_upd(sc);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2005-08-09 10:20:02 +00:00
|
|
|
if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Check RX return ring producer/consumer. */
|
2001-09-27 23:55:28 +00:00
|
|
|
bge_rxeof(sc);
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Check TX ring producer/consumer. */
|
2001-09-27 23:55:28 +00:00
|
|
|
bge_txeof(sc);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Re-enable interrupts. */
|
|
|
|
CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
|
|
|
|
|
2005-08-09 10:20:02 +00:00
|
|
|
if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
|
|
|
|
!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
|
2003-11-11 17:57:03 +00:00
|
|
|
bge_start_locked(ifp);
|
|
|
|
|
|
|
|
BGE_UNLOCK(sc);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
2006-09-09 03:36:57 +00:00
|
|
|
static void
|
|
|
|
bge_asf_driver_up(struct bge_softc *sc)
|
|
|
|
{
|
|
|
|
if (sc->bge_asf_mode & ASF_STACKUP) {
|
|
|
|
/* Send ASF heartbeat aprox. every 2s */
|
|
|
|
if (sc->bge_asf_count)
|
|
|
|
sc->bge_asf_count --;
|
|
|
|
else {
|
|
|
|
sc->bge_asf_count = 5;
|
|
|
|
bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW,
|
|
|
|
BGE_FW_DRV_ALIVE);
|
|
|
|
bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4);
|
|
|
|
bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3);
|
|
|
|
CSR_WRITE_4(sc, BGE_CPU_EVENT,
|
|
|
|
CSR_READ_4(sc, BGE_CPU_EVENT) != (1 << 14));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2001-09-27 23:55:28 +00:00
|
|
|
static void
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_tick_locked(struct bge_softc *sc)
|
2003-11-11 17:57:03 +00:00
|
|
|
{
|
2001-09-27 23:55:28 +00:00
|
|
|
struct mii_data *mii = NULL;
|
|
|
|
|
2003-11-11 17:57:03 +00:00
|
|
|
BGE_LOCK_ASSERT(sc);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2006-06-15 14:31:49 +00:00
|
|
|
if (BGE_IS_5705_OR_BEYOND(sc))
|
2003-07-16 00:09:56 +00:00
|
|
|
bge_stats_update_regs(sc);
|
|
|
|
else
|
|
|
|
bge_stats_update(sc);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2006-08-23 11:32:54 +00:00
|
|
|
if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
|
2005-12-08 13:31:52 +00:00
|
|
|
mii = device_get_softc(sc->bge_miibus);
|
2006-09-09 03:36:57 +00:00
|
|
|
/* Don't mess with the PHY in IPMI/ASF mode */
|
|
|
|
if (!((sc->bge_asf_mode & ASF_STACKUP) && (sc->bge_link)))
|
|
|
|
mii_tick(mii);
|
2006-02-01 14:26:35 +00:00
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* Since in TBI mode auto-polling can't be used we should poll
|
|
|
|
* link status manually. Here we register pending link event
|
|
|
|
* and trigger interrupt.
|
|
|
|
*/
|
|
|
|
#ifdef DEVICE_POLLING
|
2006-06-07 21:03:20 +00:00
|
|
|
/* In polling mode we poll link state in bge_poll(). */
|
2006-02-01 14:26:35 +00:00
|
|
|
if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING))
|
|
|
|
#endif
|
|
|
|
{
|
|
|
|
sc->bge_link_evt++;
|
|
|
|
BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
|
|
|
|
}
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
2006-09-09 03:36:57 +00:00
|
|
|
bge_asf_driver_up(sc);
|
|
|
|
|
2005-12-08 13:31:52 +00:00
|
|
|
callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
2003-11-11 17:57:03 +00:00
|
|
|
static void
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_tick(void *xsc)
|
2003-11-11 17:57:03 +00:00
|
|
|
{
|
|
|
|
struct bge_softc *sc;
|
|
|
|
|
|
|
|
sc = xsc;
|
|
|
|
|
|
|
|
BGE_LOCK(sc);
|
|
|
|
bge_tick_locked(sc);
|
|
|
|
BGE_UNLOCK(sc);
|
|
|
|
}
|
|
|
|
|
2003-07-16 00:09:56 +00:00
|
|
|
static void
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_stats_update_regs(struct bge_softc *sc)
|
2003-07-16 00:09:56 +00:00
|
|
|
{
|
|
|
|
struct bge_mac_stats_regs stats;
|
2006-06-07 21:03:20 +00:00
|
|
|
struct ifnet *ifp;
|
|
|
|
uint32_t *s;
|
|
|
|
u_long cnt; /* current register value */
|
2003-07-16 00:09:56 +00:00
|
|
|
int i;
|
|
|
|
|
2005-06-10 16:49:24 +00:00
|
|
|
ifp = sc->bge_ifp;
|
2003-07-16 00:09:56 +00:00
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
s = (uint32_t *)&stats;
|
2003-07-16 00:09:56 +00:00
|
|
|
for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
|
|
|
|
*s = CSR_READ_4(sc, BGE_RX_STATS + i);
|
|
|
|
s++;
|
|
|
|
}
|
|
|
|
|
2006-01-17 23:01:58 +00:00
|
|
|
cnt = stats.dot3StatsSingleCollisionFrames +
|
|
|
|
stats.dot3StatsMultipleCollisionFrames +
|
|
|
|
stats.dot3StatsExcessiveCollisions +
|
|
|
|
stats.dot3StatsLateCollisions;
|
|
|
|
ifp->if_collisions += cnt >= sc->bge_tx_collisions ?
|
|
|
|
cnt - sc->bge_tx_collisions : cnt;
|
|
|
|
sc->bge_tx_collisions = cnt;
|
2003-07-16 00:09:56 +00:00
|
|
|
}
|
|
|
|
|
2001-09-27 23:55:28 +00:00
|
|
|
static void
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_stats_update(struct bge_softc *sc)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
|
|
|
struct ifnet *ifp;
|
2005-12-15 05:48:49 +00:00
|
|
|
bus_size_t stats;
|
2006-06-07 21:03:20 +00:00
|
|
|
u_long cnt; /* current register value */
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2005-06-10 16:49:24 +00:00
|
|
|
ifp = sc->bge_ifp;
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2005-12-15 05:48:49 +00:00
|
|
|
stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
|
|
|
|
|
|
|
|
#define READ_STAT(sc, stats, stat) \
|
|
|
|
CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2006-01-17 23:01:58 +00:00
|
|
|
cnt = READ_STAT(sc, stats,
|
|
|
|
txstats.dot3StatsSingleCollisionFrames.bge_addr_lo);
|
|
|
|
cnt += READ_STAT(sc, stats,
|
|
|
|
txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo);
|
|
|
|
cnt += READ_STAT(sc, stats,
|
|
|
|
txstats.dot3StatsExcessiveCollisions.bge_addr_lo);
|
|
|
|
cnt += READ_STAT(sc, stats,
|
|
|
|
txstats.dot3StatsLateCollisions.bge_addr_lo);
|
|
|
|
ifp->if_collisions += cnt >= sc->bge_tx_collisions ?
|
|
|
|
cnt - sc->bge_tx_collisions : cnt;
|
|
|
|
sc->bge_tx_collisions = cnt;
|
|
|
|
|
|
|
|
cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
|
|
|
|
ifp->if_ierrors += cnt >= sc->bge_rx_discards ?
|
|
|
|
cnt - sc->bge_rx_discards : cnt;
|
|
|
|
sc->bge_rx_discards = cnt;
|
|
|
|
|
|
|
|
cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
|
|
|
|
ifp->if_oerrors += cnt >= sc->bge_tx_discards ?
|
|
|
|
cnt - sc->bge_tx_discards : cnt;
|
|
|
|
sc->bge_tx_discards = cnt;
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2005-12-15 05:48:49 +00:00
|
|
|
#undef READ_STAT
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
2005-12-22 15:14:42 +00:00
|
|
|
/*
|
|
|
|
* Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
|
|
|
|
* The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
|
|
|
|
* but when such padded frames employ the bge IP/TCP checksum offload,
|
|
|
|
* the hardware checksum assist gives incorrect results (possibly
|
|
|
|
* from incorporating its own padding into the UDP/TCP checksum; who knows).
|
|
|
|
* If we pad such runts with zeros, the onboard checksum comes out correct.
|
|
|
|
*/
|
|
|
|
static __inline int
|
|
|
|
bge_cksum_pad(struct mbuf *m)
|
|
|
|
{
|
|
|
|
int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len;
|
|
|
|
struct mbuf *last;
|
|
|
|
|
|
|
|
/* If there's only the packet-header and we can pad there, use it. */
|
|
|
|
if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) &&
|
|
|
|
M_TRAILINGSPACE(m) >= padlen) {
|
|
|
|
last = m;
|
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* Walk packet chain to find last mbuf. We will either
|
|
|
|
* pad there, or append a new mbuf and pad it.
|
|
|
|
*/
|
|
|
|
for (last = m; last->m_next != NULL; last = last->m_next);
|
|
|
|
if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) {
|
|
|
|
/* Allocate new empty mbuf, pad it. Compact later. */
|
|
|
|
struct mbuf *n;
|
|
|
|
|
|
|
|
MGET(n, M_DONTWAIT, MT_DATA);
|
|
|
|
if (n == NULL)
|
|
|
|
return (ENOBUFS);
|
|
|
|
n->m_len = 0;
|
|
|
|
last->m_next = n;
|
|
|
|
last = n;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Now zero the pad area, to avoid the bge cksum-assist bug. */
|
|
|
|
memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
|
|
|
|
last->m_len += padlen;
|
|
|
|
m->m_pkthdr.len += padlen;
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
2001-09-27 23:55:28 +00:00
|
|
|
/*
|
|
|
|
* Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
|
|
|
|
* pointers to descriptors.
|
|
|
|
*/
|
|
|
|
static int
|
2006-08-17 09:53:04 +00:00
|
|
|
bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
2005-12-15 09:45:53 +00:00
|
|
|
bus_dma_segment_t segs[BGE_NSEG_NEW];
|
2003-07-25 19:42:44 +00:00
|
|
|
bus_dmamap_t map;
|
2006-08-17 09:53:04 +00:00
|
|
|
struct bge_tx_bd *d;
|
|
|
|
struct mbuf *m = *m_head;
|
2005-12-15 09:45:53 +00:00
|
|
|
uint32_t idx = *txidx;
|
2006-08-17 09:53:04 +00:00
|
|
|
uint16_t csum_flags;
|
2005-12-15 09:45:53 +00:00
|
|
|
int nsegs, i, error;
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2006-08-18 13:53:53 +00:00
|
|
|
csum_flags = 0;
|
|
|
|
if (m->m_pkthdr.csum_flags) {
|
|
|
|
if (m->m_pkthdr.csum_flags & CSUM_IP)
|
|
|
|
csum_flags |= BGE_TXBDFLAG_IP_CSUM;
|
|
|
|
if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
|
|
|
|
csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
|
|
|
|
if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
|
|
|
|
(error = bge_cksum_pad(m)) != 0) {
|
|
|
|
m_freem(m);
|
|
|
|
*m_head = NULL;
|
|
|
|
return (error);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (m->m_flags & M_LASTFRAG)
|
|
|
|
csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
|
|
|
|
else if (m->m_flags & M_FRAG)
|
|
|
|
csum_flags |= BGE_TXBDFLAG_IP_FRAG;
|
|
|
|
}
|
|
|
|
|
2005-12-15 09:45:53 +00:00
|
|
|
map = sc->bge_cdata.bge_tx_dmamap[idx];
|
2006-08-17 09:53:04 +00:00
|
|
|
error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag, map, m, segs,
|
|
|
|
&nsegs, BUS_DMA_NOWAIT);
|
|
|
|
if (error == EFBIG) {
|
|
|
|
m = m_defrag(m, M_DONTWAIT);
|
|
|
|
if (m == NULL) {
|
|
|
|
m_freem(*m_head);
|
|
|
|
*m_head = NULL;
|
|
|
|
return (ENOBUFS);
|
2005-12-15 09:45:53 +00:00
|
|
|
}
|
2006-08-17 09:53:04 +00:00
|
|
|
*m_head = m;
|
|
|
|
error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag, map, m,
|
|
|
|
segs, &nsegs, BUS_DMA_NOWAIT);
|
|
|
|
if (error) {
|
|
|
|
m_freem(m);
|
|
|
|
*m_head = NULL;
|
2006-06-08 10:19:16 +00:00
|
|
|
return (error);
|
2006-08-17 09:53:04 +00:00
|
|
|
}
|
|
|
|
} else if (error != 0)
|
|
|
|
return (error);
|
2005-12-15 09:45:53 +00:00
|
|
|
|
2001-09-27 23:55:28 +00:00
|
|
|
/*
|
2003-07-25 19:42:44 +00:00
|
|
|
* Sanity check: avoid coming within 16 descriptors
|
|
|
|
* of the end of the ring.
|
2001-09-27 23:55:28 +00:00
|
|
|
*/
|
2005-12-15 09:45:53 +00:00
|
|
|
if (nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) {
|
|
|
|
bus_dmamap_unload(sc->bge_cdata.bge_mtag, map);
|
|
|
|
return (ENOBUFS);
|
|
|
|
}
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2005-12-22 01:44:27 +00:00
|
|
|
bus_dmamap_sync(sc->bge_cdata.bge_mtag, map, BUS_DMASYNC_PREWRITE);
|
|
|
|
|
2005-12-15 09:45:53 +00:00
|
|
|
for (i = 0; ; i++) {
|
|
|
|
d = &sc->bge_ldata.bge_tx_ring[idx];
|
|
|
|
d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
|
|
|
|
d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
|
|
|
|
d->bge_len = segs[i].ds_len;
|
|
|
|
d->bge_flags = csum_flags;
|
|
|
|
if (i == nsegs - 1)
|
|
|
|
break;
|
|
|
|
BGE_INC(idx, BGE_TX_RING_CNT);
|
|
|
|
}
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2005-12-15 09:45:53 +00:00
|
|
|
/* Mark the last segment as end of packet... */
|
|
|
|
d->bge_flags |= BGE_TXBDFLAG_END;
|
2006-08-17 09:53:04 +00:00
|
|
|
|
2005-12-15 09:45:53 +00:00
|
|
|
/* ... and put VLAN tag into first segment. */
|
|
|
|
d = &sc->bge_ldata.bge_tx_ring[*txidx];
|
2006-09-17 13:33:30 +00:00
|
|
|
if (m->m_flags & M_VLANTAG) {
|
2005-12-15 09:45:53 +00:00
|
|
|
d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
|
2006-09-17 13:33:30 +00:00
|
|
|
d->bge_vlan_tag = m->m_pkthdr.ether_vtag;
|
2005-12-15 09:45:53 +00:00
|
|
|
} else
|
|
|
|
d->bge_vlan_tag = 0;
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2003-07-25 19:42:44 +00:00
|
|
|
/*
|
|
|
|
* Insure that the map for this transmission
|
|
|
|
* is placed at the array index of the last descriptor
|
|
|
|
* in this chain.
|
|
|
|
*/
|
2005-12-15 09:45:53 +00:00
|
|
|
sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
|
|
|
|
sc->bge_cdata.bge_tx_dmamap[idx] = map;
|
2006-08-17 09:53:04 +00:00
|
|
|
sc->bge_cdata.bge_tx_chain[idx] = m;
|
2005-12-15 09:45:53 +00:00
|
|
|
sc->bge_txcnt += nsegs;
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2005-12-15 09:45:53 +00:00
|
|
|
BGE_INC(idx, BGE_TX_RING_CNT);
|
|
|
|
*txidx = idx;
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2005-12-15 09:45:53 +00:00
|
|
|
return (0);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Main transmit routine. To avoid having to do mbuf copies, we put pointers
|
|
|
|
* to the mbuf data regions directly in the transmit descriptors.
|
|
|
|
*/
|
|
|
|
static void
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_start_locked(struct ifnet *ifp)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
|
|
|
struct bge_softc *sc;
|
|
|
|
struct mbuf *m_head = NULL;
|
2005-12-18 20:26:12 +00:00
|
|
|
uint32_t prodidx;
|
2004-10-30 22:59:30 +00:00
|
|
|
int count = 0;
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
sc = ifp->if_softc;
|
|
|
|
|
2005-12-08 13:31:52 +00:00
|
|
|
if (!sc->bge_link || IFQ_DRV_IS_EMPTY(&ifp->if_snd))
|
2001-09-27 23:55:28 +00:00
|
|
|
return;
|
|
|
|
|
2005-12-18 20:26:12 +00:00
|
|
|
prodidx = sc->bge_tx_prodidx;
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
|
2004-10-30 21:21:10 +00:00
|
|
|
IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
|
2001-09-27 23:55:28 +00:00
|
|
|
if (m_head == NULL)
|
|
|
|
break;
|
|
|
|
|
|
|
|
/*
|
2004-07-24 13:45:38 +00:00
|
|
|
* XXX
|
|
|
|
* The code inside the if() block is never reached since we
|
|
|
|
* must mark CSUM_IP_FRAGS in our if_hwassist to start getting
|
|
|
|
* requests to checksum TCP/UDP in a fragmented packet.
|
2004-10-30 14:54:51 +00:00
|
|
|
*
|
2001-09-27 23:55:28 +00:00
|
|
|
* XXX
|
|
|
|
* safety overkill. If this is a fragmented packet chain
|
|
|
|
* with delayed TCP/UDP checksums, then only encapsulate
|
|
|
|
* it if we have enough descriptors to handle the entire
|
|
|
|
* chain at once.
|
|
|
|
* (paranoia -- may not actually be needed)
|
|
|
|
*/
|
|
|
|
if (m_head->m_flags & M_FIRSTFRAG &&
|
|
|
|
m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
|
|
|
|
if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
|
|
|
|
m_head->m_pkthdr.csum_data + 16) {
|
2004-10-30 21:21:10 +00:00
|
|
|
IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
|
2005-08-09 10:20:02 +00:00
|
|
|
ifp->if_drv_flags |= IFF_DRV_OACTIVE;
|
2001-09-27 23:55:28 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Pack the data into the transmit ring. If we
|
|
|
|
* don't have room, set the OACTIVE flag and wait
|
|
|
|
* for the NIC to drain the ring.
|
|
|
|
*/
|
2006-08-17 09:53:04 +00:00
|
|
|
if (bge_encap(sc, &m_head, &prodidx)) {
|
|
|
|
if (m_head == NULL)
|
|
|
|
break;
|
2004-10-30 21:21:10 +00:00
|
|
|
IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
|
2005-08-09 10:20:02 +00:00
|
|
|
ifp->if_drv_flags |= IFF_DRV_OACTIVE;
|
2001-09-27 23:55:28 +00:00
|
|
|
break;
|
|
|
|
}
|
2004-10-30 22:59:30 +00:00
|
|
|
++count;
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* If there's a BPF listener, bounce a copy of this frame
|
|
|
|
* to him.
|
|
|
|
*/
|
2002-11-14 23:54:55 +00:00
|
|
|
BPF_MTAP(ifp, m_head);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
if (count == 0)
|
|
|
|
/* No packets were dequeued. */
|
2004-10-30 22:59:30 +00:00
|
|
|
return;
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Transmit. */
|
2001-09-27 23:55:28 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
|
2003-05-04 00:07:21 +00:00
|
|
|
/* 5700 b2 errata */
|
2003-05-07 21:51:13 +00:00
|
|
|
if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
|
2003-05-04 00:07:21 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2005-12-18 20:26:12 +00:00
|
|
|
sc->bge_tx_prodidx = prodidx;
|
|
|
|
|
2001-09-27 23:55:28 +00:00
|
|
|
/*
|
|
|
|
* Set a timeout in case the chip goes out to lunch.
|
|
|
|
*/
|
|
|
|
ifp->if_timer = 5;
|
|
|
|
}
|
|
|
|
|
2003-11-11 17:57:03 +00:00
|
|
|
/*
|
|
|
|
* Main transmit routine. To avoid having to do mbuf copies, we put pointers
|
|
|
|
* to the mbuf data regions directly in the transmit descriptors.
|
|
|
|
*/
|
2001-09-27 23:55:28 +00:00
|
|
|
static void
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_start(struct ifnet *ifp)
|
2003-11-11 17:57:03 +00:00
|
|
|
{
|
|
|
|
struct bge_softc *sc;
|
|
|
|
|
|
|
|
sc = ifp->if_softc;
|
|
|
|
BGE_LOCK(sc);
|
|
|
|
bge_start_locked(ifp);
|
|
|
|
BGE_UNLOCK(sc);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_init_locked(struct bge_softc *sc)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
|
|
|
struct ifnet *ifp;
|
2006-06-07 21:03:20 +00:00
|
|
|
uint16_t *m;
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2003-11-11 17:57:03 +00:00
|
|
|
BGE_LOCK_ASSERT(sc);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2005-06-10 16:49:24 +00:00
|
|
|
ifp = sc->bge_ifp;
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2005-08-09 10:20:02 +00:00
|
|
|
if (ifp->if_drv_flags & IFF_DRV_RUNNING)
|
2001-09-27 23:55:28 +00:00
|
|
|
return;
|
|
|
|
|
|
|
|
/* Cancel pending I/O and flush buffers. */
|
|
|
|
bge_stop(sc);
|
2006-09-09 03:36:57 +00:00
|
|
|
|
|
|
|
bge_stop_fw(sc);
|
|
|
|
bge_sig_pre_reset(sc, BGE_RESET_START);
|
2001-09-27 23:55:28 +00:00
|
|
|
bge_reset(sc);
|
2006-09-09 03:36:57 +00:00
|
|
|
bge_sig_legacy(sc, BGE_RESET_START);
|
|
|
|
bge_sig_post_reset(sc, BGE_RESET_START);
|
|
|
|
|
2001-09-27 23:55:28 +00:00
|
|
|
bge_chipinit(sc);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Init the various state machines, ring
|
|
|
|
* control blocks and firmware.
|
|
|
|
*/
|
|
|
|
if (bge_blockinit(sc)) {
|
2005-12-23 02:04:41 +00:00
|
|
|
device_printf(sc->bge_dev, "initialization failure\n");
|
2001-09-27 23:55:28 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2005-06-10 16:49:24 +00:00
|
|
|
ifp = sc->bge_ifp;
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
/* Specify MTU. */
|
|
|
|
CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
|
2003-08-04 05:50:53 +00:00
|
|
|
ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
/* Load our MAC address. */
|
2006-06-07 21:03:20 +00:00
|
|
|
m = (uint16_t *)IF_LLADDR(sc->bge_ifp);
|
2001-09-27 23:55:28 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
|
|
|
|
CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
|
|
|
|
|
2006-09-18 22:18:21 +00:00
|
|
|
/* Program promiscuous mode. */
|
|
|
|
bge_setpromisc(sc);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
/* Program multicast filter. */
|
|
|
|
bge_setmulti(sc);
|
|
|
|
|
|
|
|
/* Init RX ring. */
|
|
|
|
bge_init_rx_ring_std(sc);
|
|
|
|
|
2003-07-16 00:09:56 +00:00
|
|
|
/*
|
|
|
|
* Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
|
|
|
|
* memory to insure that the chip has in fact read the first
|
|
|
|
* entry of the ring.
|
|
|
|
*/
|
|
|
|
if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
|
2006-06-07 21:03:20 +00:00
|
|
|
uint32_t v, i;
|
2003-07-16 00:09:56 +00:00
|
|
|
for (i = 0; i < 10; i++) {
|
|
|
|
DELAY(20);
|
|
|
|
v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
|
|
|
|
if (v == (MCLBYTES - ETHER_ALIGN))
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (i == 10)
|
2005-12-23 02:04:41 +00:00
|
|
|
device_printf (sc->bge_dev,
|
|
|
|
"5705 A0 chip failed to load RX ring\n");
|
2003-07-16 00:09:56 +00:00
|
|
|
}
|
|
|
|
|
2001-09-27 23:55:28 +00:00
|
|
|
/* Init jumbo RX ring. */
|
|
|
|
if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
|
|
|
|
bge_init_rx_ring_jumbo(sc);
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Init our RX return ring index. */
|
2001-09-27 23:55:28 +00:00
|
|
|
sc->bge_rx_saved_considx = 0;
|
|
|
|
|
|
|
|
/* Init TX ring. */
|
|
|
|
bge_init_tx_ring(sc);
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Turn on transmitter. */
|
2001-09-27 23:55:28 +00:00
|
|
|
BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Turn on receiver. */
|
2001-09-27 23:55:28 +00:00
|
|
|
BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
|
|
|
|
|
|
|
|
/* Tell firmware we're alive. */
|
|
|
|
BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
|
|
|
|
|
2005-10-22 14:31:01 +00:00
|
|
|
#ifdef DEVICE_POLLING
|
|
|
|
/* Disable interrupts if we are polling. */
|
|
|
|
if (ifp->if_capenable & IFCAP_POLLING) {
|
|
|
|
BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
|
|
|
|
BGE_PCIMISCCTL_MASK_PCI_INTR);
|
|
|
|
CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
|
|
|
|
CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
|
|
|
|
CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
|
|
|
|
} else
|
|
|
|
#endif
|
2006-09-09 03:36:57 +00:00
|
|
|
|
2001-09-27 23:55:28 +00:00
|
|
|
/* Enable host interrupts. */
|
2005-10-22 14:31:01 +00:00
|
|
|
{
|
2001-09-27 23:55:28 +00:00
|
|
|
BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
|
|
|
|
BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
|
|
|
|
CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
|
2005-10-22 14:31:01 +00:00
|
|
|
}
|
|
|
|
|
2006-08-24 14:41:16 +00:00
|
|
|
bge_ifmedia_upd_locked(ifp);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2005-08-09 10:20:02 +00:00
|
|
|
ifp->if_drv_flags |= IFF_DRV_RUNNING;
|
|
|
|
ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2003-11-11 17:57:03 +00:00
|
|
|
callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_init(void *xsc)
|
2003-11-11 17:57:03 +00:00
|
|
|
{
|
|
|
|
struct bge_softc *sc = xsc;
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2003-11-11 17:57:03 +00:00
|
|
|
BGE_LOCK(sc);
|
|
|
|
bge_init_locked(sc);
|
|
|
|
BGE_UNLOCK(sc);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Set media options.
|
|
|
|
*/
|
|
|
|
static int
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_ifmedia_upd(struct ifnet *ifp)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
2006-08-24 14:41:16 +00:00
|
|
|
struct bge_softc *sc = ifp->if_softc;
|
|
|
|
int res;
|
|
|
|
|
|
|
|
BGE_LOCK(sc);
|
|
|
|
res = bge_ifmedia_upd_locked(ifp);
|
|
|
|
BGE_UNLOCK(sc);
|
|
|
|
|
|
|
|
return (res);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
bge_ifmedia_upd_locked(struct ifnet *ifp)
|
|
|
|
{
|
|
|
|
struct bge_softc *sc = ifp->if_softc;
|
2001-09-27 23:55:28 +00:00
|
|
|
struct mii_data *mii;
|
|
|
|
struct ifmedia *ifm;
|
|
|
|
|
2006-08-24 14:41:16 +00:00
|
|
|
BGE_LOCK_ASSERT(sc);
|
|
|
|
|
2001-09-27 23:55:28 +00:00
|
|
|
ifm = &sc->bge_ifmedia;
|
|
|
|
|
|
|
|
/* If this is a 1000baseX NIC, enable the TBI port. */
|
2006-08-23 11:32:54 +00:00
|
|
|
if (sc->bge_flags & BGE_FLAG_TBI) {
|
2001-09-27 23:55:28 +00:00
|
|
|
if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
|
2006-06-07 21:03:20 +00:00
|
|
|
return (EINVAL);
|
2001-09-27 23:55:28 +00:00
|
|
|
switch(IFM_SUBTYPE(ifm->ifm_media)) {
|
|
|
|
case IFM_AUTO:
|
2005-06-24 21:43:47 +00:00
|
|
|
/*
|
|
|
|
* The BCM5704 ASIC appears to have a special
|
|
|
|
* mechanism for programming the autoneg
|
|
|
|
* advertisement registers in TBI mode.
|
|
|
|
*/
|
2006-04-25 15:56:52 +00:00
|
|
|
if (bge_fake_autoneg == 0 &&
|
|
|
|
sc->bge_asicrev == BGE_ASICREV_BCM5704) {
|
2005-06-24 21:43:47 +00:00
|
|
|
uint32_t sgdig;
|
|
|
|
CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
|
|
|
|
sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
|
|
|
|
sgdig |= BGE_SGDIGCFG_AUTO|
|
|
|
|
BGE_SGDIGCFG_PAUSE_CAP|
|
|
|
|
BGE_SGDIGCFG_ASYM_PAUSE;
|
|
|
|
CSR_WRITE_4(sc, BGE_SGDIG_CFG,
|
|
|
|
sgdig|BGE_SGDIGCFG_SEND);
|
|
|
|
DELAY(5);
|
|
|
|
CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
|
|
|
|
}
|
2001-09-27 23:55:28 +00:00
|
|
|
break;
|
|
|
|
case IFM_1000_SX:
|
|
|
|
if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
|
|
|
|
BGE_CLRBIT(sc, BGE_MAC_MODE,
|
|
|
|
BGE_MACMODE_HALF_DUPLEX);
|
|
|
|
} else {
|
|
|
|
BGE_SETBIT(sc, BGE_MAC_MODE,
|
|
|
|
BGE_MACMODE_HALF_DUPLEX);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
2006-06-07 21:03:20 +00:00
|
|
|
return (EINVAL);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
2006-06-07 21:03:20 +00:00
|
|
|
return (0);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
2006-02-17 14:33:35 +00:00
|
|
|
sc->bge_link_evt++;
|
2001-09-27 23:55:28 +00:00
|
|
|
mii = device_get_softc(sc->bge_miibus);
|
|
|
|
if (mii->mii_instance) {
|
|
|
|
struct mii_softc *miisc;
|
|
|
|
for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
|
|
|
|
miisc = LIST_NEXT(miisc, mii_list))
|
|
|
|
mii_phy_reset(miisc);
|
|
|
|
}
|
|
|
|
mii_mediachg(mii);
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
return (0);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Report current media status.
|
|
|
|
*/
|
|
|
|
static void
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
2006-08-24 14:41:16 +00:00
|
|
|
struct bge_softc *sc = ifp->if_softc;
|
2001-09-27 23:55:28 +00:00
|
|
|
struct mii_data *mii;
|
|
|
|
|
2006-08-24 14:41:16 +00:00
|
|
|
BGE_LOCK(sc);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2006-08-23 11:32:54 +00:00
|
|
|
if (sc->bge_flags & BGE_FLAG_TBI) {
|
2001-09-27 23:55:28 +00:00
|
|
|
ifmr->ifm_status = IFM_AVALID;
|
|
|
|
ifmr->ifm_active = IFM_ETHER;
|
|
|
|
if (CSR_READ_4(sc, BGE_MAC_STS) &
|
|
|
|
BGE_MACSTAT_TBI_PCS_SYNCHED)
|
|
|
|
ifmr->ifm_status |= IFM_ACTIVE;
|
2006-06-15 14:31:49 +00:00
|
|
|
else {
|
|
|
|
ifmr->ifm_active |= IFM_NONE;
|
2006-08-24 14:41:16 +00:00
|
|
|
BGE_UNLOCK(sc);
|
2006-06-15 14:31:49 +00:00
|
|
|
return;
|
|
|
|
}
|
2001-09-27 23:55:28 +00:00
|
|
|
ifmr->ifm_active |= IFM_1000_SX;
|
|
|
|
if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
|
2004-10-30 14:54:51 +00:00
|
|
|
ifmr->ifm_active |= IFM_HDX;
|
2001-09-27 23:55:28 +00:00
|
|
|
else
|
|
|
|
ifmr->ifm_active |= IFM_FDX;
|
2006-08-24 14:41:16 +00:00
|
|
|
BGE_UNLOCK(sc);
|
2001-09-27 23:55:28 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
mii = device_get_softc(sc->bge_miibus);
|
|
|
|
mii_pollstat(mii);
|
|
|
|
ifmr->ifm_active = mii->mii_media_active;
|
|
|
|
ifmr->ifm_status = mii->mii_media_status;
|
2006-08-24 14:41:16 +00:00
|
|
|
|
|
|
|
BGE_UNLOCK(sc);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
|
|
|
struct bge_softc *sc = ifp->if_softc;
|
|
|
|
struct ifreq *ifr = (struct ifreq *) data;
|
|
|
|
struct mii_data *mii;
|
2006-09-18 20:54:40 +00:00
|
|
|
int flags, mask, error = 0;
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
switch (command) {
|
2001-09-27 23:55:28 +00:00
|
|
|
case SIOCSIFMTU:
|
2006-06-15 14:31:49 +00:00
|
|
|
if (ifr->ifr_mtu < ETHERMIN ||
|
|
|
|
((BGE_IS_JUMBO_CAPABLE(sc)) &&
|
|
|
|
ifr->ifr_mtu > BGE_JUMBO_MTU) ||
|
|
|
|
((!BGE_IS_JUMBO_CAPABLE(sc)) &&
|
|
|
|
ifr->ifr_mtu > ETHERMTU))
|
2001-09-27 23:55:28 +00:00
|
|
|
error = EINVAL;
|
2006-06-15 14:31:49 +00:00
|
|
|
else if (ifp->if_mtu != ifr->ifr_mtu) {
|
2001-09-27 23:55:28 +00:00
|
|
|
ifp->if_mtu = ifr->ifr_mtu;
|
2005-08-09 10:20:02 +00:00
|
|
|
ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
|
2001-09-27 23:55:28 +00:00
|
|
|
bge_init(sc);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case SIOCSIFFLAGS:
|
2003-11-11 17:57:03 +00:00
|
|
|
BGE_LOCK(sc);
|
2001-09-27 23:55:28 +00:00
|
|
|
if (ifp->if_flags & IFF_UP) {
|
|
|
|
/*
|
|
|
|
* If only the state of the PROMISC flag changed,
|
|
|
|
* then just use the 'set promisc mode' command
|
|
|
|
* instead of reinitializing the entire NIC. Doing
|
|
|
|
* a full re-init means reloading the firmware and
|
|
|
|
* waiting for it to start up, which may take a
|
2006-02-01 10:11:24 +00:00
|
|
|
* second or two. Similarly for ALLMULTI.
|
2001-09-27 23:55:28 +00:00
|
|
|
*/
|
2006-09-18 20:54:40 +00:00
|
|
|
if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
|
|
|
|
flags = ifp->if_flags ^ sc->bge_if_flags;
|
2006-09-18 22:18:21 +00:00
|
|
|
if (flags & IFF_PROMISC)
|
|
|
|
bge_setpromisc(sc);
|
2006-09-18 20:54:40 +00:00
|
|
|
if (flags & IFF_ALLMULTI)
|
|
|
|
bge_setmulti(sc);
|
2001-09-27 23:55:28 +00:00
|
|
|
} else
|
2003-11-11 17:57:03 +00:00
|
|
|
bge_init_locked(sc);
|
2001-09-27 23:55:28 +00:00
|
|
|
} else {
|
2005-08-09 10:20:02 +00:00
|
|
|
if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
|
2001-09-27 23:55:28 +00:00
|
|
|
bge_stop(sc);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
sc->bge_if_flags = ifp->if_flags;
|
2003-11-11 17:57:03 +00:00
|
|
|
BGE_UNLOCK(sc);
|
2001-09-27 23:55:28 +00:00
|
|
|
error = 0;
|
|
|
|
break;
|
|
|
|
case SIOCADDMULTI:
|
|
|
|
case SIOCDELMULTI:
|
2005-08-09 10:20:02 +00:00
|
|
|
if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
|
2003-11-11 17:57:03 +00:00
|
|
|
BGE_LOCK(sc);
|
2001-09-27 23:55:28 +00:00
|
|
|
bge_setmulti(sc);
|
2003-11-11 17:57:03 +00:00
|
|
|
BGE_UNLOCK(sc);
|
2001-09-27 23:55:28 +00:00
|
|
|
error = 0;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case SIOCSIFMEDIA:
|
|
|
|
case SIOCGIFMEDIA:
|
2006-08-23 11:32:54 +00:00
|
|
|
if (sc->bge_flags & BGE_FLAG_TBI) {
|
2001-09-27 23:55:28 +00:00
|
|
|
error = ifmedia_ioctl(ifp, ifr,
|
|
|
|
&sc->bge_ifmedia, command);
|
|
|
|
} else {
|
|
|
|
mii = device_get_softc(sc->bge_miibus);
|
|
|
|
error = ifmedia_ioctl(ifp, ifr,
|
|
|
|
&mii->mii_media, command);
|
|
|
|
}
|
|
|
|
break;
|
2004-10-30 14:54:51 +00:00
|
|
|
case SIOCSIFCAP:
|
2001-09-27 23:55:28 +00:00
|
|
|
mask = ifr->ifr_reqcap ^ ifp->if_capenable;
|
2005-10-22 14:31:01 +00:00
|
|
|
#ifdef DEVICE_POLLING
|
|
|
|
if (mask & IFCAP_POLLING) {
|
|
|
|
if (ifr->ifr_reqcap & IFCAP_POLLING) {
|
|
|
|
error = ether_poll_register(bge_poll, ifp);
|
|
|
|
if (error)
|
2006-06-07 21:03:20 +00:00
|
|
|
return (error);
|
2005-10-22 14:31:01 +00:00
|
|
|
BGE_LOCK(sc);
|
|
|
|
BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
|
|
|
|
BGE_PCIMISCCTL_MASK_PCI_INTR);
|
|
|
|
CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
|
|
|
|
CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
|
|
|
|
CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
|
2006-06-08 10:19:16 +00:00
|
|
|
ifp->if_capenable |= IFCAP_POLLING;
|
2005-10-22 14:31:01 +00:00
|
|
|
BGE_UNLOCK(sc);
|
|
|
|
} else {
|
|
|
|
error = ether_poll_deregister(ifp);
|
|
|
|
/* Enable interrupt even in error case */
|
|
|
|
BGE_LOCK(sc);
|
|
|
|
CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
|
|
|
|
CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
|
|
|
|
BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
|
|
|
|
BGE_PCIMISCCTL_MASK_PCI_INTR);
|
|
|
|
CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
|
|
|
|
ifp->if_capenable &= ~IFCAP_POLLING;
|
|
|
|
BGE_UNLOCK(sc);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
2005-12-22 15:14:42 +00:00
|
|
|
if (mask & IFCAP_HWCSUM) {
|
|
|
|
ifp->if_capenable ^= IFCAP_HWCSUM;
|
|
|
|
if (IFCAP_HWCSUM & ifp->if_capenable &&
|
|
|
|
IFCAP_HWCSUM & ifp->if_capabilities)
|
2004-07-24 13:45:38 +00:00
|
|
|
ifp->if_hwassist = BGE_CSUM_FEATURES;
|
2001-09-27 23:55:28 +00:00
|
|
|
else
|
2004-07-24 13:45:38 +00:00
|
|
|
ifp->if_hwassist = 0;
|
2006-01-30 13:45:55 +00:00
|
|
|
VLAN_CAPABILITIES(ifp);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
2002-11-14 23:54:55 +00:00
|
|
|
error = ether_ioctl(ifp, command, data);
|
2001-09-27 23:55:28 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
return (error);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_watchdog(struct ifnet *ifp)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
|
|
|
struct bge_softc *sc;
|
|
|
|
|
|
|
|
sc = ifp->if_softc;
|
|
|
|
|
2005-12-23 02:04:41 +00:00
|
|
|
if_printf(ifp, "watchdog timeout -- resetting\n");
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2005-08-09 10:20:02 +00:00
|
|
|
ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
|
2001-09-27 23:55:28 +00:00
|
|
|
bge_init(sc);
|
|
|
|
|
|
|
|
ifp->if_oerrors++;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Stop the adapter and free any mbufs allocated to the
|
|
|
|
* RX and TX lists.
|
|
|
|
*/
|
|
|
|
static void
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_stop(struct bge_softc *sc)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
|
|
|
struct ifnet *ifp;
|
|
|
|
struct ifmedia_entry *ifm;
|
|
|
|
struct mii_data *mii = NULL;
|
|
|
|
int mtmp, itmp;
|
|
|
|
|
2003-11-11 17:57:03 +00:00
|
|
|
BGE_LOCK_ASSERT(sc);
|
|
|
|
|
2005-06-10 16:49:24 +00:00
|
|
|
ifp = sc->bge_ifp;
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2006-08-23 11:32:54 +00:00
|
|
|
if ((sc->bge_flags & BGE_FLAG_TBI) == 0)
|
2001-09-27 23:55:28 +00:00
|
|
|
mii = device_get_softc(sc->bge_miibus);
|
|
|
|
|
2003-11-11 17:57:03 +00:00
|
|
|
callout_stop(&sc->bge_stat_ch);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
/*
|
2006-06-07 21:03:20 +00:00
|
|
|
* Disable all of the receiver blocks.
|
2001-09-27 23:55:28 +00:00
|
|
|
*/
|
|
|
|
BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
|
|
|
|
BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
|
|
|
|
BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
|
2006-06-15 14:31:49 +00:00
|
|
|
if (!(BGE_IS_5705_OR_BEYOND(sc)))
|
2003-07-16 00:09:56 +00:00
|
|
|
BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
|
2001-09-27 23:55:28 +00:00
|
|
|
BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
|
|
|
|
BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
|
|
|
|
BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
|
|
|
|
|
|
|
|
/*
|
2006-06-07 21:03:20 +00:00
|
|
|
* Disable all of the transmit blocks.
|
2001-09-27 23:55:28 +00:00
|
|
|
*/
|
|
|
|
BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
|
|
|
|
BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
|
|
|
|
BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
|
|
|
|
BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
|
|
|
|
BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
|
2006-06-15 14:31:49 +00:00
|
|
|
if (!(BGE_IS_5705_OR_BEYOND(sc)))
|
2003-07-16 00:09:56 +00:00
|
|
|
BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
|
2001-09-27 23:55:28 +00:00
|
|
|
BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Shut down all of the memory managers and related
|
|
|
|
* state machines.
|
|
|
|
*/
|
|
|
|
BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
|
|
|
|
BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
|
2006-06-15 14:31:49 +00:00
|
|
|
if (!(BGE_IS_5705_OR_BEYOND(sc)))
|
2003-07-16 00:09:56 +00:00
|
|
|
BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
|
2001-09-27 23:55:28 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
|
|
|
|
CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
|
2006-06-15 14:31:49 +00:00
|
|
|
if (!(BGE_IS_5705_OR_BEYOND(sc))) {
|
2003-07-16 00:09:56 +00:00
|
|
|
BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
|
|
|
|
BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
|
|
|
|
}
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
/* Disable host interrupts. */
|
|
|
|
BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
|
|
|
|
CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Tell firmware we're shutting down.
|
|
|
|
*/
|
2006-09-09 03:36:57 +00:00
|
|
|
|
|
|
|
bge_stop_fw(sc);
|
|
|
|
bge_sig_pre_reset(sc, BGE_RESET_STOP);
|
|
|
|
bge_reset(sc);
|
|
|
|
bge_sig_legacy(sc, BGE_RESET_STOP);
|
|
|
|
bge_sig_post_reset(sc, BGE_RESET_STOP);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Keep the ASF firmware running if up.
|
|
|
|
*/
|
|
|
|
if (sc->bge_asf_mode & ASF_STACKUP)
|
|
|
|
BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
|
|
|
|
else
|
|
|
|
BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
/* Free the RX lists. */
|
|
|
|
bge_free_rx_ring_std(sc);
|
|
|
|
|
|
|
|
/* Free jumbo RX list. */
|
2006-06-15 14:31:49 +00:00
|
|
|
if (BGE_IS_JUMBO_CAPABLE(sc))
|
2003-07-16 00:09:56 +00:00
|
|
|
bge_free_rx_ring_jumbo(sc);
|
2001-09-27 23:55:28 +00:00
|
|
|
|
|
|
|
/* Free TX buffers. */
|
|
|
|
bge_free_tx_ring(sc);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Isolate/power down the PHY, but leave the media selection
|
|
|
|
* unchanged so that things will be put back to normal when
|
|
|
|
* we bring the interface back up.
|
|
|
|
*/
|
2006-08-23 11:32:54 +00:00
|
|
|
if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
|
2001-09-27 23:55:28 +00:00
|
|
|
itmp = ifp->if_flags;
|
|
|
|
ifp->if_flags |= IFF_UP;
|
2005-09-04 06:35:59 +00:00
|
|
|
/*
|
|
|
|
* If we are called from bge_detach(), mii is already NULL.
|
|
|
|
*/
|
|
|
|
if (mii != NULL) {
|
|
|
|
ifm = mii->mii_media.ifm_cur;
|
|
|
|
mtmp = ifm->ifm_media;
|
|
|
|
ifm->ifm_media = IFM_ETHER|IFM_NONE;
|
|
|
|
mii_mediachg(mii);
|
|
|
|
ifm->ifm_media = mtmp;
|
|
|
|
}
|
2001-09-27 23:55:28 +00:00
|
|
|
ifp->if_flags = itmp;
|
|
|
|
}
|
|
|
|
|
|
|
|
sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
|
|
|
|
|
2006-02-17 14:33:35 +00:00
|
|
|
/*
|
|
|
|
* We can't just call bge_link_upd() cause chip is almost stopped so
|
|
|
|
* bge_link_upd -> bge_tick_locked -> bge_stats_update sequence may
|
|
|
|
* lead to hardware deadlock. So we just clearing MAC's link state
|
|
|
|
* (PHY may still have link UP).
|
|
|
|
*/
|
|
|
|
if (bootverbose && sc->bge_link)
|
|
|
|
if_printf(sc->bge_ifp, "link DOWN\n");
|
|
|
|
sc->bge_link = 0;
|
2001-09-27 23:55:28 +00:00
|
|
|
|
2006-02-17 14:33:35 +00:00
|
|
|
ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Stop all chip I/O so that the kernel's probe routines don't
|
|
|
|
* get confused by errant DMAs when rebooting.
|
|
|
|
*/
|
|
|
|
static void
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_shutdown(device_t dev)
|
2001-09-27 23:55:28 +00:00
|
|
|
{
|
|
|
|
struct bge_softc *sc;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
|
2003-11-11 17:57:03 +00:00
|
|
|
BGE_LOCK(sc);
|
2004-10-30 14:54:51 +00:00
|
|
|
bge_stop(sc);
|
2001-09-27 23:55:28 +00:00
|
|
|
bge_reset(sc);
|
2003-11-11 17:57:03 +00:00
|
|
|
BGE_UNLOCK(sc);
|
2001-09-27 23:55:28 +00:00
|
|
|
}
|
2005-09-28 19:20:49 +00:00
|
|
|
|
|
|
|
static int
|
|
|
|
bge_suspend(device_t dev)
|
|
|
|
{
|
|
|
|
struct bge_softc *sc;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
BGE_LOCK(sc);
|
|
|
|
bge_stop(sc);
|
|
|
|
BGE_UNLOCK(sc);
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
bge_resume(device_t dev)
|
|
|
|
{
|
|
|
|
struct bge_softc *sc;
|
|
|
|
struct ifnet *ifp;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
BGE_LOCK(sc);
|
|
|
|
ifp = sc->bge_ifp;
|
|
|
|
if (ifp->if_flags & IFF_UP) {
|
|
|
|
bge_init_locked(sc);
|
|
|
|
if (ifp->if_drv_flags & IFF_DRV_RUNNING)
|
|
|
|
bge_start_locked(ifp);
|
|
|
|
}
|
|
|
|
BGE_UNLOCK(sc);
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
2005-12-08 13:31:52 +00:00
|
|
|
|
|
|
|
static void
|
2006-06-07 21:03:20 +00:00
|
|
|
bge_link_upd(struct bge_softc *sc)
|
2005-12-08 13:31:52 +00:00
|
|
|
{
|
2006-01-13 08:59:40 +00:00
|
|
|
struct mii_data *mii;
|
|
|
|
uint32_t link, status;
|
2005-12-08 13:31:52 +00:00
|
|
|
|
|
|
|
BGE_LOCK_ASSERT(sc);
|
2006-01-13 08:59:40 +00:00
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Clear 'pending link event' flag. */
|
2006-02-01 14:26:35 +00:00
|
|
|
sc->bge_link_evt = 0;
|
|
|
|
|
2005-12-08 13:31:52 +00:00
|
|
|
/*
|
|
|
|
* Process link state changes.
|
|
|
|
* Grrr. The link status word in the status block does
|
|
|
|
* not work correctly on the BCM5700 rev AX and BX chips,
|
|
|
|
* according to all available information. Hence, we have
|
|
|
|
* to enable MII interrupts in order to properly obtain
|
|
|
|
* async link changes. Unfortunately, this also means that
|
|
|
|
* we have to read the MAC status register to detect link
|
|
|
|
* changes, thereby adding an additional register access to
|
|
|
|
* the interrupt handler.
|
2006-01-13 08:59:40 +00:00
|
|
|
*
|
|
|
|
* XXX: perhaps link state detection procedure used for
|
2006-06-15 14:31:49 +00:00
|
|
|
* BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
|
2005-12-08 13:31:52 +00:00
|
|
|
*/
|
|
|
|
|
2006-01-13 08:59:40 +00:00
|
|
|
if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
|
2006-06-15 14:31:49 +00:00
|
|
|
sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
|
2005-12-08 13:31:52 +00:00
|
|
|
status = CSR_READ_4(sc, BGE_MAC_STS);
|
|
|
|
if (status & BGE_MACSTAT_MI_INTERRUPT) {
|
|
|
|
callout_stop(&sc->bge_stat_ch);
|
|
|
|
bge_tick_locked(sc);
|
2006-01-13 08:59:40 +00:00
|
|
|
|
|
|
|
mii = device_get_softc(sc->bge_miibus);
|
|
|
|
if (!sc->bge_link &&
|
|
|
|
mii->mii_media_status & IFM_ACTIVE &&
|
|
|
|
IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
|
|
|
|
sc->bge_link++;
|
|
|
|
if (bootverbose)
|
|
|
|
if_printf(sc->bge_ifp, "link UP\n");
|
|
|
|
} else if (sc->bge_link &&
|
|
|
|
(!(mii->mii_media_status & IFM_ACTIVE) ||
|
|
|
|
IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
|
|
|
|
sc->bge_link = 0;
|
|
|
|
if (bootverbose)
|
|
|
|
if_printf(sc->bge_ifp, "link DOWN\n");
|
|
|
|
}
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Clear the interrupt. */
|
2005-12-08 13:31:52 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
|
|
|
|
BGE_EVTENB_MI_INTERRUPT);
|
|
|
|
bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
|
|
|
|
bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,
|
|
|
|
BRGPHY_INTRS);
|
|
|
|
}
|
|
|
|
return;
|
2006-06-08 10:19:16 +00:00
|
|
|
}
|
2005-12-08 13:31:52 +00:00
|
|
|
|
2006-08-23 11:32:54 +00:00
|
|
|
if (sc->bge_flags & BGE_FLAG_TBI) {
|
2006-01-13 08:59:40 +00:00
|
|
|
status = CSR_READ_4(sc, BGE_MAC_STS);
|
2006-02-01 14:26:35 +00:00
|
|
|
if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
|
|
|
|
if (!sc->bge_link) {
|
2006-01-13 08:59:40 +00:00
|
|
|
sc->bge_link++;
|
|
|
|
if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
|
|
|
|
BGE_CLRBIT(sc, BGE_MAC_MODE,
|
|
|
|
BGE_MACMODE_TBI_SEND_CFGS);
|
|
|
|
CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
|
|
|
|
if (bootverbose)
|
|
|
|
if_printf(sc->bge_ifp, "link UP\n");
|
2006-06-07 21:03:20 +00:00
|
|
|
if_link_state_change(sc->bge_ifp,
|
|
|
|
LINK_STATE_UP);
|
2006-01-13 08:59:40 +00:00
|
|
|
}
|
2006-02-01 14:26:35 +00:00
|
|
|
} else if (sc->bge_link) {
|
|
|
|
sc->bge_link = 0;
|
|
|
|
if (bootverbose)
|
|
|
|
if_printf(sc->bge_ifp, "link DOWN\n");
|
|
|
|
if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
|
2006-01-13 08:59:40 +00:00
|
|
|
}
|
2006-02-17 14:33:35 +00:00
|
|
|
/* Discard link events for MII/GMII cards if MI auto-polling disabled */
|
|
|
|
} else if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
|
2006-06-08 10:19:16 +00:00
|
|
|
/*
|
2006-01-13 08:59:40 +00:00
|
|
|
* Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
|
|
|
|
* in status word always set. Workaround this bug by reading
|
|
|
|
* PHY link status directly.
|
|
|
|
*/
|
|
|
|
link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
|
|
|
|
|
|
|
|
if (link != sc->bge_link ||
|
|
|
|
sc->bge_asicrev == BGE_ASICREV_BCM5700) {
|
|
|
|
callout_stop(&sc->bge_stat_ch);
|
|
|
|
bge_tick_locked(sc);
|
|
|
|
|
|
|
|
mii = device_get_softc(sc->bge_miibus);
|
|
|
|
if (!sc->bge_link &&
|
|
|
|
mii->mii_media_status & IFM_ACTIVE &&
|
|
|
|
IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
|
|
|
|
sc->bge_link++;
|
|
|
|
if (bootverbose)
|
|
|
|
if_printf(sc->bge_ifp, "link UP\n");
|
|
|
|
} else if (sc->bge_link &&
|
|
|
|
(!(mii->mii_media_status & IFM_ACTIVE) ||
|
|
|
|
IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
|
|
|
|
sc->bge_link = 0;
|
|
|
|
if (bootverbose)
|
|
|
|
if_printf(sc->bge_ifp, "link DOWN\n");
|
|
|
|
}
|
|
|
|
}
|
2005-12-08 13:31:52 +00:00
|
|
|
}
|
|
|
|
|
2006-06-07 21:03:20 +00:00
|
|
|
/* Clear the attention. */
|
2005-12-08 13:31:52 +00:00
|
|
|
CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
|
|
|
|
BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
|
|
|
|
BGE_MACSTAT_LINK_CHANGED);
|
|
|
|
}
|