d/freebsd-dev
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
6f78dae849
freebsd-dev/sys/powerpc/include/intr_machdep.h

67 lines
2.4 KiB
C
Raw Normal View History

/* -> /*- for license, minor formatting changes
2005-01-07 02:29:27 +00:00
/*-
sys/powerpc: further adoption of SPDX licensing ID tags. Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
2017-11-27 15:09:59 +00:00
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
Add interrupt handling support code. I've tried to make this fairly platform-independant as some PowerPC platforms may not have openpic-style interrupt controllers. This may not have the best performance but it works for now.
2002-07-09 11:12:20 +00:00
* Copyright (C) 2002 Benno Rice.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _MACHINE_INTR_MACHDEP_H_
#define _MACHINE_INTR_MACHDEP_H_
Revamp the interrupt handling in support of INTR_FILTER. This includes: o Revamp the PIC I/F to only abstract the PIC hardware. The resource handling has been moved to nexus, where it belongs. o Include EOI and MASK+EOI methods to the PIC I/F in support of INTR_FILTER. o With the allocation of interrupt resources and setup of interrupt handlers in the common platform code we can delay talking to the PIC hardware after enumeration of all devices. Introduce a call to powerpc_intr_enable() in configure_final() to achieve that and have powerpc_setup_intr() only program the PIC when !cold. o As a consequence of the above, remove all early_attach() glue from the OpenPIC and Heathrow PIC drivers and have them register themselves when they're found during enumeration. o Decouple the interrupt vector from the interrupt request line. Allocate vectors increasingly so that they can be used for the intrcnt index as well. Extend the Heathrow PIC driver to translate between IRQ and vector. The OpenPIC driver already has the support for vectors in hardware. Approved by: re (blanket)
2007-08-11 19:25:32 +00:00
#define INTR_VECTORS 256
Provide for multiple, cascaded PICs on PowerPC systems, and extend the OFW interrupt map interface to also return the device's interrupt parent. MFC after: 8.1-RELEASE
2010-06-18 14:06:27 +00:00
PPC: increase MAX_PICS to 32 Previous value was too low on dual-socket POWER8 system. Submitted by: Wojciech Macek <wma@freebsd.org> Reviewed by: nwhitehorn Obtained from: Semihalf Sponsored by: QCM Technologies Differential revision: https://reviews.freebsd.org/D12540
2017-10-02 06:05:19 +00:00
#define MAX_PICS 32
Rename INTR_VEC to MAP_IRQ. From the OFW or FDT we obtain a PIC handle with interrupt pin. This we map to the resource called SYS_RES_IRQ.
2011-02-02 05:58:51 +00:00
#define MAP_IRQ(node, pin) powerpc_get_irq(node, pin)
Add interrupt handling support code. I've tried to make this fairly platform-independant as some PowerPC platforms may not have openpic-style interrupt controllers. This may not have the best performance but it works for now.
2002-07-09 11:12:20 +00:00
Add support for the U4 PCI-Express bridge chipset used in late-generation Powermac G5 systems. MSI and several other things are not presently supported. The U3/U4 internal device support portions of this change were contributed by Andreas Tobler. MFC after: 1 week
2010-05-16 15:18:25 +00:00
/*
* Default base address for MSI messages on PowerPC
*/
#define MSI_INTEL_ADDR_BASE 0xfee00000
Provide for multiple, cascaded PICs on PowerPC systems, and extend the OFW interrupt map interface to also return the device's interrupt parent. MFC after: 8.1-RELEASE
2010-06-18 14:06:27 +00:00
extern device_t root_pic;
Add interrupt handling support code. I've tried to make this fairly platform-independant as some PowerPC platforms may not have openpic-style interrupt controllers. This may not have the best performance but it works for now.
2002-07-09 11:12:20 +00:00
Revamp the interrupt handling in support of INTR_FILTER. This includes: o Revamp the PIC I/F to only abstract the PIC hardware. The resource handling has been moved to nexus, where it belongs. o Include EOI and MASK+EOI methods to the PIC I/F in support of INTR_FILTER. o With the allocation of interrupt resources and setup of interrupt handlers in the common platform code we can delay talking to the PIC hardware after enumeration of all devices. Introduce a call to powerpc_intr_enable() in configure_final() to achieve that and have powerpc_setup_intr() only program the PIC when !cold. o As a consequence of the above, remove all early_attach() glue from the OpenPIC and Heathrow PIC drivers and have them register themselves when they're found during enumeration. o Decouple the interrupt vector from the interrupt request line. Allocate vectors increasingly so that they can be used for the intrcnt index as well. Extend the Heathrow PIC driver to translate between IRQ and vector. The OpenPIC driver already has the support for vectors in hardware. Approved by: re (blanket)
2007-08-11 19:25:32 +00:00
struct trapframe;
Add interrupt handling support code. I've tried to make this fairly platform-independant as some PowerPC platforms may not have openpic-style interrupt controllers. This may not have the best performance but it works for now.
2002-07-09 11:12:20 +00:00
Add PIC support for IPIs. When registering an interrupt handler, the PIC also informs the platform at which IRQ level it can start assigning IPIs, since this can depend on the number of IRQs supported for external interrupts.
2008-02-12 18:14:46 +00:00
driver_filter_t powerpc_ipi_handler;
Update PowerPC event timer code to use new event timers infrastructure. Reviewed by: nwitehorn Tested by: andreast H/W donated by: Gheorghe Ardelean
2010-09-11 04:45:51 +00:00
void intrcnt_add(const char *name, u_long **countp);
Return base IRQ of PIC when added and massively increase the number of available IRQs per PIC for large systems. MFC after: 3 weeks
2017-11-25 22:42:05 +00:00
u_int powerpc_register_pic(device_t, uint32_t, u_int, u_int, u_int);
Fix the interrupt code, broken 7 months ago. The interrupt framework already supported nested PICs, but was limited to having a nested AT-PIC only. With G5 support the need for nested OpenPIC controllers needed to be added. This was done the wrong way and broke the MPC8555 eval system in the process. OFW, as well as FDT, describe the interrupt routing in terms of a controller and an interrupt pin on it. This needs to be mapped to a flat and global resource: the IRQ. The IRQ is the same as the PCI intline and as such needs to be representable in 8 bits. Secondly, ISA support pretty much dictates that IRQ 0-15 should be reserved for ISA interrupts, because of the internal workins of south bridges. Both were broken. This change reverts revision 209298 for a big part and re-implements it simpler. In particular: o The id() method of the PIC I/F is removed again. It's not needed. o The openpic_attach() function has been changed to take the OFW or FDT phandle of the controller as a second argument. All bus attachments that previously used openpic_attach() as the attach method of the device I/F now implement as bus-specific method and pass the phandle_t to the renamed openpic_attach(). o Change powerpc_register_pic() to take a few more arguments. In particular: - Pass the number of IPIs specificly. The number of IRQs carved out for a PIC is the sum of the number of int. pins and IPIs. - Pass a flag indicating whether the PIC is an AT-PIC or not. This tells the interrupt framework whether to assign IRQ 0-15 or some other range. o Until we implement proper multi-pass bus enumeration, we have to handle the case where we need to map from PIC+pin to IRQ *before* the PIC gets registered. This is done in a similar way as before, but rather than carving out 256 IRQs per PIC, we carve out 128 IRQs (124 pins + 4 IPIs). This is supposed to handle the G5 case, but should really be fixed properly using multiple passes. o Have the interrupt framework set root_pic in most cases and not put that burden in PIC drivers (for the most part). o Remove powerpc_ign_lookup() and replace it with powerpc_get_irq(). Remove IGN_SHIFT, INTR_INTLINE and INTR_IGN. Related to the above, fix the Freescale PCI controller driver, broken by the FDT code. Besides not attaching properly, bus numbers were assigned improperly and enumeration was broken in general. This prevented the AT PIC from being discovered and interrupt routing to work properly. Consequently, the ata(4) controller stopped functioning. Fix the driver, and FDT PCI support, enough to get the MPC8555CDS going again. The FDT PCI code needs a whole lot more work. No breakages are expected, but lackiong G5 hardware, it's possible that there are unpleasant side-effects. At least MPC85xx support is back to where it was 7 months ago -- it's amazing how badly support can be broken in just 7 months... Sponsored by: Juniper Networks
2011-01-29 20:58:38 +00:00
u_int powerpc_get_irq(uint32_t, u_int);
Eliminate <machine/interruptvar.h> as it has only a single prototype. In the future that prototype will not be needed at all anyway, but for now it's moved to intr_machdep.h. Approved by: re (blanket)
2007-08-07 23:33:35 +00:00
Revamp the interrupt handling in support of INTR_FILTER. This includes: o Revamp the PIC I/F to only abstract the PIC hardware. The resource handling has been moved to nexus, where it belongs. o Include EOI and MASK+EOI methods to the PIC I/F in support of INTR_FILTER. o With the allocation of interrupt resources and setup of interrupt handlers in the common platform code we can delay talking to the PIC hardware after enumeration of all devices. Introduce a call to powerpc_intr_enable() in configure_final() to achieve that and have powerpc_setup_intr() only program the PIC when !cold. o As a consequence of the above, remove all early_attach() glue from the OpenPIC and Heathrow PIC drivers and have them register themselves when they're found during enumeration. o Decouple the interrupt vector from the interrupt request line. Allocate vectors increasingly so that they can be used for the intrcnt index as well. Extend the Heathrow PIC driver to translate between IRQ and vector. The OpenPIC driver already has the support for vectors in hardware. Approved by: re (blanket)
2007-08-11 19:25:32 +00:00
void powerpc_dispatch_intr(u_int, struct trapframe *);
int powerpc_enable_intr(void);
Provide for multiple, cascaded PICs on PowerPC systems, and extend the OFW interrupt map interface to also return the device's interrupt parent. MFC after: 8.1-RELEASE
2010-06-18 14:06:27 +00:00
int powerpc_setup_intr(const char *, u_int, driver_filter_t, driver_intr_t,
Add NUMA support to powerpc Summary: Initial NUMA support: - associate CPU with domain - associate memory ranges with domain - identify domain for devices - limit device interrupt binding to appropriate domain - Additionally fixes a bug in the setting of Maxmem which led to only memory attached to the first socket being enabled for DMA A pmap variant can opt in to numa support by by calling `numa_mem_regions` at the end of pmap_bootstrap - registering the corresponding ranges with the VM. This yields a ~20% improvement in build times of llvm on dual socket POWER9 over non-NUMA. Original patch by mmacy. Differential Revision: https://reviews.freebsd.org/D17933
2019-04-13 04:03:18 +00:00
void *, enum intr_type, void **, int);
Revamp the interrupt handling in support of INTR_FILTER. This includes: o Revamp the PIC I/F to only abstract the PIC hardware. The resource handling has been moved to nexus, where it belongs. o Include EOI and MASK+EOI methods to the PIC I/F in support of INTR_FILTER. o With the allocation of interrupt resources and setup of interrupt handlers in the common platform code we can delay talking to the PIC hardware after enumeration of all devices. Introduce a call to powerpc_intr_enable() in configure_final() to achieve that and have powerpc_setup_intr() only program the PIC when !cold. o As a consequence of the above, remove all early_attach() glue from the OpenPIC and Heathrow PIC drivers and have them register themselves when they're found during enumeration. o Decouple the interrupt vector from the interrupt request line. Allocate vectors increasingly so that they can be used for the intrcnt index as well. Extend the Heathrow PIC driver to translate between IRQ and vector. The OpenPIC driver already has the support for vectors in hardware. Approved by: re (blanket)
2007-08-11 19:25:32 +00:00
int powerpc_teardown_intr(void *);
Configure interrupts on SMP systems to be distributed among all online CPUs by default, and provide a functional version of BUS_BIND_INTR(). While here, fix some potential concurrency problems in the interrupt handling code.
2010-06-23 22:33:03 +00:00
int powerpc_bind_intr(u_int irq, u_char cpu);
Add support for the BUS_CONFIG_INTR() method to the platform and to openpic(4). Make use of it in ocpbus(4). On the MPC85xxCDS, IRQ0:4 are active-low.
2008-03-07 22:08:43 +00:00
int powerpc_config_intr(int, enum intr_trigger, enum intr_polarity);
Allow PIC drivers to translate firmware sense codes for themselves. This is designed to replace the tables in dev/fdt/fdt_ARCH.c, but will not happen quite yet.
2013-10-24 15:37:32 +00:00
int powerpc_fw_config_intr(int irq, int sense_code);
Add interrupt handling support code. I've tried to make this fairly platform-independant as some PowerPC platforms may not have openpic-style interrupt controllers. This may not have the best performance but it works for now.
2002-07-09 11:12:20 +00:00
Add support for the Freescale dTSEC DPAA-based ethernet controller. Freescale's QorIQ line includes a new ethernet controller, based on their Datapath Acceleration Architecture (DPAA). This uses a combination of a Frame manager, Buffer manager, and Queue manager to improve performance across all interfaces by being able to pass data directly between hardware acceleration interfaces. As part of this import, Freescale's Netcomm Software (ncsw) driver is imported. This was an attempt by Freescale to create an OS-agnostic sub-driver for managing the hardware, using shims to interface to the OS-specific APIs. This work was abandoned, and Freescale's primary work is in the Linux driver (dual BSD/GPL license). Hence, this was imported directly to sys/contrib, rather than going through the vendor area. Going forward, FreeBSD-specific changes may be made to the ncsw code, diverging from the upstream in potentially incompatible ways. An alternative could be to import the Linux driver itself, using the linuxKPI layer, as that would maintain parity with the vendor-maintained driver. However, the Linux driver has not been evaluated for reliability yet, and may have issues with the import, whereas the ncsw-based driver in this commit was completed by Semihalf 4 years ago, and is very stable. Other SoC modules based on DPAA, which could be added in the future: * Security and Encryption engine (SEC4.x, SEC5.x) * RAID engine Additional work to be done: * Implement polling mode * Test vlan support * Add support for the Pattern Matching Engine, which can do regular expression matching on packets. This driver has been tested on the P5020 QorIQ SoC. Others listed in the dtsec(4) manual page are expected to work as the same DPAA engine is included in all. Obtained from: Semihalf Relnotes: Yes Sponsored by: Alex Perez/Inertial Computing
2016-02-29 03:38:00 +00:00
void powerpc_intr_mask(u_int irq);
void powerpc_intr_unmask(u_int irq);
Add interrupt handling support code. I've tried to make this fairly platform-independant as some PowerPC platforms may not have openpic-style interrupt controllers. This may not have the best performance but it works for now.
2002-07-09 11:12:20 +00:00
#endif /* _MACHINE_INTR_MACHDEP_H_ */
Reference in New Issue Copy Permalink