2012-01-26 18:17:21 +00:00
|
|
|
/*-
|
Bring in LSI's latest mps(4) 6Gb SAS and WarpDrive driver, version
14.00.00.01-fbsd.
Their description of the changes is as follows:
1. Copyright contents has been changed in all respective .c
and .h files
2. Support for WRITE12 and READ12 for direct-io (warpdrive only)
has been added.
3. Driver has added checks to see if Drive has READ_CAP_16
support before sending it down to the device.
If SPC3_SID_PROTECT flag is set in the inquiry data, the
device supports protection information, and must support
the 16 byte read capacity command, otherwise continue without
sending read cap 16. This will optimize driver performance,
since it will not send READ_CAP_16 to the drive which does
not have support of READ_CAP_16.
4. With new approach, "MPTIOCTL_RESET_ADAPTER" IOCTL will not
use DELAY() which is busy loop implementation.
It will use <msleep> (Better way to sleep without busy
loop). Also from the HBA reset code path and some other
places, DELAY() is replaced with msleep() or "pause()",
which is based on sleep/wakeup style calls. Driver use
msleep()/pause() instead of DELAY based on CAN_SLEEP/NO_SLEEP
flags to avoid busy loop which is not required all the
time.e.a
a. While driver is getting loaded, driver calls most of the
commands with NO_SLEEP.
b. When Driver is functional and it needs Reinit of HBA,
CAN_SLEEP flag is used.
5. <mpslsi> driver is not Endian safe. It will not work on Big
Endian machines like Sparc and PowerPC platforms because it
assumes it is running on a Little Endian machine.
Driver code is modified such way that it does not assume CPU
arch is Little Endian.
a. All places where Driver interacts from HBA to Host, it
converts Little Endian format to CPU format.
b. All places where Driver interacts from Host to HBA, it
converts CPU format to Little Endian.
6. Findout memory leaks in FreeBSD Driver and resolve those,
such as memory leak in targ's luns creation/deletion.
Also added additional checks to see memory allocation
success/fail.
7. Add loginfo prints as debug message, i.e. When FW sends any
loginfo, Driver should print those as debug message.
This will help for debugging purpose.
8. There is possibility to get config request timeout. Current
driver is able to detect config request timetout, but it does
not do anything on config_request timeout. Driver should
call mps_reinit() if any request_poll (which is called as
part of config_request) is time out.
9. cdb length check is required for 32 byte CDB. Add correct mpi
control value for 32 bit CDB as below while submitting SCSI IO
Request to controller.
mpi_control |= 4 << MPI2_SCSIIO_CONTROL_ADDCDBLEN_SHIFT;
10. Check the actual status of Message unit reset
(mps_message_unit_reset).Previously FreeBSD Driver just writes
MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET and never check the ack
(it just wait for 50 millisecond). So, Driver now check the
status of "MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET" after writing
it to the FW.
Now it also checking for whether doorbell ack uses msleep with
proper sleep flags, instead of <DELAY>.
11. Previously CAM does not detect Multi-Lun Devices. In order to
detect Multi-Lun Devices by CAM the driver needs following change
set:
a. There is "max_lun" field which Driver need to set based on
hw/fw support. Currently LSI released driver does not set
this field.
b. Default of "max_lun" should not be 0 in OS, but it is
currently set to 0 in CAM layer.
c. Export max_lun capacity to 255
12. Driver will not reset target info after port enable complete and
also do Device removal when Device remove from FW. The detail
description is as follows
a. When Driver receive WD PD add events, it will add all
information in driver local data structure.
b. Only for WD, we have below checks after port enable
completes, where driver clear off all information retrieved
at #1.
if ((sc->WD_available &&
(sc->WD_hide_expose == MPS_WD_HIDE_ALWAYS)) ||
(sc->WD_valid_config && (sc->WD_hide_expose ==
MPS_WD_HIDE_IF_VOLUME)) {
// clear off target data structure.
}
It is mainly not to attach PDs to OS.
FreeBSD does bus rescan as older Parallel scsi style. So Driver
needs to handle which Drive is visible to OS. That is a reason
we have to clear off targ information for PDs.
Again, above logic was implemented long time ago. Similar concept
we have for non-wd also. For that, LSI have introduced different
logic to hide PDs.
Eventually, because of above gap, when Phy goes offline, we
observe below failure. That is what Driver is not doing complete
removal of device with FW. (which was pointed by Scott)
Apr 5 02:39:24 Freebsd7 kernel: mpslsi0: mpssas_prepare_remove
Apr 5 02:39:24 Freebsd7 kernel: mpssas_prepare_remove 497 : invalid handle 0xe
Now Driver will not reset target info after port enable complete
and also will do Device removal when Device remove from FW.
13. Returning "CAM_SEL_TIMEOUT" instead of "CAM_TID_INVALID"
error code on request to the Target IDs that have no devices
conected at that moment. As if "CAM_TID_INVALID" error code
is returned to the CAM Layaer then it results in a huge chain
of errors in verbose kernel messages on boot and every
hot-plug event.
Submitted by: Sreekanth Reddy <Sreekanth.Reddy@lsi.com>
MFC after: 3 days
2012-06-28 03:48:54 +00:00
|
|
|
* Copyright (c) 2011, 2012 LSI Corp.
|
2012-01-26 18:17:21 +00:00
|
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|
* All rights reserved.
|
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
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* SUCH DAMAGE.
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*
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* LSI MPT-Fusion Host Adapter FreeBSD
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*
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* $FreeBSD$
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*/
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|
2010-09-10 15:03:56 +00:00
|
|
|
/*
|
Bring in LSI's latest mps(4) 6Gb SAS and WarpDrive driver, version
14.00.00.01-fbsd.
Their description of the changes is as follows:
1. Copyright contents has been changed in all respective .c
and .h files
2. Support for WRITE12 and READ12 for direct-io (warpdrive only)
has been added.
3. Driver has added checks to see if Drive has READ_CAP_16
support before sending it down to the device.
If SPC3_SID_PROTECT flag is set in the inquiry data, the
device supports protection information, and must support
the 16 byte read capacity command, otherwise continue without
sending read cap 16. This will optimize driver performance,
since it will not send READ_CAP_16 to the drive which does
not have support of READ_CAP_16.
4. With new approach, "MPTIOCTL_RESET_ADAPTER" IOCTL will not
use DELAY() which is busy loop implementation.
It will use <msleep> (Better way to sleep without busy
loop). Also from the HBA reset code path and some other
places, DELAY() is replaced with msleep() or "pause()",
which is based on sleep/wakeup style calls. Driver use
msleep()/pause() instead of DELAY based on CAN_SLEEP/NO_SLEEP
flags to avoid busy loop which is not required all the
time.e.a
a. While driver is getting loaded, driver calls most of the
commands with NO_SLEEP.
b. When Driver is functional and it needs Reinit of HBA,
CAN_SLEEP flag is used.
5. <mpslsi> driver is not Endian safe. It will not work on Big
Endian machines like Sparc and PowerPC platforms because it
assumes it is running on a Little Endian machine.
Driver code is modified such way that it does not assume CPU
arch is Little Endian.
a. All places where Driver interacts from HBA to Host, it
converts Little Endian format to CPU format.
b. All places where Driver interacts from Host to HBA, it
converts CPU format to Little Endian.
6. Findout memory leaks in FreeBSD Driver and resolve those,
such as memory leak in targ's luns creation/deletion.
Also added additional checks to see memory allocation
success/fail.
7. Add loginfo prints as debug message, i.e. When FW sends any
loginfo, Driver should print those as debug message.
This will help for debugging purpose.
8. There is possibility to get config request timeout. Current
driver is able to detect config request timetout, but it does
not do anything on config_request timeout. Driver should
call mps_reinit() if any request_poll (which is called as
part of config_request) is time out.
9. cdb length check is required for 32 byte CDB. Add correct mpi
control value for 32 bit CDB as below while submitting SCSI IO
Request to controller.
mpi_control |= 4 << MPI2_SCSIIO_CONTROL_ADDCDBLEN_SHIFT;
10. Check the actual status of Message unit reset
(mps_message_unit_reset).Previously FreeBSD Driver just writes
MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET and never check the ack
(it just wait for 50 millisecond). So, Driver now check the
status of "MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET" after writing
it to the FW.
Now it also checking for whether doorbell ack uses msleep with
proper sleep flags, instead of <DELAY>.
11. Previously CAM does not detect Multi-Lun Devices. In order to
detect Multi-Lun Devices by CAM the driver needs following change
set:
a. There is "max_lun" field which Driver need to set based on
hw/fw support. Currently LSI released driver does not set
this field.
b. Default of "max_lun" should not be 0 in OS, but it is
currently set to 0 in CAM layer.
c. Export max_lun capacity to 255
12. Driver will not reset target info after port enable complete and
also do Device removal when Device remove from FW. The detail
description is as follows
a. When Driver receive WD PD add events, it will add all
information in driver local data structure.
b. Only for WD, we have below checks after port enable
completes, where driver clear off all information retrieved
at #1.
if ((sc->WD_available &&
(sc->WD_hide_expose == MPS_WD_HIDE_ALWAYS)) ||
(sc->WD_valid_config && (sc->WD_hide_expose ==
MPS_WD_HIDE_IF_VOLUME)) {
// clear off target data structure.
}
It is mainly not to attach PDs to OS.
FreeBSD does bus rescan as older Parallel scsi style. So Driver
needs to handle which Drive is visible to OS. That is a reason
we have to clear off targ information for PDs.
Again, above logic was implemented long time ago. Similar concept
we have for non-wd also. For that, LSI have introduced different
logic to hide PDs.
Eventually, because of above gap, when Phy goes offline, we
observe below failure. That is what Driver is not doing complete
removal of device with FW. (which was pointed by Scott)
Apr 5 02:39:24 Freebsd7 kernel: mpslsi0: mpssas_prepare_remove
Apr 5 02:39:24 Freebsd7 kernel: mpssas_prepare_remove 497 : invalid handle 0xe
Now Driver will not reset target info after port enable complete
and also will do Device removal when Device remove from FW.
13. Returning "CAM_SEL_TIMEOUT" instead of "CAM_TID_INVALID"
error code on request to the Target IDs that have no devices
conected at that moment. As if "CAM_TID_INVALID" error code
is returned to the CAM Layaer then it results in a huge chain
of errors in verbose kernel messages on boot and every
hot-plug event.
Submitted by: Sreekanth Reddy <Sreekanth.Reddy@lsi.com>
MFC after: 3 days
2012-06-28 03:48:54 +00:00
|
|
|
* Copyright (c) 2000-2012 LSI Corporation.
|
2010-09-10 15:03:56 +00:00
|
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|
*
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*
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* Name: mpi2_targ.h
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* Title: MPI Target mode messages and structures
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* Creation Date: September 8, 2006
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*
|
2012-01-26 18:17:21 +00:00
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* mpi2_targ.h Version: 02.00.04
|
2010-09-10 15:03:56 +00:00
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*
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* Version History
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* ---------------
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*
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* Date Version Description
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* -------- -------- ------------------------------------------------------
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* 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
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* 08-31-07 02.00.01 Added Command Buffer Data Location Address Space bits to
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* BufferPostFlags field of CommandBufferPostBase Request.
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* 02-29-08 02.00.02 Modified various names to make them 32-character unique.
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* 10-02-08 02.00.03 Removed NextCmdBufferOffset from
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* MPI2_TARGET_CMD_BUF_POST_BASE_REQUEST.
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* Target Status Send Request only takes a single SGE for
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* response data.
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2012-01-26 18:17:21 +00:00
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* 02-10-10 02.00.04 Added comment to MPI2_TARGET_SSP_RSP_IU structure.
|
2010-09-10 15:03:56 +00:00
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* --------------------------------------------------------------------------
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*/
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#ifndef MPI2_TARG_H
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#define MPI2_TARG_H
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/******************************************************************************
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*
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* SCSI Target Messages
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*
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*******************************************************************************/
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/****************************************************************************
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* Target Command Buffer Post Base Request
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****************************************************************************/
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typedef struct _MPI2_TARGET_CMD_BUF_POST_BASE_REQUEST
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{
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U8 BufferPostFlags; /* 0x00 */
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U8 Reserved1; /* 0x01 */
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U8 ChainOffset; /* 0x02 */
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U8 Function; /* 0x03 */
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U16 TotalCmdBuffers; /* 0x04 */
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U8 Reserved; /* 0x06 */
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U8 MsgFlags; /* 0x07 */
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U8 VP_ID; /* 0x08 */
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U8 VF_ID; /* 0x09 */
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U16 Reserved2; /* 0x0A */
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U32 Reserved3; /* 0x0C */
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U16 CmdBufferLength; /* 0x10 */
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U16 Reserved4; /* 0x12 */
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U32 BaseAddressLow; /* 0x14 */
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U32 BaseAddressHigh; /* 0x18 */
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} MPI2_TARGET_CMD_BUF_POST_BASE_REQUEST,
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MPI2_POINTER PTR_MPI2_TARGET_CMD_BUF_POST_BASE_REQUEST,
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Mpi2TargetCmdBufferPostBaseRequest_t,
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MPI2_POINTER pMpi2TargetCmdBufferPostBaseRequest_t;
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/* values for the BufferPostflags field */
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#define MPI2_CMD_BUF_POST_BASE_ADDRESS_SPACE_MASK (0x0C)
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#define MPI2_CMD_BUF_POST_BASE_SYSTEM_ADDRESS_SPACE (0x00)
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#define MPI2_CMD_BUF_POST_BASE_IOCDDR_ADDRESS_SPACE (0x04)
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#define MPI2_CMD_BUF_POST_BASE_IOCPLB_ADDRESS_SPACE (0x08)
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#define MPI2_CMD_BUF_POST_BASE_IOCPLBNTA_ADDRESS_SPACE (0x0C)
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#define MPI2_CMD_BUF_POST_BASE_FLAGS_AUTO_POST_ALL (0x01)
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/****************************************************************************
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* Target Command Buffer Post List Request
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****************************************************************************/
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typedef struct _MPI2_TARGET_CMD_BUF_POST_LIST_REQUEST
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{
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U16 Reserved; /* 0x00 */
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U8 ChainOffset; /* 0x02 */
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U8 Function; /* 0x03 */
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U16 CmdBufferCount; /* 0x04 */
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U8 Reserved1; /* 0x06 */
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U8 MsgFlags; /* 0x07 */
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U8 VP_ID; /* 0x08 */
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U8 VF_ID; /* 0x09 */
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U16 Reserved2; /* 0x0A */
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U32 Reserved3; /* 0x0C */
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U16 IoIndex[2]; /* 0x10 */
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} MPI2_TARGET_CMD_BUF_POST_LIST_REQUEST,
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MPI2_POINTER PTR_MPI2_TARGET_CMD_BUF_POST_LIST_REQUEST,
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Mpi2TargetCmdBufferPostListRequest_t,
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MPI2_POINTER pMpi2TargetCmdBufferPostListRequest_t;
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/****************************************************************************
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* Target Command Buffer Post Base List Reply
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****************************************************************************/
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typedef struct _MPI2_TARGET_BUF_POST_BASE_LIST_REPLY
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{
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U8 Flags; /* 0x00 */
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U8 Reserved; /* 0x01 */
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U8 MsgLength; /* 0x02 */
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U8 Function; /* 0x03 */
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U16 Reserved1; /* 0x04 */
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U8 Reserved2; /* 0x06 */
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U8 MsgFlags; /* 0x07 */
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U8 VP_ID; /* 0x08 */
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U8 VF_ID; /* 0x09 */
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U16 Reserved3; /* 0x0A */
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U16 Reserved4; /* 0x0C */
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U16 IOCStatus; /* 0x0E */
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U32 IOCLogInfo; /* 0x10 */
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U16 IoIndex; /* 0x14 */
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U16 Reserved5; /* 0x16 */
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U32 Reserved6; /* 0x18 */
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} MPI2_TARGET_BUF_POST_BASE_LIST_REPLY,
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MPI2_POINTER PTR_MPI2_TARGET_BUF_POST_BASE_LIST_REPLY,
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Mpi2TargetCmdBufferPostBaseListReply_t,
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MPI2_POINTER pMpi2TargetCmdBufferPostBaseListReply_t;
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/* Flags defines */
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#define MPI2_CMD_BUF_POST_REPLY_IOINDEX_VALID (0x01)
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/****************************************************************************
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* Command Buffer Formats (with 16 byte CDB)
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****************************************************************************/
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typedef struct _MPI2_TARGET_SSP_CMD_BUFFER
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{
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U8 FrameType; /* 0x00 */
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U8 Reserved1; /* 0x01 */
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U16 InitiatorConnectionTag; /* 0x02 */
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U32 HashedSourceSASAddress; /* 0x04 */
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U16 Reserved2; /* 0x08 */
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U16 Flags; /* 0x0A */
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U32 Reserved3; /* 0x0C */
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U16 Tag; /* 0x10 */
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U16 TargetPortTransferTag; /* 0x12 */
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U32 DataOffset; /* 0x14 */
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/* COMMAND information unit starts here */
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U8 LogicalUnitNumber[8]; /* 0x18 */
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U8 Reserved4; /* 0x20 */
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U8 TaskAttribute; /* lower 3 bits */ /* 0x21 */
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U8 Reserved5; /* 0x22 */
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U8 AdditionalCDBLength; /* upper 5 bits */ /* 0x23 */
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U8 CDB[16]; /* 0x24 */
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/* Additional CDB bytes extend past the CDB field */
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} MPI2_TARGET_SSP_CMD_BUFFER, MPI2_POINTER PTR_MPI2_TARGET_SSP_CMD_BUFFER,
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Mpi2TargetSspCmdBuffer, MPI2_POINTER pMp2iTargetSspCmdBuffer;
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typedef struct _MPI2_TARGET_SSP_TASK_BUFFER
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{
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|
|
U8 FrameType; /* 0x00 */
|
|
|
|
|
U8 Reserved1; /* 0x01 */
|
|
|
|
|
U16 InitiatorConnectionTag; /* 0x02 */
|
|
|
|
|
U32 HashedSourceSASAddress; /* 0x04 */
|
|
|
|
|
U16 Reserved2; /* 0x08 */
|
|
|
|
|
U16 Flags; /* 0x0A */
|
|
|
|
|
U32 Reserved3; /* 0x0C */
|
|
|
|
|
U16 Tag; /* 0x10 */
|
|
|
|
|
U16 TargetPortTransferTag; /* 0x12 */
|
|
|
|
|
U32 DataOffset; /* 0x14 */
|
|
|
|
|
/* TASK information unit starts here */
|
|
|
|
|
U8 LogicalUnitNumber[8]; /* 0x18 */
|
|
|
|
|
U16 Reserved4; /* 0x20 */
|
|
|
|
|
U8 TaskManagementFunction; /* 0x22 */
|
|
|
|
|
U8 Reserved5; /* 0x23 */
|
|
|
|
|
U16 ManagedTaskTag; /* 0x24 */
|
|
|
|
|
U16 Reserved6; /* 0x26 */
|
|
|
|
|
U32 Reserved7; /* 0x28 */
|
|
|
|
|
U32 Reserved8; /* 0x2C */
|
|
|
|
|
U32 Reserved9; /* 0x30 */
|
|
|
|
|
} MPI2_TARGET_SSP_TASK_BUFFER, MPI2_POINTER PTR_MPI2_TARGET_SSP_TASK_BUFFER,
|
|
|
|
|
Mpi2TargetSspTaskBuffer, MPI2_POINTER pMpi2TargetSspTaskBuffer;
|
|
|
|
|
|
|
|
|
|
/* mask and shift for HashedSourceSASAddress field */
|
|
|
|
|
#define MPI2_TARGET_HASHED_SAS_ADDRESS_MASK (0xFFFFFF00)
|
|
|
|
|
#define MPI2_TARGET_HASHED_SAS_ADDRESS_SHIFT (8)
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
|
* Target Assist Request
|
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
|
|
typedef struct _MPI2_TARGET_ASSIST_REQUEST
|
|
|
|
|
{
|
|
|
|
|
U8 Reserved1; /* 0x00 */
|
|
|
|
|
U8 TargetAssistFlags; /* 0x01 */
|
|
|
|
|
U8 ChainOffset; /* 0x02 */
|
|
|
|
|
U8 Function; /* 0x03 */
|
|
|
|
|
U16 QueueTag; /* 0x04 */
|
|
|
|
|
U8 Reserved2; /* 0x06 */
|
|
|
|
|
U8 MsgFlags; /* 0x07 */
|
|
|
|
|
U8 VP_ID; /* 0x08 */
|
|
|
|
|
U8 VF_ID; /* 0x09 */
|
|
|
|
|
U16 Reserved3; /* 0x0A */
|
|
|
|
|
U16 IoIndex; /* 0x0C */
|
|
|
|
|
U16 InitiatorConnectionTag; /* 0x0E */
|
|
|
|
|
U16 SGLFlags; /* 0x10 */
|
|
|
|
|
U8 SequenceNumber; /* 0x12 */
|
|
|
|
|
U8 Reserved4; /* 0x13 */
|
|
|
|
|
U8 SGLOffset0; /* 0x14 */
|
|
|
|
|
U8 SGLOffset1; /* 0x15 */
|
|
|
|
|
U8 SGLOffset2; /* 0x16 */
|
|
|
|
|
U8 SGLOffset3; /* 0x17 */
|
|
|
|
|
U32 SkipCount; /* 0x18 */
|
|
|
|
|
U32 DataLength; /* 0x1C */
|
|
|
|
|
U32 BidirectionalDataLength; /* 0x20 */
|
|
|
|
|
U16 IoFlags; /* 0x24 */
|
|
|
|
|
U16 EEDPFlags; /* 0x26 */
|
|
|
|
|
U32 EEDPBlockSize; /* 0x28 */
|
|
|
|
|
U32 SecondaryReferenceTag; /* 0x2C */
|
|
|
|
|
U16 SecondaryApplicationTag; /* 0x30 */
|
|
|
|
|
U16 ApplicationTagTranslationMask; /* 0x32 */
|
|
|
|
|
U32 PrimaryReferenceTag; /* 0x34 */
|
|
|
|
|
U16 PrimaryApplicationTag; /* 0x38 */
|
|
|
|
|
U16 PrimaryApplicationTagMask; /* 0x3A */
|
|
|
|
|
U32 RelativeOffset; /* 0x3C */
|
|
|
|
|
U32 Reserved5; /* 0x40 */
|
|
|
|
|
U32 Reserved6; /* 0x44 */
|
|
|
|
|
U32 Reserved7; /* 0x48 */
|
|
|
|
|
U32 Reserved8; /* 0x4C */
|
|
|
|
|
MPI2_SGE_IO_UNION SGL[1]; /* 0x50 */
|
|
|
|
|
} MPI2_TARGET_ASSIST_REQUEST, MPI2_POINTER PTR_MPI2_TARGET_ASSIST_REQUEST,
|
|
|
|
|
Mpi2TargetAssistRequest_t, MPI2_POINTER pMpi2TargetAssistRequest_t;
|
|
|
|
|
|
|
|
|
|
/* Target Assist TargetAssistFlags bits */
|
|
|
|
|
|
|
|
|
|
#define MPI2_TARGET_ASSIST_FLAGS_REPOST_CMD_BUFFER (0x80)
|
|
|
|
|
#define MPI2_TARGET_ASSIST_FLAGS_TLR (0x10)
|
|
|
|
|
#define MPI2_TARGET_ASSIST_FLAGS_RETRANSMIT (0x04)
|
|
|
|
|
#define MPI2_TARGET_ASSIST_FLAGS_AUTO_STATUS (0x02)
|
|
|
|
|
#define MPI2_TARGET_ASSIST_FLAGS_DATA_DIRECTION (0x01)
|
|
|
|
|
|
|
|
|
|
/* Target Assist SGLFlags bits */
|
|
|
|
|
|
|
|
|
|
/* base values for Data Location Address Space */
|
|
|
|
|
#define MPI2_TARGET_ASSIST_SGLFLAGS_ADDR_MASK (0x0C)
|
|
|
|
|
#define MPI2_TARGET_ASSIST_SGLFLAGS_SYSTEM_ADDR (0x00)
|
|
|
|
|
#define MPI2_TARGET_ASSIST_SGLFLAGS_IOCDDR_ADDR (0x04)
|
|
|
|
|
#define MPI2_TARGET_ASSIST_SGLFLAGS_IOCPLB_ADDR (0x08)
|
|
|
|
|
#define MPI2_TARGET_ASSIST_SGLFLAGS_PLBNTA_ADDR (0x0C)
|
|
|
|
|
|
|
|
|
|
/* base values for Type */
|
|
|
|
|
#define MPI2_TARGET_ASSIST_SGLFLAGS_TYPE_MASK (0x03)
|
|
|
|
|
#define MPI2_TARGET_ASSIST_SGLFLAGS_MPI_TYPE (0x00)
|
|
|
|
|
#define MPI2_TARGET_ASSIST_SGLFLAGS_32IEEE_TYPE (0x01)
|
|
|
|
|
#define MPI2_TARGET_ASSIST_SGLFLAGS_64IEEE_TYPE (0x02)
|
|
|
|
|
|
|
|
|
|
/* shift values for each sub-field */
|
|
|
|
|
#define MPI2_TARGET_ASSIST_SGLFLAGS_SGL3_SHIFT (12)
|
|
|
|
|
#define MPI2_TARGET_ASSIST_SGLFLAGS_SGL2_SHIFT (8)
|
|
|
|
|
#define MPI2_TARGET_ASSIST_SGLFLAGS_SGL1_SHIFT (4)
|
|
|
|
|
#define MPI2_TARGET_ASSIST_SGLFLAGS_SGL0_SHIFT (0)
|
|
|
|
|
|
|
|
|
|
/* Target Assist IoFlags bits */
|
|
|
|
|
|
|
|
|
|
#define MPI2_TARGET_ASSIST_IOFLAGS_BIDIRECTIONAL (0x0800)
|
|
|
|
|
#define MPI2_TARGET_ASSIST_IOFLAGS_MULTICAST (0x0400)
|
|
|
|
|
#define MPI2_TARGET_ASSIST_IOFLAGS_RECEIVE_FIRST (0x0200)
|
|
|
|
|
|
|
|
|
|
/* Target Assist EEDPFlags bits */
|
|
|
|
|
|
|
|
|
|
#define MPI2_TA_EEDPFLAGS_INC_PRI_REFTAG (0x8000)
|
|
|
|
|
#define MPI2_TA_EEDPFLAGS_INC_SEC_REFTAG (0x4000)
|
|
|
|
|
#define MPI2_TA_EEDPFLAGS_INC_PRI_APPTAG (0x2000)
|
|
|
|
|
#define MPI2_TA_EEDPFLAGS_INC_SEC_APPTAG (0x1000)
|
|
|
|
|
|
|
|
|
|
#define MPI2_TA_EEDPFLAGS_CHECK_REFTAG (0x0400)
|
|
|
|
|
#define MPI2_TA_EEDPFLAGS_CHECK_APPTAG (0x0200)
|
|
|
|
|
#define MPI2_TA_EEDPFLAGS_CHECK_GUARD (0x0100)
|
|
|
|
|
|
|
|
|
|
#define MPI2_TA_EEDPFLAGS_PASSTHRU_REFTAG (0x0008)
|
|
|
|
|
|
|
|
|
|
#define MPI2_TA_EEDPFLAGS_MASK_OP (0x0007)
|
|
|
|
|
#define MPI2_TA_EEDPFLAGS_NOOP_OP (0x0000)
|
|
|
|
|
#define MPI2_TA_EEDPFLAGS_CHECK_OP (0x0001)
|
|
|
|
|
#define MPI2_TA_EEDPFLAGS_STRIP_OP (0x0002)
|
|
|
|
|
#define MPI2_TA_EEDPFLAGS_CHECK_REMOVE_OP (0x0003)
|
|
|
|
|
#define MPI2_TA_EEDPFLAGS_INSERT_OP (0x0004)
|
|
|
|
|
#define MPI2_TA_EEDPFLAGS_REPLACE_OP (0x0006)
|
|
|
|
|
#define MPI2_TA_EEDPFLAGS_CHECK_REGEN_OP (0x0007)
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
|
* Target Status Send Request
|
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
|
|
typedef struct _MPI2_TARGET_STATUS_SEND_REQUEST
|
|
|
|
|
{
|
|
|
|
|
U8 Reserved1; /* 0x00 */
|
|
|
|
|
U8 StatusFlags; /* 0x01 */
|
|
|
|
|
U8 ChainOffset; /* 0x02 */
|
|
|
|
|
U8 Function; /* 0x03 */
|
|
|
|
|
U16 QueueTag; /* 0x04 */
|
|
|
|
|
U8 Reserved2; /* 0x06 */
|
|
|
|
|
U8 MsgFlags; /* 0x07 */
|
|
|
|
|
U8 VP_ID; /* 0x08 */
|
|
|
|
|
U8 VF_ID; /* 0x09 */
|
|
|
|
|
U16 Reserved3; /* 0x0A */
|
|
|
|
|
U16 IoIndex; /* 0x0C */
|
|
|
|
|
U16 InitiatorConnectionTag; /* 0x0E */
|
|
|
|
|
U16 SGLFlags; /* 0x10 */
|
|
|
|
|
U16 Reserved4; /* 0x12 */
|
|
|
|
|
U8 SGLOffset0; /* 0x14 */
|
|
|
|
|
U8 Reserved5; /* 0x15 */
|
|
|
|
|
U16 Reserved6; /* 0x16 */
|
|
|
|
|
U32 Reserved7; /* 0x18 */
|
|
|
|
|
U32 Reserved8; /* 0x1C */
|
|
|
|
|
MPI2_SIMPLE_SGE_UNION StatusDataSGE; /* 0x20 */
|
|
|
|
|
} MPI2_TARGET_STATUS_SEND_REQUEST,
|
|
|
|
|
MPI2_POINTER PTR_MPI2_TARGET_STATUS_SEND_REQUEST,
|
|
|
|
|
Mpi2TargetStatusSendRequest_t, MPI2_POINTER pMpi2TargetStatusSendRequest_t;
|
|
|
|
|
|
|
|
|
|
/* Target Status Send StatusFlags bits */
|
|
|
|
|
|
|
|
|
|
#define MPI2_TSS_FLAGS_REPOST_CMD_BUFFER (0x80)
|
|
|
|
|
#define MPI2_TSS_FLAGS_RETRANSMIT (0x04)
|
|
|
|
|
#define MPI2_TSS_FLAGS_AUTO_GOOD_STATUS (0x01)
|
|
|
|
|
|
|
|
|
|
/* Target Status Send SGLFlags bits */
|
|
|
|
|
/* Data Location Address Space */
|
|
|
|
|
#define MPI2_TSS_SGLFLAGS_ADDR_MASK (0x0C)
|
|
|
|
|
#define MPI2_TSS_SGLFLAGS_SYSTEM_ADDR (0x00)
|
|
|
|
|
#define MPI2_TSS_SGLFLAGS_IOCDDR_ADDR (0x04)
|
|
|
|
|
#define MPI2_TSS_SGLFLAGS_IOCPLB_ADDR (0x08)
|
|
|
|
|
#define MPI2_TSS_SGLFLAGS_IOCPLBNTA_ADDR (0x0C)
|
|
|
|
|
/* Type */
|
|
|
|
|
#define MPI2_TSS_SGLFLAGS_TYPE_MASK (0x03)
|
|
|
|
|
#define MPI2_TSS_SGLFLAGS_MPI_TYPE (0x00)
|
|
|
|
|
#define MPI2_TSS_SGLFLAGS_IEEE32_TYPE (0x01)
|
|
|
|
|
#define MPI2_TSS_SGLFLAGS_IEEE64_TYPE (0x02)
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* NOTE: The SSP status IU is big-endian. When used on a little-endian system,
|
|
|
|
|
* this structure properly orders the bytes.
|
|
|
|
|
*/
|
|
|
|
|
typedef struct _MPI2_TARGET_SSP_RSP_IU
|
|
|
|
|
{
|
|
|
|
|
U32 Reserved0[6]; /* reserved for SSP header */ /* 0x00 */
|
2012-01-26 18:17:21 +00:00
|
|
|
|
2010-09-10 15:03:56 +00:00
|
|
|
/* start of RESPONSE information unit */
|
|
|
|
|
U32 Reserved1; /* 0x18 */
|
|
|
|
|
U32 Reserved2; /* 0x1C */
|
|
|
|
|
U16 Reserved3; /* 0x20 */
|
|
|
|
|
U8 DataPres; /* lower 2 bits */ /* 0x22 */
|
|
|
|
|
U8 Status; /* 0x23 */
|
|
|
|
|
U32 Reserved4; /* 0x24 */
|
|
|
|
|
U32 SenseDataLength; /* 0x28 */
|
|
|
|
|
U32 ResponseDataLength; /* 0x2C */
|
2012-01-26 18:17:21 +00:00
|
|
|
|
|
|
|
|
/* start of Response or Sense Data (size may vary dynamically) */
|
2010-09-10 15:03:56 +00:00
|
|
|
U8 ResponseSenseData[4]; /* 0x30 */
|
|
|
|
|
} MPI2_TARGET_SSP_RSP_IU, MPI2_POINTER PTR_MPI2_TARGET_SSP_RSP_IU,
|
|
|
|
|
Mpi2TargetSspRspIu_t, MPI2_POINTER pMpi2TargetSspRspIu_t;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
|
* Target Standard Reply - used with Target Assist or Target Status Send
|
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
|
|
typedef struct _MPI2_TARGET_STANDARD_REPLY
|
|
|
|
|
{
|
|
|
|
|
U16 Reserved; /* 0x00 */
|
|
|
|
|
U8 MsgLength; /* 0x02 */
|
|
|
|
|
U8 Function; /* 0x03 */
|
|
|
|
|
U16 Reserved1; /* 0x04 */
|
|
|
|
|
U8 Reserved2; /* 0x06 */
|
|
|
|
|
U8 MsgFlags; /* 0x07 */
|
|
|
|
|
U8 VP_ID; /* 0x08 */
|
|
|
|
|
U8 VF_ID; /* 0x09 */
|
|
|
|
|
U16 Reserved3; /* 0x0A */
|
|
|
|
|
U16 Reserved4; /* 0x0C */
|
|
|
|
|
U16 IOCStatus; /* 0x0E */
|
|
|
|
|
U32 IOCLogInfo; /* 0x10 */
|
|
|
|
|
U16 IoIndex; /* 0x14 */
|
|
|
|
|
U16 Reserved5; /* 0x16 */
|
|
|
|
|
U32 TransferCount; /* 0x18 */
|
|
|
|
|
U32 BidirectionalTransferCount; /* 0x1C */
|
|
|
|
|
} MPI2_TARGET_STANDARD_REPLY, MPI2_POINTER PTR_MPI2_TARGET_STANDARD_REPLY,
|
|
|
|
|
Mpi2TargetErrorReply_t, MPI2_POINTER pMpi2TargetErrorReply_t;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
|
* Target Mode Abort Request
|
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
|
|
typedef struct _MPI2_TARGET_MODE_ABORT_REQUEST
|
|
|
|
|
{
|
|
|
|
|
U8 AbortType; /* 0x00 */
|
|
|
|
|
U8 Reserved1; /* 0x01 */
|
|
|
|
|
U8 ChainOffset; /* 0x02 */
|
|
|
|
|
U8 Function; /* 0x03 */
|
|
|
|
|
U16 Reserved2; /* 0x04 */
|
|
|
|
|
U8 Reserved3; /* 0x06 */
|
|
|
|
|
U8 MsgFlags; /* 0x07 */
|
|
|
|
|
U8 VP_ID; /* 0x08 */
|
|
|
|
|
U8 VF_ID; /* 0x09 */
|
|
|
|
|
U16 Reserved4; /* 0x0A */
|
|
|
|
|
U16 IoIndexToAbort; /* 0x0C */
|
|
|
|
|
U16 Reserved6; /* 0x0E */
|
|
|
|
|
U32 MidToAbort; /* 0x10 */
|
|
|
|
|
} MPI2_TARGET_MODE_ABORT, MPI2_POINTER PTR_MPI2_TARGET_MODE_ABORT,
|
|
|
|
|
Mpi2TargetModeAbort_t, MPI2_POINTER pMpi2TargetModeAbort_t;
|
|
|
|
|
|
|
|
|
|
/* Target Mode Abort AbortType values */
|
|
|
|
|
|
|
|
|
|
#define MPI2_TARGET_MODE_ABORT_ALL_CMD_BUFFERS (0x00)
|
|
|
|
|
#define MPI2_TARGET_MODE_ABORT_ALL_IO (0x01)
|
|
|
|
|
#define MPI2_TARGET_MODE_ABORT_EXACT_IO (0x02)
|
|
|
|
|
#define MPI2_TARGET_MODE_ABORT_EXACT_IO_REQUEST (0x03)
|
|
|
|
|
#define MPI2_TARGET_MODE_ABORT_IO_REQUEST_AND_IO (0x04)
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
|
* Target Mode Abort Reply
|
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
|
|
typedef struct _MPI2_TARGET_MODE_ABORT_REPLY
|
|
|
|
|
{
|
|
|
|
|
U16 Reserved; /* 0x00 */
|
|
|
|
|
U8 MsgLength; /* 0x02 */
|
|
|
|
|
U8 Function; /* 0x03 */
|
|
|
|
|
U16 Reserved1; /* 0x04 */
|
|
|
|
|
U8 Reserved2; /* 0x06 */
|
|
|
|
|
U8 MsgFlags; /* 0x07 */
|
|
|
|
|
U8 VP_ID; /* 0x08 */
|
|
|
|
|
U8 VF_ID; /* 0x09 */
|
|
|
|
|
U16 Reserved3; /* 0x0A */
|
|
|
|
|
U16 Reserved4; /* 0x0C */
|
|
|
|
|
U16 IOCStatus; /* 0x0E */
|
|
|
|
|
U32 IOCLogInfo; /* 0x10 */
|
|
|
|
|
U32 AbortCount; /* 0x14 */
|
|
|
|
|
} MPI2_TARGET_MODE_ABORT_REPLY, MPI2_POINTER PTR_MPI2_TARGET_MODE_ABORT_REPLY,
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Mpi2TargetModeAbortReply_t, MPI2_POINTER pMpi2TargetModeAbortReply_t;
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#endif
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