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freebsd-dev/sys/arm/include/cpufunc.h

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Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
/* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */
Start all license statements with /*-
2005-01-05 21:58:49 +00:00
/*-
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
* Copyright (c) 1997 Mark Brinicombe.
* Copyright (c) 1997 Causality Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Causality Limited.
* 4. The name of Causality Limited may not be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RiscBSD kernel project
*
* cpufunc.h
*
* Prototypes for cpu, mmu and tlb related functions.
*
* $FreeBSD$
*/
#ifndef _MACHINE_CPUFUNC_H_
#define _MACHINE_CPUFUNC_H_
#ifdef _KERNEL
#include <sys/types.h>
#include <machine/cpuconf.h>
Implement a stub breakpoint().
2004-07-12 21:20:38 +00:00
#include <machine/katelib.h> /* For in[bwl] and out[bwl] */
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
Implement a stub breakpoint().
2004-07-12 21:20:38 +00:00
static __inline void
breakpoint(void)
{
Implement enough to be able to enter and leave DDB.
2004-11-20 16:52:10 +00:00
__asm(".word 0xe7ffffff");
Implement a stub breakpoint().
2004-07-12 21:20:38 +00:00
}
Nuke disable_intr() and enable_intr(), as it already exists elsewhere.
2004-07-20 22:38:46 +00:00
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
struct cpu_functions {
/* CPU functions */
u_int (*cf_id) (void);
void (*cf_cpwait) (void);
/* MMU functions */
u_int (*cf_control) (u_int bic, u_int eor);
void (*cf_domains) (u_int domains);
void (*cf_setttb) (u_int ttb);
u_int (*cf_faultstatus) (void);
u_int (*cf_faultaddress) (void);
/* TLB functions */
void (*cf_tlb_flushID) (void);
void (*cf_tlb_flushID_SE) (u_int va);
void (*cf_tlb_flushI) (void);
void (*cf_tlb_flushI_SE) (u_int va);
void (*cf_tlb_flushD) (void);
void (*cf_tlb_flushD_SE) (u_int va);
/*
* Cache operations:
*
* We define the following primitives:
*
* icache_sync_all Synchronize I-cache
* icache_sync_range Synchronize I-cache range
*
* dcache_wbinv_all Write-back and Invalidate D-cache
* dcache_wbinv_range Write-back and Invalidate D-cache range
* dcache_inv_range Invalidate D-cache range
* dcache_wb_range Write-back D-cache range
*
* idcache_wbinv_all Write-back and Invalidate D-cache,
* Invalidate I-cache
* idcache_wbinv_range Write-back and Invalidate D-cache,
* Invalidate I-cache range
*
* Note that the ARM term for "write-back" is "clean". We use
* the term "write-back" since it's a more common way to describe
* the operation.
*
* There are some rules that must be followed:
*
Add a new cache maintenance function, idcache_inv_all, to the table, and implementations for each of the chips we support. Most chips up through armv6 can use the armv4 implementation which has a single coprocessor opcode for this operation. The rather more complex armv7 implementation comes from netbsd.
2014-02-24 01:41:58 +00:00
* ID-cache Invalidate All:
* Unlike other functions, this one must never write back.
* It is used to intialize the MMU when it is in an unknown
* state (such as when it may have lines tagged as valid
* that belong to a previous set of mappings).
*
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
* I-cache Synch (all or range):
* The goal is to synchronize the instruction stream,
* so you may beed to write-back dirty D-cache blocks
* first. If a range is requested, and you can't
* synchronize just a range, you have to hit the whole
* thing.
*
* D-cache Write-Back and Invalidate range:
* If you can't WB-Inv a range, you must WB-Inv the
* entire D-cache.
*
* D-cache Invalidate:
* If you can't Inv the D-cache, you must Write-Back
* and Invalidate. Code that uses this operation
* MUST NOT assume that the D-cache will not be written
* back to memory.
*
* D-cache Write-Back:
* If you can't Write-back without doing an Inv,
* that's fine. Then treat this as a WB-Inv.
* Skipping the invalidate is merely an optimization.
*
* All operations:
* Valid virtual addresses must be passed to each
* cache operation.
*/
void (*cf_icache_sync_all) (void);
void (*cf_icache_sync_range) (vm_offset_t, vm_size_t);
void (*cf_dcache_wbinv_all) (void);
void (*cf_dcache_wbinv_range) (vm_offset_t, vm_size_t);
void (*cf_dcache_inv_range) (vm_offset_t, vm_size_t);
void (*cf_dcache_wb_range) (vm_offset_t, vm_size_t);
Add a new cache maintenance function, idcache_inv_all, to the table, and implementations for each of the chips we support. Most chips up through armv6 can use the armv4 implementation which has a single coprocessor opcode for this operation. The rather more complex armv7 implementation comes from netbsd.
2014-02-24 01:41:58 +00:00
void (*cf_idcache_inv_all) (void);
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
void (*cf_idcache_wbinv_all) (void);
void (*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t);
Add a new set of functions to handle L2 cache. Make them no-op for every CPU except Xscale core 3. Approved by: re (blanket)
2007-07-27 14:39:41 +00:00
void (*cf_l2cache_wbinv_all) (void);
void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t);
void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t);
void (*cf_l2cache_wb_range) (vm_offset_t, vm_size_t);
Add cpu_l2cache_drain_writebuf(), use it to implement generic_bs_barrier(). On modern ARM SoCs the L2 cache controller sits between the CPU and the AXI bus, and most on-chip memory-mapped devices are on the AXI bus. We map the device registers using the 'Device' memory attribute, which means the memory is not cached, but writes to it are buffered. Ensuring that a write has made it all the way to a device may require that the L2 controller take some action. There is currently only one implementation of the new function, for the PL310 cache controller. It invokes a function that the controller manual calls "cache sync" but it actually has nothing to do with cache at all, it triggers a drain of all pending store buffer writes and it blocks until they complete. The sheeva and xscale L2 controllers (which predate the concept of Device memory) don't seem to have a corresponding function. It appears that the standard armv5 drain_writebuf function includes draining all the way through the L2 controller.
2014-05-11 04:24:57 +00:00
void (*cf_l2cache_drain_writebuf) (void);
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
/* Other functions */
void (*cf_flush_prefetchbuf) (void);
void (*cf_drain_writebuf) (void);
void (*cf_flush_brnchtgt_C) (void);
void (*cf_flush_brnchtgt_E) (u_int va);
void (*cf_sleep) (int mode);
/* Soft functions */
int (*cf_dataabt_fixup) (void *arg);
int (*cf_prefetchabt_fixup) (void *arg);
void (*cf_context_switch) (void);
Remove the bootconfig parsing. We never used it and always passed either an empty string or NULL to the setup functions that called into it.
2015-03-29 20:37:28 +00:00
void (*cf_setup) (void);
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
};
extern struct cpu_functions cpufuncs;
extern u_int cputype;
Initial version of DTrace on ARM32. Submitted by: Howard Su based on work by Oleksandr Tymoshenko Reviewed by: ian, andrew, rpaulo, markj
2015-02-10 19:41:30 +00:00
#define cpu_ident() cpufuncs.cf_id()
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
#define cpu_cpwait() cpufuncs.cf_cpwait()
#define cpu_control(c, e) cpufuncs.cf_control(c, e)
#define cpu_domains(d) cpufuncs.cf_domains(d)
#define cpu_setttb(t) cpufuncs.cf_setttb(t)
#define cpu_faultstatus() cpufuncs.cf_faultstatus()
#define cpu_faultaddress() cpufuncs.cf_faultaddress()
Merging projects/armv6, part 1 Cummulative patch of changes that are not vendor-specific: - ARMv6 and ARMv7 architecture support - ARM SMP support - VFP/Neon support - ARM Generic Interrupt Controller driver - Simplification of startup code for all platforms
2012-08-15 03:03:03 +00:00
#ifndef SMP
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
#define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID()
#define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e)
#define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI()
#define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e)
#define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD()
#define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e)
Merging projects/armv6, part 1 Cummulative patch of changes that are not vendor-specific: - ARMv6 and ARMv7 architecture support - ARM SMP support - VFP/Neon support - ARM Generic Interrupt Controller driver - Simplification of startup code for all platforms
2012-08-15 03:03:03 +00:00
#else
void tlb_broadcast(int);
Add identification and necessary type checks for Krait CPU cores. Krait CPU is used in Qualcomm Snapdragon S4 and Snapdragon 400/600/800 SoCs and has architectural similarities to ARM Cortex-A15. As for development boards IFC6400 series embedded boards from Inforce Computing uses Snapdragon S4 Pro/APQ8064. Approved by: stas (mentor)
2013-12-20 00:56:23 +00:00
#if defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) || defined(CPU_KRAIT)
Merging projects/armv6, part 1 Cummulative patch of changes that are not vendor-specific: - ARMv6 and ARMv7 architecture support - ARM SMP support - VFP/Neon support - ARM Generic Interrupt Controller driver - Simplification of startup code for all platforms
2012-08-15 03:03:03 +00:00
#define TLB_BROADCAST /* No need to explicitely send an IPI */
#else
#define TLB_BROADCAST tlb_broadcast(7)
#endif
#define cpu_tlb_flushID() do { \
cpufuncs.cf_tlb_flushID(); \
TLB_BROADCAST; \
} while(0)
#define cpu_tlb_flushID_SE(e) do { \
cpufuncs.cf_tlb_flushID_SE(e); \
TLB_BROADCAST; \
} while(0)
#define cpu_tlb_flushI() do { \
cpufuncs.cf_tlb_flushI(); \
TLB_BROADCAST; \
} while(0)
#define cpu_tlb_flushI_SE(e) do { \
cpufuncs.cf_tlb_flushI_SE(e); \
TLB_BROADCAST; \
} while(0)
#define cpu_tlb_flushD() do { \
cpufuncs.cf_tlb_flushD(); \
TLB_BROADCAST; \
} while(0)
#define cpu_tlb_flushD_SE(e) do { \
cpufuncs.cf_tlb_flushD_SE(e); \
TLB_BROADCAST; \
} while(0)
#endif
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
#define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all()
#define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s))
#define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all()
#define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s))
#define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s))
#define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s))
Add a new cache maintenance function, idcache_inv_all, to the table, and implementations for each of the chips we support. Most chips up through armv6 can use the armv4 implementation which has a single coprocessor opcode for this operation. The rather more complex armv7 implementation comes from netbsd.
2014-02-24 01:41:58 +00:00
#define cpu_idcache_inv_all() cpufuncs.cf_idcache_inv_all()
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
#define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all()
#define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s))
Add a new set of functions to handle L2 cache. Make them no-op for every CPU except Xscale core 3. Approved by: re (blanket)
2007-07-27 14:39:41 +00:00
#define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all()
#define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s))
#define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s))
#define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s))
Add cpu_l2cache_drain_writebuf(), use it to implement generic_bs_barrier(). On modern ARM SoCs the L2 cache controller sits between the CPU and the AXI bus, and most on-chip memory-mapped devices are on the AXI bus. We map the device registers using the 'Device' memory attribute, which means the memory is not cached, but writes to it are buffered. Ensuring that a write has made it all the way to a device may require that the L2 controller take some action. There is currently only one implementation of the new function, for the PL310 cache controller. It invokes a function that the controller manual calls "cache sync" but it actually has nothing to do with cache at all, it triggers a drain of all pending store buffer writes and it blocks until they complete. The sheeva and xscale L2 controllers (which predate the concept of Device memory) don't seem to have a corresponding function. It appears that the standard armv5 drain_writebuf function includes draining all the way through the L2 controller.
2014-05-11 04:24:57 +00:00
#define cpu_l2cache_drain_writebuf() cpufuncs.cf_l2cache_drain_writebuf()
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
#define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf()
#define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf()
#define cpu_flush_brnchtgt_C() cpufuncs.cf_flush_brnchtgt_C()
#define cpu_flush_brnchtgt_E(e) cpufuncs.cf_flush_brnchtgt_E(e)
#define cpu_sleep(m) cpufuncs.cf_sleep(m)
#define cpu_dataabt_fixup(a) cpufuncs.cf_dataabt_fixup(a)
#define cpu_prefetchabt_fixup(a) cpufuncs.cf_prefetchabt_fixup(a)
#define ABORT_FIXUP_OK 0 /* fixup succeeded */
#define ABORT_FIXUP_FAILED 1 /* fixup failed */
#define ABORT_FIXUP_RETURN 2 /* abort handler should return */
Remove the bootconfig parsing. We never used it and always passed either an empty string or NULL to the setup functions that called into it.
2015-03-29 20:37:28 +00:00
#define cpu_setup() cpufuncs.cf_setup()
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
int set_cpufuncs (void);
#define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */
#define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */
void cpufunc_nullop (void);
int cpufunc_null_fixup (void *);
int early_abort_fixup (void *);
int late_abort_fixup (void *);
u_int cpufunc_id (void);
Merging projects/armv6, part 1 Cummulative patch of changes that are not vendor-specific: - ARMv6 and ARMv7 architecture support - ARM SMP support - VFP/Neon support - ARM Generic Interrupt Controller driver - Simplification of startup code for all platforms
2012-08-15 03:03:03 +00:00
u_int cpufunc_cpuid (void);
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
u_int cpufunc_control (u_int clear, u_int bic);
void cpufunc_domains (u_int domains);
u_int cpufunc_faultstatus (void);
u_int cpufunc_faultaddress (void);
Merging projects/armv6, part 1 Cummulative patch of changes that are not vendor-specific: - ARMv6 and ARMv7 architecture support - ARM SMP support - VFP/Neon support - ARM Generic Interrupt Controller driver - Simplification of startup code for all platforms
2012-08-15 03:03:03 +00:00
u_int cpu_pfr (int);
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
Add support for FA626TE. Tested on GM8181 development board.
2010-05-04 10:14:05 +00:00
#if defined(CPU_FA526) || defined(CPU_FA626TE)
Remove the bootconfig parsing. We never used it and always passed either an empty string or NULL to the setup functions that called into it.
2015-03-29 20:37:28 +00:00
void fa526_setup (void);
Add support for Cavium Econa CNS11XX ARM boards. These boards were previously know by StarSemi STR9104. Tested by the submitter on an Emprex NSD-100 board. Submitted by: Yohanes Nugroho <yohanes at gmail.com> Reviewed by: freebsd-arm, stas Obtained from: //depot/projects/str91xx/...
2010-01-04 03:35:45 +00:00
void fa526_setttb (u_int ttb);
void fa526_context_switch (void);
void fa526_cpu_sleep (int);
void fa526_tlb_flushI_SE (u_int);
void fa526_tlb_flushID_SE (u_int);
void fa526_flush_prefetchbuf (void);
void fa526_flush_brnchtgt_E (u_int);
void fa526_icache_sync_all (void);
void fa526_icache_sync_range(vm_offset_t start, vm_size_t end);
void fa526_dcache_wbinv_all (void);
void fa526_dcache_wbinv_range(vm_offset_t start, vm_size_t end);
void fa526_dcache_inv_range (vm_offset_t start, vm_size_t end);
void fa526_dcache_wb_range (vm_offset_t start, vm_size_t end);
void fa526_idcache_wbinv_all(void);
void fa526_idcache_wbinv_range(vm_offset_t start, vm_size_t end);
#endif
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
#ifdef CPU_ARM9
void arm9_setttb (u_int);
void arm9_tlb_flushID_SE (u_int va);
Remove __P
2007-03-21 03:28:16 +00:00
void arm9_icache_sync_all (void);
void arm9_icache_sync_range (vm_offset_t, vm_size_t);
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
Remove __P
2007-03-21 03:28:16 +00:00
void arm9_dcache_wbinv_all (void);
void arm9_dcache_wbinv_range (vm_offset_t, vm_size_t);
void arm9_dcache_inv_range (vm_offset_t, vm_size_t);
void arm9_dcache_wb_range (vm_offset_t, vm_size_t);
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
Remove __P
2007-03-21 03:28:16 +00:00
void arm9_idcache_wbinv_all (void);
void arm9_idcache_wbinv_range (vm_offset_t, vm_size_t);
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
void arm9_context_switch (void);
Remove the bootconfig parsing. We never used it and always passed either an empty string or NULL to the setup functions that called into it.
2015-03-29 20:37:28 +00:00
void arm9_setup (void);
Bring in bits I forgot while importing write back support for arm9.
2005-06-03 19:49:53 +00:00
extern unsigned arm9_dcache_sets_max;
extern unsigned arm9_dcache_sets_inc;
extern unsigned arm9_dcache_index_max;
extern unsigned arm9_dcache_index_inc;
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
#endif
Remove support for CPU_ARM10. No kernel configs could possibly use this as it's not an available option. Along with this we will never support this cpu type as very few arm10 chips were made.
2015-03-29 17:13:44 +00:00
#if defined(CPU_ARM9E)
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
void arm10_tlb_flushID_SE (u_int);
void arm10_tlb_flushI_SE (u_int);
void arm10_context_switch (void);
Remove the bootconfig parsing. We never used it and always passed either an empty string or NULL to the setup functions that called into it.
2015-03-29 20:37:28 +00:00
void arm10_setup (void);
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
Fix confusing naming of Marvell ARM CPU specific routines. - The contents of 'feroceon_cpufuncs' dispatch table was really dedicated for the new Sheeva CPU (in 88F6xxx and MV-78xxx SOCs), and NOT Feroceon. - Feroceon CPU (in 88F5xxx SOCs) appears as a regular ARM926EJ-S core and does not require dedicated routines. This will be accompanied by a file rename commit.
2009-01-09 10:45:04 +00:00
u_int sheeva_control_ext (u_int, u_int);
Add basic cpu_sleep() support for Marvell SoCs. This drops my SheevaPlug's heatsink termperature in open air from 49C to 43C when idle.
2010-09-18 16:57:05 +00:00
void sheeva_cpu_sleep (int);
Fix confusing naming of Marvell ARM CPU specific routines. - The contents of 'feroceon_cpufuncs' dispatch table was really dedicated for the new Sheeva CPU (in 88F6xxx and MV-78xxx SOCs), and NOT Feroceon. - Feroceon CPU (in 88F5xxx SOCs) appears as a regular ARM926EJ-S core and does not require dedicated routines. This will be accompanied by a file rename commit.
2009-01-09 10:45:04 +00:00
void sheeva_setttb (u_int);
void sheeva_dcache_wbinv_range (vm_offset_t, vm_size_t);
void sheeva_dcache_inv_range (vm_offset_t, vm_size_t);
void sheeva_dcache_wb_range (vm_offset_t, vm_size_t);
void sheeva_idcache_wbinv_range (vm_offset_t, vm_size_t);
void sheeva_l2cache_wbinv_range (vm_offset_t, vm_size_t);
void sheeva_l2cache_inv_range (vm_offset_t, vm_size_t);
void sheeva_l2cache_wb_range (vm_offset_t, vm_size_t);
void sheeva_l2cache_wbinv_all (void);
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
#endif
Remove unused cpufunc arm11 and armv6 code. While here only define the remaining functions in the context we use them in.
2015-03-29 18:44:15 +00:00
#if defined(CPU_MV_PJ4B)
Merging projects/armv6, part 1 Cummulative patch of changes that are not vendor-specific: - ARMv6 and ARMv7 architecture support - ARM SMP support - VFP/Neon support - ARM Generic Interrupt Controller driver - Simplification of startup code for all platforms
2012-08-15 03:03:03 +00:00
void armv6_idcache_wbinv_all (void);
Remove unused cpufunc arm11 and armv6 code. While here only define the remaining functions in the context we use them in.
2015-03-29 18:44:15 +00:00
#endif
#if defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) || defined(CPU_KRAIT)
Merging projects/armv6, part 1 Cummulative patch of changes that are not vendor-specific: - ARMv6 and ARMv7 architecture support - ARM SMP support - VFP/Neon support - ARM Generic Interrupt Controller driver - Simplification of startup code for all platforms
2012-08-15 03:03:03 +00:00
void armv7_setttb (u_int);
void armv7_tlb_flushID (void);
void armv7_tlb_flushID_SE (u_int);
Make this declaration into a proper function prototype.
2014-04-29 23:29:28 +00:00
void armv7_icache_sync_all (void);
Merging projects/armv6, part 1 Cummulative patch of changes that are not vendor-specific: - ARMv6 and ARMv7 architecture support - ARM SMP support - VFP/Neon support - ARM Generic Interrupt Controller driver - Simplification of startup code for all platforms
2012-08-15 03:03:03 +00:00
void armv7_icache_sync_range (vm_offset_t, vm_size_t);
void armv7_idcache_wbinv_range (vm_offset_t, vm_size_t);
Add a new cache maintenance function, idcache_inv_all, to the table, and implementations for each of the chips we support. Most chips up through armv6 can use the armv4 implementation which has a single coprocessor opcode for this operation. The rather more complex armv7 implementation comes from netbsd.
2014-02-24 01:41:58 +00:00
void armv7_idcache_inv_all (void);
Merging projects/armv6, part 1 Cummulative patch of changes that are not vendor-specific: - ARMv6 and ARMv7 architecture support - ARM SMP support - VFP/Neon support - ARM Generic Interrupt Controller driver - Simplification of startup code for all platforms
2012-08-15 03:03:03 +00:00
void armv7_dcache_wbinv_all (void);
void armv7_idcache_wbinv_all (void);
void armv7_dcache_wbinv_range (vm_offset_t, vm_size_t);
void armv7_dcache_inv_range (vm_offset_t, vm_size_t);
void armv7_dcache_wb_range (vm_offset_t, vm_size_t);
void armv7_cpu_sleep (int);
Remove the bootconfig parsing. We never used it and always passed either an empty string or NULL to the setup functions that called into it.
2015-03-29 20:37:28 +00:00
void armv7_setup (void);
Merging projects/armv6, part 1 Cummulative patch of changes that are not vendor-specific: - ARMv6 and ARMv7 architecture support - ARM SMP support - VFP/Neon support - ARM Generic Interrupt Controller driver - Simplification of startup code for all platforms
2012-08-15 03:03:03 +00:00
void armv7_context_switch (void);
void armv7_drain_writebuf (void);
void armv7_sev (void);
Add an armv7 implementation of cpu_sleep(). The arm11/armv6 implementation we've been using was actually just spinning due to ARM having redefined the old 'wait for interrupt' operation via the system coprocessor as a nop and replacing it with a WFI instruction.
2014-02-28 00:41:55 +00:00
void armv7_sleep (int unused);
Merging projects/armv6, part 1 Cummulative patch of changes that are not vendor-specific: - ARMv6 and ARMv7 architecture support - ARM SMP support - VFP/Neon support - ARM Generic Interrupt Controller driver - Simplification of startup code for all platforms
2012-08-15 03:03:03 +00:00
u_int armv7_auxctrl (u_int, u_int);
Remove the bootconfig parsing. We never used it and always passed either an empty string or NULL to the setup functions that called into it.
2015-03-29 20:37:28 +00:00
void pj4bv7_setup (void);
Merging projects/armv6, part 1 Cummulative patch of changes that are not vendor-specific: - ARMv6 and ARMv7 architecture support - ARM SMP support - VFP/Neon support - ARM Generic Interrupt Controller driver - Simplification of startup code for all platforms
2012-08-15 03:03:03 +00:00
void pj4b_config (void);
void armadaxp_idcache_wbinv_all (void);
Remove the bootconfig parsing. We never used it and always passed either an empty string or NULL to the setup functions that called into it.
2015-03-29 20:37:28 +00:00
void cortexa_setup (void);
Merge support from p4 (from NetBSD) for arm9e and arm10, arm11 cores. Not yet connected to the build, but reduces diffs to p4 repo. Obtained from: NetBSD
2007-10-18 05:33:06 +00:00
#endif
Replace generic ARM11 option with more specific support for ARM1136 and ARM1176 Submitted by: Daisuke Aoyama <aoyama at peach.ne.jp> Obtained from: NetBSD
2012-12-20 04:32:02 +00:00
#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
Remove unused cpufunc arm11 and armv6 code. While here only define the remaining functions in the context we use them in.
2015-03-29 18:44:15 +00:00
void arm11_tlb_flushID (void);
void arm11_tlb_flushID_SE (u_int);
void arm11_tlb_flushI (void);
void arm11_tlb_flushI_SE (u_int);
void arm11_tlb_flushD (void);
void arm11_tlb_flushD_SE (u_int va);
void arm11_context_switch (void);
void arm11_drain_writebuf (void);
void armv6_dcache_wbinv_range (vm_offset_t, vm_size_t);
void armv6_dcache_inv_range (vm_offset_t, vm_size_t);
void armv6_dcache_wb_range (vm_offset_t, vm_size_t);
void armv6_idcache_inv_all (void);
Replace generic ARM11 option with more specific support for ARM1136 and ARM1176 Submitted by: Daisuke Aoyama <aoyama at peach.ne.jp> Obtained from: NetBSD
2012-12-20 04:32:02 +00:00
void arm11x6_setttb (u_int);
void arm11x6_idcache_wbinv_all (void);
void arm11x6_dcache_wbinv_all (void);
void arm11x6_icache_sync_all (void);
void arm11x6_flush_prefetchbuf (void);
void arm11x6_icache_sync_range (vm_offset_t, vm_size_t);
void arm11x6_idcache_wbinv_range (vm_offset_t, vm_size_t);
Remove the bootconfig parsing. We never used it and always passed either an empty string or NULL to the setup functions that called into it.
2015-03-29 20:37:28 +00:00
void arm11x6_setup (void);
Replace generic ARM11 option with more specific support for ARM1136 and ARM1176 Submitted by: Daisuke Aoyama <aoyama at peach.ne.jp> Obtained from: NetBSD
2012-12-20 04:32:02 +00:00
void arm11x6_sleep (int); /* no ref. for errata */
#endif
#if defined(CPU_ARM1136)
Remove unused cpufunc arm11 and armv6 code. While here only define the remaining functions in the context we use them in.
2015-03-29 18:44:15 +00:00
void arm11_sleep (int);
Replace generic ARM11 option with more specific support for ARM1136 and ARM1176 Submitted by: Daisuke Aoyama <aoyama at peach.ne.jp> Obtained from: NetBSD
2012-12-20 04:32:02 +00:00
void arm1136_sleep_rev0 (int); /* for errata 336501 */
#endif
Remove support for CPU_ARM10. No kernel configs could possibly use this as it's not an available option. Along with this we will never support this cpu type as very few arm10 chips were made.
2015-03-29 17:13:44 +00:00
#if defined(CPU_ARM9E)
Merge support from p4 (from NetBSD) for arm9e and arm10, arm11 cores. Not yet connected to the build, but reduces diffs to p4 repo. Obtained from: NetBSD
2007-10-18 05:33:06 +00:00
void armv5_ec_setttb(u_int);
void armv5_ec_icache_sync_all(void);
void armv5_ec_icache_sync_range(vm_offset_t, vm_size_t);
void armv5_ec_dcache_wbinv_all(void);
void armv5_ec_dcache_wbinv_range(vm_offset_t, vm_size_t);
void armv5_ec_dcache_inv_range(vm_offset_t, vm_size_t);
void armv5_ec_dcache_wb_range(vm_offset_t, vm_size_t);
void armv5_ec_idcache_wbinv_all(void);
void armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t);
#endif
Remove support for CPU_ARM10. No kernel configs could possibly use this as it's not an available option. Along with this we will never support this cpu type as very few arm10 chips were made.
2015-03-29 17:13:44 +00:00
#if defined(CPU_ARM9) || defined(CPU_ARM9E) || \
Add support for FA626TE. Tested on GM8181 development board.
2010-05-04 10:14:05 +00:00
defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(CPU_FA526) || defined(CPU_FA626TE) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
Identify the xscale 81342.
2006-11-07 22:36:57 +00:00
defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
trim trailing whitespace
2012-06-13 05:02:51 +00:00
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
void armv4_tlb_flushID (void);
void armv4_tlb_flushI (void);
void armv4_tlb_flushD (void);
void armv4_tlb_flushD_SE (u_int va);
void armv4_drain_writebuf (void);
Add a new cache maintenance function, idcache_inv_all, to the table, and implementations for each of the chips we support. Most chips up through armv6 can use the armv4 implementation which has a single coprocessor opcode for this operation. The rather more complex armv7 implementation comes from netbsd.
2014-02-24 01:41:58 +00:00
void armv4_idcache_inv_all (void);
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
#endif
Finally bring it support for the i80219 XScale processor. Submitted by: Max M. Boyarov <m.boyarov bsd by>
2006-08-24 23:51:28 +00:00
#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
Identify the xscale 81342.
2006-11-07 22:36:57 +00:00
defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
void xscale_cpwait (void);
void xscale_cpu_sleep (int mode);
u_int xscale_control (u_int clear, u_int bic);
void xscale_setttb (u_int ttb);
void xscale_tlb_flushID_SE (u_int va);
void xscale_cache_flushID (void);
void xscale_cache_flushI (void);
void xscale_cache_flushD (void);
void xscale_cache_flushD_SE (u_int entry);
void xscale_cache_cleanID (void);
void xscale_cache_cleanD (void);
void xscale_cache_cleanD_E (u_int entry);
void xscale_cache_clean_minidata (void);
void xscale_cache_purgeID (void);
void xscale_cache_purgeID_E (u_int entry);
void xscale_cache_purgeD (void);
void xscale_cache_purgeD_E (u_int entry);
void xscale_cache_syncI (void);
void xscale_cache_cleanID_rng (vm_offset_t start, vm_size_t end);
void xscale_cache_cleanD_rng (vm_offset_t start, vm_size_t end);
void xscale_cache_purgeID_rng (vm_offset_t start, vm_size_t end);
void xscale_cache_purgeD_rng (vm_offset_t start, vm_size_t end);
void xscale_cache_syncI_rng (vm_offset_t start, vm_size_t end);
void xscale_cache_flushD_rng (vm_offset_t start, vm_size_t end);
void xscale_context_switch (void);
Remove the bootconfig parsing. We never used it and always passed either an empty string or NULL to the setup functions that called into it.
2015-03-29 20:37:28 +00:00
void xscale_setup (void);
trim trailing whitespace
2012-06-13 05:02:51 +00:00
#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425
Finally bring it support for the i80219 XScale processor. Submitted by: Max M. Boyarov <m.boyarov bsd by>
2006-08-24 23:51:28 +00:00
CPU_XSCALE_80219 */
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
Identify the xscale 81342.
2006-11-07 22:36:57 +00:00
#ifdef CPU_XSCALE_81342
Add a new set of functions to handle L2 cache. Make them no-op for every CPU except Xscale core 3. Approved by: re (blanket)
2007-07-27 14:39:41 +00:00
void xscalec3_l2cache_purge (void);
Identify the xscale 81342.
2006-11-07 22:36:57 +00:00
void xscalec3_cache_purgeID (void);
void xscalec3_cache_purgeD (void);
Add a new set of functions to handle L2 cache. Make them no-op for every CPU except Xscale core 3. Approved by: re (blanket)
2007-07-27 14:39:41 +00:00
void xscalec3_cache_cleanID (void);
void xscalec3_cache_cleanD (void);
Identify the xscale 81342.
2006-11-07 22:36:57 +00:00
void xscalec3_cache_syncI (void);
Add a new set of functions to handle L2 cache. Make them no-op for every CPU except Xscale core 3. Approved by: re (blanket)
2007-07-27 14:39:41 +00:00
void xscalec3_cache_purgeID_rng (vm_offset_t start, vm_size_t end);
Identify the xscale 81342.
2006-11-07 22:36:57 +00:00
void xscalec3_cache_purgeD_rng (vm_offset_t start, vm_size_t end);
Add a new set of functions to handle L2 cache. Make them no-op for every CPU except Xscale core 3. Approved by: re (blanket)
2007-07-27 14:39:41 +00:00
void xscalec3_cache_cleanID_rng (vm_offset_t start, vm_size_t end);
void xscalec3_cache_cleanD_rng (vm_offset_t start, vm_size_t end);
void xscalec3_cache_syncI_rng (vm_offset_t start, vm_size_t end);
void xscalec3_l2cache_flush_rng (vm_offset_t, vm_size_t);
void xscalec3_l2cache_clean_rng (vm_offset_t start, vm_size_t end);
void xscalec3_l2cache_purge_rng (vm_offset_t start, vm_size_t end);
Identify the xscale 81342.
2006-11-07 22:36:57 +00:00
void xscalec3_setttb (u_int ttb);
void xscalec3_context_switch (void);
#endif /* CPU_XSCALE_81342 */
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
#define setttb cpu_setttb
#define drain_writebuf cpu_drain_writebuf
/*
* Macros for manipulating CPU interrupts
*/
static __inline u_int32_t __set_cpsr_c(u_int bic, u_int eor) __attribute__((__unused__));
static __inline u_int32_t
__set_cpsr_c(u_int bic, u_int eor)
{
u_int32_t tmp, ret;
__asm __volatile(
"mrs %0, cpsr\n" /* Get the CPSR */
"bic %1, %0, %2\n" /* Clear bits */
"eor %1, %1, %3\n" /* XOR bits */
"msr cpsr_c, %1\n" /* Set the control field of CPSR */
: "=&r" (ret), "=&r" (tmp)
Use interrupts_disable() and interrupts_restore() as intr_disable() and intr_restore() instead of re-implement it.
2004-11-04 19:18:50 +00:00
: "r" (bic), "r" (eor) : "memory");
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
return ret;
}
Don't define intr_disable and intr_restore as macros. The macros interfere with structure fields of the same name in drivers, like the intr_disable function pointer in struct cphy_ops in cxgb(4). Instead define intr_disable and intr_restore as inline functions. With intr_disable() an inline function, the I32_bit and F32_bit macros now need to be visible in MI code and given the rather poor names, this is not at all good. Define ARM_CPSR_F32 and ARM_CPSR_I32 and use that instead of F32_bit and I32_bit (resp) for now.
2012-11-27 00:41:39 +00:00
#define ARM_CPSR_F32 (1 << 6) /* FIQ disable */
#define ARM_CPSR_I32 (1 << 7) /* IRQ disable */
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
#define disable_interrupts(mask) \
Don't define intr_disable and intr_restore as macros. The macros interfere with structure fields of the same name in drivers, like the intr_disable function pointer in struct cphy_ops in cxgb(4). Instead define intr_disable and intr_restore as inline functions. With intr_disable() an inline function, the I32_bit and F32_bit macros now need to be visible in MI code and given the rather poor names, this is not at all good. Define ARM_CPSR_F32 and ARM_CPSR_I32 and use that instead of F32_bit and I32_bit (resp) for now.
2012-11-27 00:41:39 +00:00
(__set_cpsr_c((mask) & (ARM_CPSR_I32 | ARM_CPSR_F32), \
(mask) & (ARM_CPSR_I32 | ARM_CPSR_F32)))
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
#define enable_interrupts(mask) \
Don't define intr_disable and intr_restore as macros. The macros interfere with structure fields of the same name in drivers, like the intr_disable function pointer in struct cphy_ops in cxgb(4). Instead define intr_disable and intr_restore as inline functions. With intr_disable() an inline function, the I32_bit and F32_bit macros now need to be visible in MI code and given the rather poor names, this is not at all good. Define ARM_CPSR_F32 and ARM_CPSR_I32 and use that instead of F32_bit and I32_bit (resp) for now.
2012-11-27 00:41:39 +00:00
(__set_cpsr_c((mask) & (ARM_CPSR_I32 | ARM_CPSR_F32), 0))
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
#define restore_interrupts(old_cpsr) \
Don't define intr_disable and intr_restore as macros. The macros interfere with structure fields of the same name in drivers, like the intr_disable function pointer in struct cphy_ops in cxgb(4). Instead define intr_disable and intr_restore as inline functions. With intr_disable() an inline function, the I32_bit and F32_bit macros now need to be visible in MI code and given the rather poor names, this is not at all good. Define ARM_CPSR_F32 and ARM_CPSR_I32 and use that instead of F32_bit and I32_bit (resp) for now.
2012-11-27 00:41:39 +00:00
(__set_cpsr_c((ARM_CPSR_I32 | ARM_CPSR_F32), \
(old_cpsr) & (ARM_CPSR_I32 | ARM_CPSR_F32)))
static __inline register_t
intr_disable(void)
{
register_t s;
s = disable_interrupts(ARM_CPSR_I32 | ARM_CPSR_F32);
return (s);
}
static __inline void
intr_restore(register_t s)
{
restore_interrupts(s);
}
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
/* Functions to manipulate the CPSR. */
u_int SetCPSR(u_int bic, u_int eor);
u_int GetCPSR(void);
/*
* Functions to manipulate cpu r13
* (in arm/arm32/setstack.S)
*/
Remove __P
2007-03-21 03:28:16 +00:00
void set_stackptr (u_int mode, u_int address);
u_int get_stackptr (u_int mode);
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
/*
* Miscellany
*/
Remove __P
2007-03-21 03:28:16 +00:00
int get_pc_str_offset (void);
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
/*
* CPU functions from locore.S
*/
Remove __P
2007-03-21 03:28:16 +00:00
void cpu_reset (void) __attribute__((__noreturn__));
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
/*
* Cache info variables.
*/
/* PRIMARY CACHE VARIABLES */
extern int arm_picache_size;
extern int arm_picache_line_size;
extern int arm_picache_ways;
extern int arm_pdcache_size; /* and unified */
extern int arm_pdcache_line_size;
trim trailing whitespace
2012-06-13 05:02:51 +00:00
extern int arm_pdcache_ways;
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
extern int arm_pcache_type;
extern int arm_pcache_unified;
extern int arm_dcache_align;
extern int arm_dcache_align_mask;
Merging projects/armv6, part 1 Cummulative patch of changes that are not vendor-specific: - ARMv6 and ARMv7 architecture support - ARM SMP support - VFP/Neon support - ARM Generic Interrupt Controller driver - Simplification of startup code for all platforms
2012-08-15 03:03:03 +00:00
extern u_int arm_cache_level;
extern u_int arm_cache_loc;
extern u_int arm_cache_type[14];
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
#endif /* _KERNEL */
#endif /* _MACHINE_CPUFUNC_H_ */
/* End of cpufunc.h */
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