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freebsd-dev/sys/arm/ti/cpsw/if_cpswreg.h

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Merging of projects/armv6, part 10 - Support for Texas Instruments SoCs: - AM335x - OMAP4 - Kernel configs, DTS for Beaglebone and Pandaboard Submitted by: Ben Gray, Damjan Marion
2012-08-15 06:31:32 +00:00
/*-
sys/arm: further adoption of SPDX licensing ID tags. Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
2017-11-27 15:04:10 +00:00
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
Merging of projects/armv6, part 10 - Support for Texas Instruments SoCs: - AM335x - OMAP4 - Kernel configs, DTS for Beaglebone and Pandaboard Submitted by: Ben Gray, Damjan Marion
2012-08-15 06:31:32 +00:00
* Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _IF_CPSWREG_H
#define _IF_CPSWREG_H
Fixes a few style(9) issues, remove extra blank lines. No functional changes. Sponsored by: Rubicon Comunications (Netgate)
2016-03-17 06:23:48 +00:00
#define CPSW_SS_OFFSET 0x0000
#define CPSW_SS_IDVER (CPSW_SS_OFFSET + 0x00)
#define CPSW_SS_SOFT_RESET (CPSW_SS_OFFSET + 0x08)
#define CPSW_SS_STAT_PORT_EN (CPSW_SS_OFFSET + 0x0C)
#define CPSW_SS_PTYPE (CPSW_SS_OFFSET + 0x10)
Another overhaul of the CPSW driver for BeagleBone Major changes: * Finally tracked down the flow control setting that seems to have been causing TX stalls and watchdog timeouts * RX and TX paths now share a lot more code * TX interrupt is no longer used; we instead GC finished tx queue entries at the bottom of the start routine. * TX start now queues fragmented packets directly; it only invokes defrag() for occasional very fragmented packets. * "sysctl dev.cpsw" dumps controller statistics and queue counts * Host Error Interrupt will give extensive debugging information if the controller chokes on the queued data.
2013-02-03 01:08:01 +00:00
#define CPSW_SS_FLOW_CONTROL (CPSW_SS_OFFSET + 0x24)
Merging of projects/armv6, part 10 - Support for Texas Instruments SoCs: - AM335x - OMAP4 - Kernel configs, DTS for Beaglebone and Pandaboard Submitted by: Ben Gray, Damjan Marion
2012-08-15 06:31:32 +00:00
Fixes a few style(9) issues, remove extra blank lines. No functional changes. Sponsored by: Rubicon Comunications (Netgate)
2016-03-17 06:23:48 +00:00
#define CPSW_PORT_OFFSET 0x0100
Another overhaul of the CPSW driver for BeagleBone Major changes: * Finally tracked down the flow control setting that seems to have been causing TX stalls and watchdog timeouts * RX and TX paths now share a lot more code * TX interrupt is no longer used; we instead GC finished tx queue entries at the bottom of the start routine. * TX start now queues fragmented packets directly; it only invokes defrag() for occasional very fragmented packets. * "sysctl dev.cpsw" dumps controller statistics and queue counts * Host Error Interrupt will give extensive debugging information if the controller chokes on the queued data.
2013-02-03 01:08:01 +00:00
#define CPSW_PORT_P_MAX_BLKS(p) (CPSW_PORT_OFFSET + 0x08 + ((p) * 0x100))
#define CPSW_PORT_P_BLK_CNT(p) (CPSW_PORT_OFFSET + 0x0C + ((p) * 0x100))
Add support for dual emac mode. In dual emac mode, the CPSW subsystem provides two independent ethernets. This is implemented (as recommended by TI's TRM) with a mixture of switch settings (vlans) and specific features of CPSW subsystem. The driver was splitted to accommodate the shared parts (RX and TX rings for example) while it still provides two independent ethernets. Each of the ethernet ports driver has it's own set of MDIO registers among the other private settings. Previously this driver always operate in promisc mode, now the Switch ALE (address table entry) is properly initialized and enabled. The driver is also tested (and known to work) with both ports operating in single port mode (active_slave 0 or 1). Tested on uBMC (dual emac mode, both ports in single mode, giga and fast ethernet) and BBB (single port, fast ethernet). Sponsored by: Rubicon Communications (Netgate)
2016-03-17 19:35:08 +00:00
#define CPSW_PORT_P_VLAN(p) (CPSW_PORT_OFFSET + 0x14 + ((p) * 0x100))
Fixes a few style(9) issues, remove extra blank lines. No functional changes. Sponsored by: Rubicon Comunications (Netgate)
2016-03-17 06:23:48 +00:00
#define CPSW_PORT_P_TX_PRI_MAP(p) (CPSW_PORT_OFFSET + 0x118 + ((p-1) * 0x100))
#define CPSW_PORT_P0_CPDMA_TX_PRI_MAP (CPSW_PORT_OFFSET + 0x01C)
#define CPSW_PORT_P0_CPDMA_RX_CH_MAP (CPSW_PORT_OFFSET + 0x020)
#define CPSW_PORT_P_SA_LO(p) (CPSW_PORT_OFFSET + 0x120 + ((p-1) * 0x100))
#define CPSW_PORT_P_SA_HI(p) (CPSW_PORT_OFFSET + 0x124 + ((p-1) * 0x100))
#define CPSW_CPDMA_OFFSET 0x0800
#define CPSW_CPDMA_TX_CONTROL (CPSW_CPDMA_OFFSET + 0x04)
#define CPSW_CPDMA_TX_TEARDOWN (CPSW_CPDMA_OFFSET + 0x08)
#define CPSW_CPDMA_RX_CONTROL (CPSW_CPDMA_OFFSET + 0x14)
#define CPSW_CPDMA_RX_TEARDOWN (CPSW_CPDMA_OFFSET + 0x18)
#define CPSW_CPDMA_SOFT_RESET (CPSW_CPDMA_OFFSET + 0x1c)
#define CPSW_CPDMA_DMACONTROL (CPSW_CPDMA_OFFSET + 0x20)
#define CPSW_CPDMA_DMASTATUS (CPSW_CPDMA_OFFSET + 0x24)
#define CPSW_CPDMA_RX_BUFFER_OFFSET (CPSW_CPDMA_OFFSET + 0x28)
#define CPSW_CPDMA_TX_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0x80)
#define CPSW_CPDMA_TX_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0x84)
#define CPSW_CPDMA_TX_INTMASK_SET (CPSW_CPDMA_OFFSET + 0x88)
#define CPSW_CPDMA_TX_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0x8C)
#define CPSW_CPDMA_CPDMA_EOI_VECTOR (CPSW_CPDMA_OFFSET + 0x94)
#define CPSW_CPDMA_RX_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0xA0)
#define CPSW_CPDMA_RX_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0xA4)
#define CPSW_CPDMA_RX_INTMASK_SET (CPSW_CPDMA_OFFSET + 0xA8)
#define CPSW_CPDMA_RX_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0xAc)
if_cpsw overhaul: - Fix RX and TX teardown: . TX teardown would not reclaim the abandoned descriptors; . Interrupt storms in RX teardown; . Fixed the acknowledge of the teardown completion interrupt. - Remove temporary lists for the descriptors; - Simplified the descriptor handling (less writes and reads from descriptors where possible); - Better debug; - Add support for the RX threshold interrupts: With interrupt moderation only, an RX overrun is likely to happen. The RX threshold is set to trigger a non paced interrupt everytime your RX free buffers are under the minimum threshold, helping to prevent the rx overrun. The NIC now survive when pushed over its limits (where previously it would lock up in a few seconds). uFW (600MHz SoC) can now forward up to 560Mb/s of UDP traffic (netmap pkt-gen as source and sink). TCP forwarding rate is over 350Mb/s. No difference (other than CPU use) was seen on Beaglebone black (1GHz SoC) for his fast ethernet. Tested on: uFW, BBB Sponsored by: Rubicon Communications, LLC (Netgate)
2016-10-05 19:09:27 +00:00
#define CPSW_CPDMA_RX_INT_THRESH(_ch) (1 << (8 + ((_ch) & 7)))
#define CPSW_CPDMA_RX_INT(_ch) (1 << (0 + ((_ch) & 7)))
Fixes a few style(9) issues, remove extra blank lines. No functional changes. Sponsored by: Rubicon Comunications (Netgate)
2016-03-17 06:23:48 +00:00
#define CPSW_CPDMA_DMA_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0xB0)
#define CPSW_CPDMA_DMA_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0xB4)
#define CPSW_CPDMA_DMA_INTMASK_SET (CPSW_CPDMA_OFFSET + 0xB8)
#define CPSW_CPDMA_DMA_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0xBC)
if_cpsw overhaul: - Fix RX and TX teardown: . TX teardown would not reclaim the abandoned descriptors; . Interrupt storms in RX teardown; . Fixed the acknowledge of the teardown completion interrupt. - Remove temporary lists for the descriptors; - Simplified the descriptor handling (less writes and reads from descriptors where possible); - Better debug; - Add support for the RX threshold interrupts: With interrupt moderation only, an RX overrun is likely to happen. The RX threshold is set to trigger a non paced interrupt everytime your RX free buffers are under the minimum threshold, helping to prevent the rx overrun. The NIC now survive when pushed over its limits (where previously it would lock up in a few seconds). uFW (600MHz SoC) can now forward up to 560Mb/s of UDP traffic (netmap pkt-gen as source and sink). TCP forwarding rate is over 350Mb/s. No difference (other than CPU use) was seen on Beaglebone black (1GHz SoC) for his fast ethernet. Tested on: uFW, BBB Sponsored by: Rubicon Communications, LLC (Netgate)
2016-10-05 19:09:27 +00:00
#define CPSW_CPDMA_RX_PENDTHRESH(p) (CPSW_CPDMA_OFFSET + 0x0c0 + ((p) * 0x04))
Fixes a few style(9) issues, remove extra blank lines. No functional changes. Sponsored by: Rubicon Comunications (Netgate)
2016-03-17 06:23:48 +00:00
#define CPSW_CPDMA_RX_FREEBUFFER(p) (CPSW_CPDMA_OFFSET + 0x0e0 + ((p) * 0x04))
#define CPSW_STATS_OFFSET 0x0900
#define CPSW_STATERAM_OFFSET 0x0A00
#define CPSW_CPDMA_TX_HDP(p) (CPSW_STATERAM_OFFSET + 0x00 + ((p) * 0x04))
#define CPSW_CPDMA_RX_HDP(p) (CPSW_STATERAM_OFFSET + 0x20 + ((p) * 0x04))
#define CPSW_CPDMA_TX_CP(p) (CPSW_STATERAM_OFFSET + 0x40 + ((p) * 0x04))
#define CPSW_CPDMA_RX_CP(p) (CPSW_STATERAM_OFFSET + 0x60 + ((p) * 0x04))
#define CPSW_CPTS_OFFSET 0x0C00
#define CPSW_ALE_OFFSET 0x0D00
#define CPSW_ALE_CONTROL (CPSW_ALE_OFFSET + 0x08)
Add support for dual emac mode. In dual emac mode, the CPSW subsystem provides two independent ethernets. This is implemented (as recommended by TI's TRM) with a mixture of switch settings (vlans) and specific features of CPSW subsystem. The driver was splitted to accommodate the shared parts (RX and TX rings for example) while it still provides two independent ethernets. Each of the ethernet ports driver has it's own set of MDIO registers among the other private settings. Previously this driver always operate in promisc mode, now the Switch ALE (address table entry) is properly initialized and enabled. The driver is also tested (and known to work) with both ports operating in single port mode (active_slave 0 or 1). Tested on uBMC (dual emac mode, both ports in single mode, giga and fast ethernet) and BBB (single port, fast ethernet). Sponsored by: Rubicon Communications (Netgate)
2016-03-17 19:35:08 +00:00
#define CPSW_ALE_CTL_ENABLE (1U << 31)
#define CPSW_ALE_CTL_CLEAR_TBL (1 << 30)
#define CPSW_ALE_CTL_BYPASS (1 << 4)
#define CPSW_ALE_CTL_VLAN_AWARE (1 << 2)
Fixes a few style(9) issues, remove extra blank lines. No functional changes. Sponsored by: Rubicon Comunications (Netgate)
2016-03-17 06:23:48 +00:00
#define CPSW_ALE_TBLCTL (CPSW_ALE_OFFSET + 0x20)
#define CPSW_ALE_TBLW2 (CPSW_ALE_OFFSET + 0x34)
#define CPSW_ALE_TBLW1 (CPSW_ALE_OFFSET + 0x38)
#define CPSW_ALE_TBLW0 (CPSW_ALE_OFFSET + 0x3C)
Add support for dual emac mode. In dual emac mode, the CPSW subsystem provides two independent ethernets. This is implemented (as recommended by TI's TRM) with a mixture of switch settings (vlans) and specific features of CPSW subsystem. The driver was splitted to accommodate the shared parts (RX and TX rings for example) while it still provides two independent ethernets. Each of the ethernet ports driver has it's own set of MDIO registers among the other private settings. Previously this driver always operate in promisc mode, now the Switch ALE (address table entry) is properly initialized and enabled. The driver is also tested (and known to work) with both ports operating in single port mode (active_slave 0 or 1). Tested on uBMC (dual emac mode, both ports in single mode, giga and fast ethernet) and BBB (single port, fast ethernet). Sponsored by: Rubicon Communications (Netgate)
2016-03-17 19:35:08 +00:00
#define ALE_MCAST(_a) ((_a[1] >> 8) & 1)
#define ALE_MCAST_FWD (3 << 30)
#define ALE_PORTS(_a) ((_a[2] >> 2) & 7)
#define ALE_TYPE(_a) ((_a[1] >> 28) & 3)
#define ALE_TYPE_ADDR 1
#define ALE_TYPE_VLAN 2
#define ALE_TYPE_VLAN_ADDR 3
#define ALE_VLAN(_a) ((_a[1] >> 16) & 0xfff)
Enable multicast addresses on vlan ports. Fixes the reception of broadcast packets on vlan aware mode. Sponsored by: Rubicon Communications (Netgate)
2016-03-21 03:16:56 +00:00
#define ALE_VLAN_UNREGFLOOD(_a) ((_a[0] >> 8) & 7)
#define ALE_VLAN_REGFLOOD(_a) ((_a[0] >> 16) & 7)
Add support for dual emac mode. In dual emac mode, the CPSW subsystem provides two independent ethernets. This is implemented (as recommended by TI's TRM) with a mixture of switch settings (vlans) and specific features of CPSW subsystem. The driver was splitted to accommodate the shared parts (RX and TX rings for example) while it still provides two independent ethernets. Each of the ethernet ports driver has it's own set of MDIO registers among the other private settings. Previously this driver always operate in promisc mode, now the Switch ALE (address table entry) is properly initialized and enabled. The driver is also tested (and known to work) with both ports operating in single port mode (active_slave 0 or 1). Tested on uBMC (dual emac mode, both ports in single mode, giga and fast ethernet) and BBB (single port, fast ethernet). Sponsored by: Rubicon Communications (Netgate)
2016-03-17 19:35:08 +00:00
#define ALE_VLAN_UNTAG(_a) ((_a[0] >> 24) & 7)
#define ALE_VLAN_MEMBERS(_a) (_a[0] & 7)
Fixes a few style(9) issues, remove extra blank lines. No functional changes. Sponsored by: Rubicon Comunications (Netgate)
2016-03-17 06:23:48 +00:00
#define CPSW_ALE_PORTCTL(p) (CPSW_ALE_OFFSET + 0x40 + ((p) * 0x04))
Add the etherswitch(4) support for TI CPSW. Adds VLAN and port management abilities for etherswitchcfg(8). The code is conditionally enabled for now, because it is not necessary on single ethernet use cases. Obtained from: pfSense MFC after: 2 weeks Sponsored by: Rubicon Communications, LLC (Netgate)
2016-11-24 20:14:43 +00:00
#define ALE_PORTCTL_NO_SA_UPDATE (1 << 5)
#define ALE_PORTCTL_NO_LEARN (1 << 4)
#define ALE_PORTCTL_INGRESS (1 << 3)
#define ALE_PORTCTL_DROP_UNTAGGED (1 << 2)
#define ALE_PORTCTL_FORWARD 3
#define ALE_PORTCTL_LEARN 2
#define ALE_PORTCTL_BLOCKED 1
#define ALE_PORTCTL_DISABLED 0
Merging of projects/armv6, part 10 - Support for Texas Instruments SoCs: - AM335x - OMAP4 - Kernel configs, DTS for Beaglebone and Pandaboard Submitted by: Ben Gray, Damjan Marion
2012-08-15 06:31:32 +00:00
Another overhaul of the CPSW driver for BeagleBone Major changes: * Finally tracked down the flow control setting that seems to have been causing TX stalls and watchdog timeouts * RX and TX paths now share a lot more code * TX interrupt is no longer used; we instead GC finished tx queue entries at the bottom of the start routine. * TX start now queues fragmented packets directly; it only invokes defrag() for occasional very fragmented packets. * "sysctl dev.cpsw" dumps controller statistics and queue counts * Host Error Interrupt will give extensive debugging information if the controller chokes on the queued data.
2013-02-03 01:08:01 +00:00
/* SL1 is at 0x0D80, SL2 is at 0x0DC0 */
Fixes a few style(9) issues, remove extra blank lines. No functional changes. Sponsored by: Rubicon Comunications (Netgate)
2016-03-17 06:23:48 +00:00
#define CPSW_SL_OFFSET 0x0D80
#define CPSW_SL_MACCONTROL(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x04)
Add support for dual emac mode. In dual emac mode, the CPSW subsystem provides two independent ethernets. This is implemented (as recommended by TI's TRM) with a mixture of switch settings (vlans) and specific features of CPSW subsystem. The driver was splitted to accommodate the shared parts (RX and TX rings for example) while it still provides two independent ethernets. Each of the ethernet ports driver has it's own set of MDIO registers among the other private settings. Previously this driver always operate in promisc mode, now the Switch ALE (address table entry) is properly initialized and enabled. The driver is also tested (and known to work) with both ports operating in single port mode (active_slave 0 or 1). Tested on uBMC (dual emac mode, both ports in single mode, giga and fast ethernet) and BBB (single port, fast ethernet). Sponsored by: Rubicon Communications (Netgate)
2016-03-17 19:35:08 +00:00
#define CPSW_SL_MACTL_IFCTL_B (1 << 16)
#define CPSW_SL_MACTL_IFCTL_A (1 << 15)
#define CPSW_SL_MACTL_GIG (1 << 7)
#define CPSW_SL_MACTL_GMII_ENABLE (1 << 5)
#define CPSW_SL_MACTL_FULLDUPLEX (1 << 0)
Fixes a few style(9) issues, remove extra blank lines. No functional changes. Sponsored by: Rubicon Comunications (Netgate)
2016-03-17 06:23:48 +00:00
#define CPSW_SL_MACSTATUS(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x08)
#define CPSW_SL_SOFT_RESET(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x0C)
#define CPSW_SL_RX_MAXLEN(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x10)
#define CPSW_SL_RX_PAUSE(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x18)
#define CPSW_SL_TX_PAUSE(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x1C)
#define CPSW_SL_RX_PRI_MAP(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x24)
#define MDIO_OFFSET 0x1000
#define MDIOCONTROL (MDIO_OFFSET + 0x04)
Add support for dual emac mode. In dual emac mode, the CPSW subsystem provides two independent ethernets. This is implemented (as recommended by TI's TRM) with a mixture of switch settings (vlans) and specific features of CPSW subsystem. The driver was splitted to accommodate the shared parts (RX and TX rings for example) while it still provides two independent ethernets. Each of the ethernet ports driver has it's own set of MDIO registers among the other private settings. Previously this driver always operate in promisc mode, now the Switch ALE (address table entry) is properly initialized and enabled. The driver is also tested (and known to work) with both ports operating in single port mode (active_slave 0 or 1). Tested on uBMC (dual emac mode, both ports in single mode, giga and fast ethernet) and BBB (single port, fast ethernet). Sponsored by: Rubicon Communications (Netgate)
2016-03-17 19:35:08 +00:00
#define MDIOCTL_ENABLE (1 << 30)
#define MDIOCTL_FAULTENB (1 << 18)
#define MDIOLINKINTRAW (MDIO_OFFSET + 0x10)
#define MDIOLINKINTMASKED (MDIO_OFFSET + 0x14)
Fixes a few style(9) issues, remove extra blank lines. No functional changes. Sponsored by: Rubicon Comunications (Netgate)
2016-03-17 06:23:48 +00:00
#define MDIOUSERACCESS0 (MDIO_OFFSET + 0x80)
#define MDIOUSERPHYSEL0 (MDIO_OFFSET + 0x84)
Add support for dual emac mode. In dual emac mode, the CPSW subsystem provides two independent ethernets. This is implemented (as recommended by TI's TRM) with a mixture of switch settings (vlans) and specific features of CPSW subsystem. The driver was splitted to accommodate the shared parts (RX and TX rings for example) while it still provides two independent ethernets. Each of the ethernet ports driver has it's own set of MDIO registers among the other private settings. Previously this driver always operate in promisc mode, now the Switch ALE (address table entry) is properly initialized and enabled. The driver is also tested (and known to work) with both ports operating in single port mode (active_slave 0 or 1). Tested on uBMC (dual emac mode, both ports in single mode, giga and fast ethernet) and BBB (single port, fast ethernet). Sponsored by: Rubicon Communications (Netgate)
2016-03-17 19:35:08 +00:00
#define MDIOUSERACCESS1 (MDIO_OFFSET + 0x88)
#define MDIOUSERPHYSEL1 (MDIO_OFFSET + 0x8C)
#define MDIO_PHYSEL_LINKINTENB (1 << 6)
#define MDIO_PHYACCESS_GO (1U << 31)
#define MDIO_PHYACCESS_WRITE (1 << 30)
#define MDIO_PHYACCESS_ACK (1 << 29)
Fixes a few style(9) issues, remove extra blank lines. No functional changes. Sponsored by: Rubicon Comunications (Netgate)
2016-03-17 06:23:48 +00:00
#define CPSW_WR_OFFSET 0x1200
#define CPSW_WR_SOFT_RESET (CPSW_WR_OFFSET + 0x04)
#define CPSW_WR_CONTROL (CPSW_WR_OFFSET + 0x08)
#define CPSW_WR_INT_CONTROL (CPSW_WR_OFFSET + 0x0c)
Add a sysctl to control the interrupt pacing on AM335x integrated switch. The hardware can be set to limit the number of interrupts from 2 to 63 interrupts per ms. To keep the compatibility with the TI documentation the sysctl take the interval between the interrupts pulses: 16~500 us. Sponsored by: Rubicon Communications, LLC (Netgate)
2016-09-27 18:19:29 +00:00
#define CPSW_WR_INT_C0_RX_PULSE (1 << 16)
#define CPSW_WR_INT_C0_TX_PULSE (1 << 17)
#define CPSW_WR_INT_C1_RX_PULSE (1 << 18)
#define CPSW_WR_INT_C1_TX_PULSE (1 << 19)
#define CPSW_WR_INT_C2_RX_PULSE (1 << 20)
#define CPSW_WR_INT_C2_TX_PULSE (1 << 21)
#define CPSW_WR_INT_PACE_EN \
(CPSW_WR_INT_C0_RX_PULSE | CPSW_WR_INT_C0_TX_PULSE | \
CPSW_WR_INT_C1_RX_PULSE | CPSW_WR_INT_C1_TX_PULSE | \
CPSW_WR_INT_C2_RX_PULSE | CPSW_WR_INT_C2_TX_PULSE)
#define CPSW_WR_INT_PRESCALE_MASK 0xfff
Fixes a few style(9) issues, remove extra blank lines. No functional changes. Sponsored by: Rubicon Comunications (Netgate)
2016-03-17 06:23:48 +00:00
#define CPSW_WR_C_RX_THRESH_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x10)
#define CPSW_WR_C_RX_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x14)
#define CPSW_WR_C_TX_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x18)
#define CPSW_WR_C_MISC_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x1C)
#define CPSW_WR_C_RX_THRESH_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x40)
#define CPSW_WR_C_RX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x44)
#define CPSW_WR_C_TX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x48)
#define CPSW_WR_C_MISC_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x4C)
Add support for dual emac mode. In dual emac mode, the CPSW subsystem provides two independent ethernets. This is implemented (as recommended by TI's TRM) with a mixture of switch settings (vlans) and specific features of CPSW subsystem. The driver was splitted to accommodate the shared parts (RX and TX rings for example) while it still provides two independent ethernets. Each of the ethernet ports driver has it's own set of MDIO registers among the other private settings. Previously this driver always operate in promisc mode, now the Switch ALE (address table entry) is properly initialized and enabled. The driver is also tested (and known to work) with both ports operating in single port mode (active_slave 0 or 1). Tested on uBMC (dual emac mode, both ports in single mode, giga and fast ethernet) and BBB (single port, fast ethernet). Sponsored by: Rubicon Communications (Netgate)
2016-03-17 19:35:08 +00:00
#define CPSW_WR_C_MISC_EVNT_PEND (1 << 4)
#define CPSW_WR_C_MISC_STAT_PEND (1 << 3)
#define CPSW_WR_C_MISC_HOST_PEND (1 << 2)
#define CPSW_WR_C_MISC_MDIOLINK (1 << 1)
#define CPSW_WR_C_MISC_MDIOUSER (1 << 0)
Add a sysctl to control the interrupt pacing on AM335x integrated switch. The hardware can be set to limit the number of interrupts from 2 to 63 interrupts per ms. To keep the compatibility with the TI documentation the sysctl take the interval between the interrupts pulses: 16~500 us. Sponsored by: Rubicon Communications, LLC (Netgate)
2016-09-27 18:19:29 +00:00
#define CPSW_WR_C_RX_IMAX(p) (CPSW_WR_OFFSET + (0x08 * (p)) + 0x70)
#define CPSW_WR_C_TX_IMAX(p) (CPSW_WR_OFFSET + (0x08 * (p)) + 0x74)
#define CPSW_WR_C_IMAX_MASK 0x3f
#define CPSW_WR_C_IMAX_MAX 63
#define CPSW_WR_C_IMAX_MIN 2
#define CPSW_WR_C_IMAX_US_MAX 500
#define CPSW_WR_C_IMAX_US_MIN 16
Fixes a few style(9) issues, remove extra blank lines. No functional changes. Sponsored by: Rubicon Comunications (Netgate)
2016-03-17 06:23:48 +00:00
#define CPSW_CPPI_RAM_OFFSET 0x2000
Another overhaul of the CPSW driver for BeagleBone Major changes: * Finally tracked down the flow control setting that seems to have been causing TX stalls and watchdog timeouts * RX and TX paths now share a lot more code * TX interrupt is no longer used; we instead GC finished tx queue entries at the bottom of the start routine. * TX start now queues fragmented packets directly; it only invokes defrag() for occasional very fragmented packets. * "sysctl dev.cpsw" dumps controller statistics and queue counts * Host Error Interrupt will give extensive debugging information if the controller chokes on the queued data.
2013-02-03 01:08:01 +00:00
#define CPSW_CPPI_RAM_SIZE 0x2000
Switch TI platform support code from using FreeBSD's custom-baked DTS files to vendor-provided ones. It should make easier to adopt platform code to new revisions of hardware and to use DTS overlays for various Beaglebone extensions (shields/capes). Original dts filenames were not changed, they're now wrappers over dts files provided by TI. So make sure you update .dtb files on your devices as part of kernel update GPIO addressing was changed: instead of one global /dev/gpioc0 there are per-bank instances of /dev/gpiocX. Each bank has 32 pins so for instance pin 121 on /dev/gpioc0 in old addressing scheme is now pin 25 on /dev/gpioc3 On Pandaboard serial console devices was changed from /dev/ttyu0 to /dev/ttyu2 so you'll have to update /etc/ttys to get login prompt on serial port in multiuser mode. Single user mode serial console should work as-is Differential Revision: https://reviews.freebsd.org/D2146 Reviewed by: rpaulo, ian, Michal Meloun, Svatopluk Kraus
2015-05-22 03:16:18 +00:00
#define CPSW_MEMWINDOW_SIZE 0x4000
Add support for dual emac mode. In dual emac mode, the CPSW subsystem provides two independent ethernets. This is implemented (as recommended by TI's TRM) with a mixture of switch settings (vlans) and specific features of CPSW subsystem. The driver was splitted to accommodate the shared parts (RX and TX rings for example) while it still provides two independent ethernets. Each of the ethernet ports driver has it's own set of MDIO registers among the other private settings. Previously this driver always operate in promisc mode, now the Switch ALE (address table entry) is properly initialized and enabled. The driver is also tested (and known to work) with both ports operating in single port mode (active_slave 0 or 1). Tested on uBMC (dual emac mode, both ports in single mode, giga and fast ethernet) and BBB (single port, fast ethernet). Sponsored by: Rubicon Communications (Netgate)
2016-03-17 19:35:08 +00:00
#define CPDMA_BD_SOP (1 << 15)
#define CPDMA_BD_EOP (1 << 14)
#define CPDMA_BD_OWNER (1 << 13)
#define CPDMA_BD_EOQ (1 << 12)
#define CPDMA_BD_TDOWNCMPLT (1 << 11)
Handle the set capabilities ioctl, letting the hardware checksum be disabled (Hi netmap!). Only remove the CRC bytes from packets when the hardware tell us to do so. Fixes the 'discard frame w/o leading ethernet header' issues. Sponsored by: Rubicon Communications, LLC (Netgate)
2017-01-19 14:58:55 +00:00
#define CPDMA_BD_PASS_CRC (1 << 10)
Add support for dual emac mode. In dual emac mode, the CPSW subsystem provides two independent ethernets. This is implemented (as recommended by TI's TRM) with a mixture of switch settings (vlans) and specific features of CPSW subsystem. The driver was splitted to accommodate the shared parts (RX and TX rings for example) while it still provides two independent ethernets. Each of the ethernet ports driver has it's own set of MDIO registers among the other private settings. Previously this driver always operate in promisc mode, now the Switch ALE (address table entry) is properly initialized and enabled. The driver is also tested (and known to work) with both ports operating in single port mode (active_slave 0 or 1). Tested on uBMC (dual emac mode, both ports in single mode, giga and fast ethernet) and BBB (single port, fast ethernet). Sponsored by: Rubicon Communications (Netgate)
2016-03-17 19:35:08 +00:00
#define CPDMA_BD_PKT_ERR_MASK (3 << 4)
#define CPDMA_BD_TO_PORT (1 << 4)
#define CPDMA_BD_PORT_MASK 3
Another overhaul of the CPSW driver for BeagleBone Major changes: * Finally tracked down the flow control setting that seems to have been causing TX stalls and watchdog timeouts * RX and TX paths now share a lot more code * TX interrupt is no longer used; we instead GC finished tx queue entries at the bottom of the start routine. * TX start now queues fragmented packets directly; it only invokes defrag() for occasional very fragmented packets. * "sysctl dev.cpsw" dumps controller statistics and queue counts * Host Error Interrupt will give extensive debugging information if the controller chokes on the queued data.
2013-02-03 01:08:01 +00:00
struct cpsw_cpdma_bd {
volatile uint32_t next;
volatile uint32_t bufptr;
volatile uint16_t buflen;
volatile uint16_t bufoff;
volatile uint16_t pktlen;
volatile uint16_t flags;
};
Merging of projects/armv6, part 10 - Support for Texas Instruments SoCs: - AM335x - OMAP4 - Kernel configs, DTS for Beaglebone and Pandaboard Submitted by: Ben Gray, Damjan Marion
2012-08-15 06:31:32 +00:00
#endif /*_IF_CPSWREG_H */
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