Add 16550 uart emulation as a PCI device. This allows it to
be activated as part of the slot config options. The syntax is: -s <slotnum>,uart[,stdio] The stdio parameter instructs the code to perform i/o using stdin/stdout. It can only be used for one instance. To allow legacy i/o ports/irqs to be used, a new variant of the slot command, -S, is introduced. When used to specify a slot, the device will use legacy resources if it supports them; otherwise it will be treated the same as the '-s' option. Specifying the -S option with the uart will first use the 0x3f8/irq 4 config, and the second -S will use 0x2F8/irq 3. Interrupt delivery is awaiting the arrival of the i/o apic code, but this works fine in uart(4)'s polled mode. This code was written by Cynthia Lu @ MIT while an intern at NetApp, with further work from neel@ and grehan@. Obtained from: NetApp
This commit is contained in:
parent
cd942e0f25
commit
0038ee9891
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/projects/bhyve/; revision=234938
@ -7,7 +7,7 @@ PROG= bhyve
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SRCS= atpic.c consport.c dbgport.c elcr.c fbsdrun.c inout.c
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SRCS+= instruction_emul.c mevent.c
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SRCS+= pci_emul.c pci_hostbridge.c pci_passthru.c pci_virtio_block.c
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SRCS+= pci_virtio_net.c pit_8254.c post.c rtc.c uart.c xmsr.c
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SRCS+= pci_virtio_net.c pci_uart.c pit_8254.c post.c rtc.c uart.c xmsr.c
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NO_MAN=
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@ -138,6 +138,7 @@ usage(int code)
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" -h: help\n"
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" -z: guest hz (default is %d)\n"
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" -s: <slot,driver,configinfo> PCI slot config\n"
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" -S: <slot,driver,configinfo> legacy PCI slot config\n"
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" -n: <slot,name> PCI slot naming\n"
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" -m: lowmem in MB\n"
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" -M: highmem in MB\n"
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@ -530,7 +531,7 @@ main(int argc, char *argv[])
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gdb_port = DEFAULT_GDB_PORT;
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guest_ncpus = 1;
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while ((c = getopt(argc, argv, "ehBHPxp:g:c:z:s:n:m:M:")) != -1) {
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while ((c = getopt(argc, argv, "ehBHPxp:g:c:z:s:S:n:m:M:")) != -1) {
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switch (c) {
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case 'B':
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inject_bkpt = 1;
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@ -554,7 +555,10 @@ main(int argc, char *argv[])
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guest_tslice = atoi(optarg);
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break;
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case 's':
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pci_parse_slot(optarg);
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pci_parse_slot(optarg, 0);
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break;
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case 'S':
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pci_parse_slot(optarg, 1);
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break;
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case 'n':
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pci_parse_name(optarg);
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@ -64,15 +64,27 @@ do { \
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#define MAXSLOTS 32
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static struct slotinfo {
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char *si_name;
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char *si_param;
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char *si_name;
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char *si_param;
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struct pci_devinst *si_devi;
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int si_titled;
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int si_pslot;
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char si_prefix;
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char si_suffix;
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int si_titled;
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int si_pslot;
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char si_prefix;
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char si_suffix;
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int si_legacy;
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} pci_slotinfo[MAXSLOTS];
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/*
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* Used to keep track of legacy interrupt owners/requestors
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*/
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#define NLIRQ 16
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static struct lirqinfo {
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int li_generic;
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int li_acount;
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struct pci_devinst *li_owner; /* XXX should be a list */
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} lirq[NLIRQ];
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/*
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* NetApp specific:
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* struct used to build an in-core OEM table to supply device names
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@ -147,7 +159,7 @@ pci_parse_slot_usage(char *aopt)
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}
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void
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pci_parse_slot(char *opt)
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pci_parse_slot(char *opt, int legacy)
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{
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char *slot, *emul, *config;
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char *str, *cpy;
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@ -174,6 +186,7 @@ pci_parse_slot(char *opt)
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} else {
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pci_slotinfo[snum].si_name = emul;
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pci_slotinfo[snum].si_param = config;
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pci_slotinfo[snum].si_legacy = legacy;
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}
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}
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@ -377,7 +390,12 @@ pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, uint64_t hostbase,
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addr = mask = lobits = 0;
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break;
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case PCIBAR_IO:
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baseptr = &pci_emul_iobase;
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if (hostbase && pci_slotinfo[pdi->pi_slot].si_legacy) {
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assert(hostbase < PCI_EMUL_IOBASE);
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baseptr = &hostbase;
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} else {
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baseptr = &pci_emul_iobase;
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}
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limit = PCI_EMUL_IOLIMIT;
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mask = PCIM_BAR_IO_BASE;
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lobits = PCIM_BAR_IO_SPACE;
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@ -729,6 +747,16 @@ init_pci(struct vmctx *ctx)
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}
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}
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pci_finish_mptable_names();
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/*
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* Allow ISA IRQs 5,10,11,12, and 15 to be available for
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* generic use
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*/
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lirq[5].li_generic = 1;
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lirq[10].li_generic = 1;
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lirq[11].li_generic = 1;
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lirq[12].li_generic = 1;
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lirq[15].li_generic = 1;
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}
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int
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@ -757,6 +785,69 @@ pci_generate_msi(struct pci_devinst *pi, int msg)
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}
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}
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int
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pci_is_legacy(struct pci_devinst *pi)
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{
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return (pci_slotinfo[pi->pi_slot].si_legacy);
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}
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static int
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pci_lintr_alloc(struct pci_devinst *pi, int vec)
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{
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int i;
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assert(vec < NLIRQ);
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if (vec == -1) {
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for (i = 0; i < NLIRQ; i++) {
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if (lirq[i].li_generic &&
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lirq[i].li_owner == NULL) {
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vec = i;
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break;
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}
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}
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} else {
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if (lirq[i].li_owner != NULL) {
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vec = -1;
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}
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}
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assert(vec != -1);
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lirq[vec].li_owner = pi;
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pi->pi_lintr_pin = vec;
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return (vec);
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}
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int
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pci_lintr_request(struct pci_devinst *pi, int vec)
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{
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vec = pci_lintr_alloc(pi, vec);
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pci_set_cfgdata8(pi, PCIR_INTLINE, vec);
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pci_set_cfgdata8(pi, PCIR_INTPIN, 1);
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return (0);
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}
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void
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pci_lintr_assert(struct pci_devinst *pi)
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{
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assert(pi->pi_lintr_pin);
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/* ioapic_assert_pin(pi->pi_vmctx, pi->pi_lintr_pin); */
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}
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void
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pci_lintr_deassert(struct pci_devinst *pi)
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{
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assert(pi->pi_lintr_pin);
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/* ioapic_deassert_pin(pi->pi_vmctx, pi->pi_lintr_pin); */
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}
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static int cfgbus, cfgslot, cfgfunc, cfgoff;
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static int
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@ -102,6 +102,7 @@ struct pci_devinst {
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struct pci_devemu *pi_d;
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struct vmctx *pi_vmctx;
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uint8_t pi_bus, pi_slot, pi_func;
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uint8_t pi_lintr_pin;
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char pi_name[PI_NAMESZ];
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uint16_t pi_iobase;
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int pi_bar_getsize;
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@ -149,22 +150,25 @@ struct msixcap {
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uint32_t pba_offset;
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} __packed;
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void init_pci(struct vmctx *ctx);
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void pci_parse_slot(char *opt);
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void pci_parse_name(char *opt);
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void pci_callback(void);
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int pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, uint64_t hostbase,
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enum pcibar_type type, uint64_t size);
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int pci_emul_add_msicap(struct pci_devinst *pi, int msgnum);
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void msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
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int bytes, uint32_t val);
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void msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
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int bytes, uint32_t val);
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void pci_generate_msi(struct pci_devinst *pi, int msgnum);
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int pci_msi_enabled(struct pci_devinst *pi);
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int pci_msi_msgnum(struct pci_devinst *pi);
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void pci_populate_msicap(struct msicap *cap, int msgs, int nextptr);
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void init_pci(struct vmctx *ctx);
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void msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
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int bytes, uint32_t val);
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void msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
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int bytes, uint32_t val);
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void pci_callback(void);
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int pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, uint64_t hostbase,
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enum pcibar_type type, uint64_t size);
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int pci_emul_add_msicap(struct pci_devinst *pi, int msgnum);
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int pci_is_legacy(struct pci_devinst *pi);
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void pci_generate_msi(struct pci_devinst *pi, int msgnum);
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void pci_lintr_assert(struct pci_devinst *pi);
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void pci_lintr_deassert(struct pci_devinst *pi);
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int pci_lintr_request(struct pci_devinst *pi, int ivec);
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int pci_msi_enabled(struct pci_devinst *pi);
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int pci_msi_msgnum(struct pci_devinst *pi);
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void pci_parse_name(char *opt);
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void pci_parse_slot(char *opt, int legacy);
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void pci_populate_msicap(struct msicap *cap, int msgs, int nextptr);
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static __inline void
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pci_set_cfgdata8(struct pci_devinst *pi, int offset, uint8_t val)
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599
usr.sbin/bhyve/pci_uart.c
Normal file
599
usr.sbin/bhyve/pci_uart.c
Normal file
@ -0,0 +1,599 @@
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/*-
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* Copyright (c) 2012 NetApp, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/types.h>
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#include <sys/select.h>
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#include <dev/ic/ns16550.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <assert.h>
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#include <termios.h>
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#include <unistd.h>
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#include <stdbool.h>
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#include <string.h>
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#include "fbsdrun.h"
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#include "pci_emul.h"
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#include "mevent.h"
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#define COM1_BASE 0x3F8
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#define COM1_IRQ 4
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#define COM2_BASE 0x2F8
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#define COM2_IRQ 3
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#define DEFAULT_RCLK 1843200
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#define DEFAULT_BAUD 9600
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#define FCR_RX_MASK 0xC0
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#define MCR_OUT1 0x04
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#define MCR_OUT2 0x08
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#define MSR_DELTA_MASK 0x0f
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#ifndef REG_SCR
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#define REG_SCR com_scr
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#endif
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#define FIFOSZ 16
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/*
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* Pick a PCI vid/did of a chip with a single uart at
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* BAR0, that most versions of FreeBSD can understand:
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* Siig CyberSerial 1-port.
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*/
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#define COM_VENDOR 0x131f
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#define COM_DEV 0x2000
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static int pci_uart_stdio; /* stdio in use for i/o */
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static int pci_uart_nldevs; /* number of legacy devices - 2 max */
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||||
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static struct {
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uint64_t baddr;
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int vector;
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} pci_uart_lres[] = {
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{ COM1_BASE, COM1_IRQ},
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{ COM2_BASE, COM2_IRQ},
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{ 0, 0 }
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};
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struct fifo {
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uint8_t buf[FIFOSZ];
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int rindex; /* index to read from */
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int windex; /* index to write to */
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int num; /* number of characters in the fifo */
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int size; /* size of the fifo */
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};
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struct pci_uart_softc {
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struct pci_devinst *pi;
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uint8_t data; /* Data register (R/W) */
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uint8_t ier; /* Interrupt enable register (R/W) */
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uint8_t lcr; /* Line control register (R/W) */
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uint8_t mcr; /* Modem control register (R/W) */
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uint8_t lsr; /* Line status register (R/W) */
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uint8_t msr; /* Modem status register (R/W) */
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uint8_t fcr; /* FIFO control register (W) */
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uint8_t scr; /* Scratch register (R/W) */
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uint8_t dll; /* Baudrate divisor latch LSB */
|
||||
uint8_t dlh; /* Baudrate divisor latch MSB */
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|
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struct fifo rxfifo;
|
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|
||||
int opened;
|
||||
int stdio;
|
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bool thre_int_pending; /* THRE interrupt pending */
|
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};
|
||||
|
||||
static void pci_uart_drain(int fd, enum ev_type ev, void *arg);
|
||||
|
||||
static struct termios tio_orig, tio_new; /* I/O Terminals */
|
||||
|
||||
static void
|
||||
ttyclose(void)
|
||||
{
|
||||
tcsetattr(STDIN_FILENO, TCSANOW, &tio_orig);
|
||||
}
|
||||
|
||||
static void
|
||||
ttyopen(void)
|
||||
{
|
||||
tcgetattr(STDIN_FILENO, &tio_orig);
|
||||
|
||||
cfmakeraw(&tio_new);
|
||||
tcsetattr(STDIN_FILENO, TCSANOW, &tio_new);
|
||||
|
||||
atexit(ttyclose);
|
||||
}
|
||||
|
||||
static bool
|
||||
tty_char_available(void)
|
||||
{
|
||||
fd_set rfds;
|
||||
struct timeval tv;
|
||||
|
||||
FD_ZERO(&rfds);
|
||||
FD_SET(STDIN_FILENO, &rfds);
|
||||
tv.tv_sec = 0;
|
||||
tv.tv_usec = 0;
|
||||
if (select(STDIN_FILENO + 1, &rfds, NULL, NULL, &tv) > 0 ) {
|
||||
return (true);
|
||||
} else {
|
||||
return (false);
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
ttyread(void)
|
||||
{
|
||||
char rb;
|
||||
|
||||
if (tty_char_available()) {
|
||||
read(STDIN_FILENO, &rb, 1);
|
||||
return (rb & 0xff);
|
||||
} else {
|
||||
return (-1);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
ttywrite(unsigned char wb)
|
||||
{
|
||||
(void) write(STDIN_FILENO, &wb, 1);
|
||||
}
|
||||
|
||||
static void
|
||||
fifo_reset(struct fifo *fifo, int size)
|
||||
{
|
||||
bzero(fifo, sizeof(struct fifo));
|
||||
fifo->size = size;
|
||||
}
|
||||
|
||||
static int
|
||||
fifo_putchar(struct fifo *fifo, uint8_t ch)
|
||||
{
|
||||
|
||||
if (fifo->num < fifo->size) {
|
||||
fifo->buf[fifo->windex] = ch;
|
||||
fifo->windex = (fifo->windex + 1) % fifo->size;
|
||||
fifo->num++;
|
||||
return (0);
|
||||
} else
|
||||
return (-1);
|
||||
}
|
||||
|
||||
static int
|
||||
fifo_getchar(struct fifo *fifo)
|
||||
{
|
||||
int c;
|
||||
|
||||
if (fifo->num > 0) {
|
||||
c = fifo->buf[fifo->rindex];
|
||||
fifo->rindex = (fifo->rindex + 1) % fifo->size;
|
||||
fifo->num--;
|
||||
return (c);
|
||||
} else
|
||||
return (-1);
|
||||
}
|
||||
|
||||
static int
|
||||
fifo_numchars(struct fifo *fifo)
|
||||
{
|
||||
|
||||
return (fifo->num);
|
||||
}
|
||||
|
||||
static void
|
||||
pci_uart_opentty(struct pci_uart_softc *sc)
|
||||
{
|
||||
struct mevent *mev;
|
||||
|
||||
assert(sc->opened == 0);
|
||||
assert(sc->stdio);
|
||||
|
||||
ttyopen();
|
||||
mev = mevent_add(STDIN_FILENO, EVF_READ, pci_uart_drain, sc);
|
||||
assert(mev);
|
||||
}
|
||||
|
||||
static void
|
||||
pci_uart_legacy_res(uint64_t *bar, int *ivec)
|
||||
{
|
||||
if (pci_uart_lres[pci_uart_nldevs].baddr != 0) {
|
||||
*bar = pci_uart_lres[pci_uart_nldevs].baddr;
|
||||
*ivec = pci_uart_lres[pci_uart_nldevs].vector;
|
||||
pci_uart_nldevs++;
|
||||
} else {
|
||||
/* TODO: print warning ? */
|
||||
*bar = 0;
|
||||
*ivec= -1;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* The IIR returns a prioritized interrupt reason:
|
||||
* - receive data available
|
||||
* - transmit holding register empty
|
||||
* - modem status change
|
||||
*
|
||||
* Return an interrupt reason if one is available.
|
||||
*/
|
||||
static int
|
||||
pci_uart_intr_reason(struct pci_uart_softc *sc)
|
||||
{
|
||||
|
||||
if ((sc->lsr & LSR_OE) != 0 && (sc->ier & IER_ERLS) != 0)
|
||||
return (IIR_RLS);
|
||||
else if (fifo_numchars(&sc->rxfifo) > 0 && (sc->ier & IER_ERXRDY) != 0)
|
||||
return (IIR_RXTOUT);
|
||||
else if (sc->thre_int_pending && (sc->ier & IER_ETXRDY) != 0)
|
||||
return (IIR_TXRDY);
|
||||
else if ((sc->msr & MSR_DELTA_MASK) != 0 && (sc->ier & IER_EMSC) != 0)
|
||||
return (IIR_MLSC);
|
||||
else
|
||||
return (IIR_NOPEND);
|
||||
}
|
||||
|
||||
static void
|
||||
pci_uart_reset(struct pci_uart_softc *sc)
|
||||
{
|
||||
uint16_t divisor;
|
||||
|
||||
divisor = DEFAULT_RCLK / DEFAULT_BAUD / 16;
|
||||
sc->dll = divisor;
|
||||
sc->dlh = divisor >> 16;
|
||||
|
||||
fifo_reset(&sc->rxfifo, 1); /* no fifo until enabled by software */
|
||||
}
|
||||
|
||||
/*
|
||||
* Toggle the COM port's intr pin depending on whether or not we have an
|
||||
* interrupt condition to report to the processor.
|
||||
*/
|
||||
static void
|
||||
pci_uart_toggle_intr(struct pci_uart_softc *sc)
|
||||
{
|
||||
uint8_t intr_reason;
|
||||
|
||||
intr_reason = pci_uart_intr_reason(sc);
|
||||
|
||||
if (intr_reason == IIR_NOPEND)
|
||||
pci_lintr_deassert(sc->pi);
|
||||
else
|
||||
pci_lintr_assert(sc->pi);
|
||||
}
|
||||
|
||||
static void
|
||||
pci_uart_drain(int fd, enum ev_type ev, void *arg)
|
||||
{
|
||||
struct pci_uart_softc *sc;
|
||||
int ch;
|
||||
|
||||
sc = arg;
|
||||
|
||||
assert(fd == STDIN_FILENO);
|
||||
assert(ev == EVF_READ);
|
||||
|
||||
while ((ch = ttyread()) != -1) {
|
||||
/*
|
||||
* If we are in loopback mode then drop this character.
|
||||
*/
|
||||
if ((sc->mcr & MCR_LOOPBACK) != 0)
|
||||
continue;
|
||||
|
||||
if (fifo_putchar(&sc->rxfifo, ch) != 0)
|
||||
sc->lsr |= LSR_OE;
|
||||
}
|
||||
|
||||
pci_uart_toggle_intr(sc);
|
||||
}
|
||||
|
||||
static void
|
||||
pci_uart_write(struct pci_devinst *pi, int baridx, int offset, int size,
|
||||
uint32_t value)
|
||||
{
|
||||
struct pci_uart_softc *sc;
|
||||
int fifosz;
|
||||
uint8_t msr;
|
||||
|
||||
sc = pi->pi_arg;
|
||||
|
||||
assert(size == 1);
|
||||
|
||||
/* Open terminal */
|
||||
if (!sc->opened && sc->stdio) {
|
||||
pci_uart_opentty(sc);
|
||||
sc->opened = 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Take care of the special case DLAB accesses first
|
||||
*/
|
||||
if ((sc->lcr & LCR_DLAB) != 0) {
|
||||
if (offset == REG_DLL) {
|
||||
sc->dll = value;
|
||||
goto done;
|
||||
}
|
||||
|
||||
if (offset == REG_DLH) {
|
||||
sc->dlh = value;
|
||||
goto done;
|
||||
}
|
||||
}
|
||||
|
||||
switch (offset) {
|
||||
case REG_DATA:
|
||||
if (sc->mcr & MCR_LOOPBACK) {
|
||||
if (fifo_putchar(&sc->rxfifo, value) != 0)
|
||||
sc->lsr |= LSR_OE;
|
||||
} else if (sc->stdio) {
|
||||
ttywrite(value);
|
||||
} /* else drop on floor */
|
||||
sc->thre_int_pending = true;
|
||||
break;
|
||||
case REG_IER:
|
||||
/*
|
||||
* Apply mask so that bits 4-7 are 0
|
||||
* Also enables bits 0-3 only if they're 1
|
||||
*/
|
||||
sc->ier = value & 0x0F;
|
||||
break;
|
||||
case REG_FCR:
|
||||
/*
|
||||
* When moving from FIFO and 16450 mode and vice versa,
|
||||
* the FIFO contents are reset.
|
||||
*/
|
||||
if ((sc->fcr & FCR_ENABLE) ^ (value & FCR_ENABLE)) {
|
||||
fifosz = (value & FCR_ENABLE) ? FIFOSZ : 1;
|
||||
fifo_reset(&sc->rxfifo, fifosz);
|
||||
}
|
||||
|
||||
/*
|
||||
* The FCR_ENABLE bit must be '1' for the programming
|
||||
* of other FCR bits to be effective.
|
||||
*/
|
||||
if ((value & FCR_ENABLE) == 0) {
|
||||
sc->fcr = 0;
|
||||
} else {
|
||||
if ((value & FCR_RCV_RST) != 0)
|
||||
fifo_reset(&sc->rxfifo, FIFOSZ);
|
||||
|
||||
sc->fcr = value &
|
||||
(FCR_ENABLE | FCR_DMA | FCR_RX_MASK);
|
||||
}
|
||||
break;
|
||||
case REG_LCR:
|
||||
sc->lcr = value;
|
||||
break;
|
||||
case REG_MCR:
|
||||
/* Apply mask so that bits 5-7 are 0 */
|
||||
sc->mcr = value & 0x1F;
|
||||
|
||||
msr = 0;
|
||||
if (sc->mcr & MCR_LOOPBACK) {
|
||||
/*
|
||||
* In the loopback mode certain bits from the
|
||||
* MCR are reflected back into MSR
|
||||
*/
|
||||
if (sc->mcr & MCR_RTS)
|
||||
msr |= MSR_CTS;
|
||||
if (sc->mcr & MCR_DTR)
|
||||
msr |= MSR_DSR;
|
||||
if (sc->mcr & MCR_OUT1)
|
||||
msr |= MSR_RI;
|
||||
if (sc->mcr & MCR_OUT2)
|
||||
msr |= MSR_DCD;
|
||||
}
|
||||
|
||||
/*
|
||||
* Detect if there has been any change between the
|
||||
* previous and the new value of MSR. If there is
|
||||
* then assert the appropriate MSR delta bit.
|
||||
*/
|
||||
if ((msr & MSR_CTS) ^ (sc->msr & MSR_CTS))
|
||||
sc->msr |= MSR_DCTS;
|
||||
if ((msr & MSR_DSR) ^ (sc->msr & MSR_DSR))
|
||||
sc->msr |= MSR_DDSR;
|
||||
if ((msr & MSR_DCD) ^ (sc->msr & MSR_DCD))
|
||||
sc->msr |= MSR_DDCD;
|
||||
if ((sc->msr & MSR_RI) != 0 && (msr & MSR_RI) == 0)
|
||||
sc->msr |= MSR_TERI;
|
||||
|
||||
/*
|
||||
* Update the value of MSR while retaining the delta
|
||||
* bits.
|
||||
*/
|
||||
sc->msr &= MSR_DELTA_MASK;
|
||||
sc->msr |= msr;
|
||||
break;
|
||||
case REG_LSR:
|
||||
/*
|
||||
* Line status register is not meant to be written to
|
||||
* during normal operation.
|
||||
*/
|
||||
break;
|
||||
case REG_MSR:
|
||||
/*
|
||||
* As far as I can tell MSR is a read-only register.
|
||||
*/
|
||||
break;
|
||||
case REG_SCR:
|
||||
sc->scr = value;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
done:
|
||||
pci_uart_toggle_intr(sc);
|
||||
}
|
||||
|
||||
uint32_t
|
||||
pci_uart_read(struct pci_devinst *pi, int baridx, int offset, int size)
|
||||
{
|
||||
struct pci_uart_softc *sc;
|
||||
uint8_t iir, intr_reason;
|
||||
uint32_t reg;
|
||||
|
||||
sc = pi->pi_arg;
|
||||
|
||||
assert(size == 1);
|
||||
|
||||
/* Open terminal */
|
||||
if (!sc->opened && sc->stdio) {
|
||||
pci_uart_opentty(sc);
|
||||
sc->opened = 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Take care of the special case DLAB accesses first
|
||||
*/
|
||||
if ((sc->lcr & LCR_DLAB) != 0) {
|
||||
if (offset == REG_DLL) {
|
||||
reg = sc->dll;
|
||||
goto done;
|
||||
}
|
||||
|
||||
if (offset == REG_DLH) {
|
||||
reg = sc->dlh;
|
||||
goto done;
|
||||
}
|
||||
}
|
||||
|
||||
switch (offset) {
|
||||
case REG_DATA:
|
||||
reg = fifo_getchar(&sc->rxfifo);
|
||||
break;
|
||||
case REG_IER:
|
||||
reg = sc->ier;
|
||||
break;
|
||||
case REG_IIR:
|
||||
iir = (sc->fcr & FCR_ENABLE) ? IIR_FIFO_MASK : 0;
|
||||
|
||||
intr_reason = pci_uart_intr_reason(sc);
|
||||
|
||||
/*
|
||||
* Deal with side effects of reading the IIR register
|
||||
*/
|
||||
if (intr_reason == IIR_TXRDY)
|
||||
sc->thre_int_pending = false;
|
||||
|
||||
iir |= intr_reason;
|
||||
|
||||
reg = iir;
|
||||
break;
|
||||
case REG_LCR:
|
||||
reg = sc->lcr;
|
||||
break;
|
||||
case REG_MCR:
|
||||
reg = sc->mcr;
|
||||
break;
|
||||
case REG_LSR:
|
||||
/* Transmitter is always ready for more data */
|
||||
sc->lsr |= LSR_TEMT | LSR_THRE;
|
||||
|
||||
/* Check for new receive data */
|
||||
if (fifo_numchars(&sc->rxfifo) > 0)
|
||||
sc->lsr |= LSR_RXRDY;
|
||||
else
|
||||
sc->lsr &= ~LSR_RXRDY;
|
||||
|
||||
reg = sc->lsr;
|
||||
|
||||
/* The LSR_OE bit is cleared on LSR read */
|
||||
sc->lsr &= ~LSR_OE;
|
||||
break;
|
||||
case REG_MSR:
|
||||
/*
|
||||
* MSR delta bits are cleared on read
|
||||
*/
|
||||
reg = sc->msr;
|
||||
sc->msr &= ~MSR_DELTA_MASK;
|
||||
break;
|
||||
case REG_SCR:
|
||||
reg = sc->scr;
|
||||
break;
|
||||
default:
|
||||
reg = 0xFF;
|
||||
break;
|
||||
}
|
||||
|
||||
done:
|
||||
pci_uart_toggle_intr(sc);
|
||||
return (reg);
|
||||
}
|
||||
|
||||
static int
|
||||
pci_uart_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
|
||||
{
|
||||
struct pci_uart_softc *sc;
|
||||
uint64_t bar;
|
||||
int ivec;
|
||||
|
||||
sc = malloc(sizeof(struct pci_uart_softc));
|
||||
memset(sc, 0, sizeof(struct pci_uart_softc));
|
||||
|
||||
pi->pi_arg = sc;
|
||||
sc->pi = pi;
|
||||
|
||||
/* initialize config space */
|
||||
pci_set_cfgdata16(pi, PCIR_DEVICE, COM_DEV);
|
||||
pci_set_cfgdata16(pi, PCIR_VENDOR, COM_VENDOR);
|
||||
pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_SIMPLECOMM);
|
||||
if (pci_is_legacy(pi)) {
|
||||
pci_uart_legacy_res(&bar, &ivec);
|
||||
} else {
|
||||
bar = 0;
|
||||
ivec = -1;
|
||||
}
|
||||
pci_emul_alloc_bar(pi, 0, bar, PCIBAR_IO, 8);
|
||||
pci_lintr_request(pi, ivec);
|
||||
|
||||
if (!strcmp("stdio", opts) && !pci_uart_stdio) {
|
||||
pci_uart_stdio = 1;
|
||||
sc->stdio = 1;
|
||||
}
|
||||
|
||||
pci_uart_reset(sc);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
struct pci_devemu pci_de_com = {
|
||||
.pe_emu = "uart",
|
||||
.pe_init = pci_uart_init,
|
||||
.pe_iow = pci_uart_write,
|
||||
.pe_ior = pci_uart_read,
|
||||
};
|
||||
PCI_EMUL_SET(pci_de_com);
|
Loading…
Reference in New Issue
Block a user