Import device-tree files from Linux 5.19
This commit is contained in:
Emmanuel Vadot
parent
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commit
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45
Bindings/arm/arm,corstone1000.yaml
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45
Bindings/arm/arm,corstone1000.yaml
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@ -0,0 +1,45 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/arm,corstone1000.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM Corstone1000 Device Tree Bindings
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maintainers:
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- Vishnu Banavath <vishnu.banavath@arm.com>
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- Rui Miguel Silva <rui.silva@linaro.org>
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description: |+
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ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that
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provides a flexible compute architecture that combines Cortex‑A and Cortex‑M
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processors.
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Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion
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systems for M-Class (or other) processors for adding sensors, connectivity,
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video, audio and machine learning at the edge System and security IPs to build
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a secure SoC for a range of rich IoT applications, for example gateways, smart
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cameras and embedded systems.
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Integrated Secure Enclave providing hardware Root of Trust and supporting
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seamless integration of the optional CryptoCell™-312 cryptographic
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accelerator.
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properties:
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$nodename:
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const: '/'
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compatible:
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oneOf:
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- description: Corstone1000 MPS3 it has 1 Cortex-A35 CPU core in a FPGA
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implementation of the Corstone1000 in the MPS3 prototyping board. See
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ARM document DAI0550.
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items:
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- const: arm,corstone1000-mps3
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- description: Corstone1000 FVP is the Fixed Virtual Platform
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implementation of this system. See ARM ecosystems FVP's.
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items:
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- const: arm,corstone1000-fvp
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additionalProperties: true
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...
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@ -64,6 +64,7 @@ properties:
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- description: BCM47094 based boards
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items:
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- enum:
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- asus,rt-ac88u
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- dlink,dir-885l
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- linksys,panamera
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- luxul,abr-4500-v1
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@ -83,9 +84,14 @@ properties:
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- brcm,bcm953012er
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- brcm,bcm953012hr
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- brcm,bcm953012k
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- const: brcm,bcm53012
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- const: brcm,bcm4708
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- description: BCM53016 based boards
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items:
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- enum:
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- meraki,mr32
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- const: brcm,brcm53012
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- const: brcm,brcm53016
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- const: brcm,bcm53016
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- const: brcm,bcm4708
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additionalProperties: true
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@ -30,7 +30,7 @@ Example:
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cpus {
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cpu@0 {
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compatible = "arm,cotex-a9";
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compatible = "arm,cortex-a9";
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reg = <0>;
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...
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enable-method = "brcm,bcm63138";
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33
Bindings/arm/bcm/brcm,bcmbca.yaml
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33
Bindings/arm/bcm/brcm,bcmbca.yaml
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@ -0,0 +1,33 @@
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# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/bcm/brcm,bcmbca.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Broadcom Broadband SoC device tree bindings
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description:
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Broadcom Broadband SoCs include family of high performance DSL/PON/Wireless
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chips that can be used as home gateway, router and WLAN AP for residential,
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enterprise and carrier applications.
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maintainers:
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- William Zhang <william.zhang@broadcom.com>
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- Anand Gore <anand.gore@broadcom.com>
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- Kursad Oney <kursad.oney@broadcom.com>
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properties:
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$nodename:
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const: '/'
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compatible:
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oneOf:
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- description: BCM47622 based boards
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items:
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- enum:
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- brcm,bcm947622
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- const: brcm,bcm47622
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- const: brcm,bcmbca
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additionalProperties: true
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...
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@ -172,7 +172,7 @@ properties:
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- karo,tx53 # Ka-Ro electronics TX53 module
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- kiebackpeter,imx53-ddc # K+P imx53 DDC
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- kiebackpeter,imx53-hsc # K+P imx53 HSC
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- menlo,m53menlo
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- menlo,m53menlo # i.MX53 Menlo board
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- voipac,imx53-dmm-668 # Voipac i.MX53 X53-DMM-668
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- const: fsl,imx53
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@ -192,6 +192,7 @@ properties:
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items:
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- enum:
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- auvidea,h100 # Auvidea H100
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- bosch,imx6q-acc # Bosch ACC i.MX6 Dual
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- boundary,imx6q-nitrogen6_max
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- boundary,imx6q-nitrogen6_som2
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- boundary,imx6q-nitrogen6x
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@ -411,7 +412,6 @@ properties:
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- technologic,imx6dl-ts4900
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- technologic,imx6dl-ts7970
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- toradex,colibri_imx6dl # Colibri iMX6 Modules
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- toradex,colibri_imx6dl-v1_1 # Colibri iMX6 V1.1 Modules
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- udoo,imx6dl-udoo # Udoo i.MX6 Dual-lite Board
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- vdl,lanmcu # Van der Laan LANMCU board
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- wand,imx6dl-wandboard # Wandboard i.MX6 Dual Lite Board
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@ -488,17 +488,13 @@ properties:
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- description: i.MX6DL Boards with Toradex Colibri iMX6DL/S Modules
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items:
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- enum:
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- toradex,colibri_imx6dl-aster # Colibri iMX6DL/S Module on Aster Board
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- toradex,colibri_imx6dl-eval-v3 # Colibri iMX6DL/S Module on Colibri Evaluation Board V3
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- toradex,colibri_imx6dl-iris # Colibri iMX6DL/S Module on Iris Board
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- toradex,colibri_imx6dl-iris-v2 # Colibri iMX6DL/S Module on Iris Board V2
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- const: toradex,colibri_imx6dl # Colibri iMX6DL/S Module
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- const: fsl,imx6dl
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- description: i.MX6DL Boards with Toradex Colibri iMX6DL/S V1.1 Modules
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items:
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- enum:
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- toradex,colibri_imx6dl-v1_1-eval-v3 # Colibri iMX6DL/S V1.1 M. on Colibri Evaluation Board V3
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- const: toradex,colibri_imx6dl-v1_1 # Colibri iMX6DL/S V1.1 Module
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- const: fsl,imx6dl
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- description: i.MX6S DHCOM DRC02 Board
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items:
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- const: dh,imx6s-dhcom-drc02
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@ -613,6 +609,28 @@ properties:
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- const: kontron,imx6ul-n6310-som
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- const: fsl,imx6ul
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- description: TQ-Systems TQMa6UL1 SoM on MBa6ULx board
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items:
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- enum:
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- tq,imx6ul-tqma6ul1-mba6ulx
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- const: tq,imx6ul-tqma6ul1 # MCIMX6G1
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- const: fsl,imx6ul
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- description: TQ-Systems TQMa6UL2 SoM on MBa6ULx board
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items:
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- enum:
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- tq,imx6ul-tqma6ul2-mba6ulx
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- const: tq,imx6ul-tqma6ul2 # MCIMX6G2
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- const: fsl,imx6ul
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- description: TQ-Systems TQMa6ULxL SoM on MBa6ULx[L] board
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items:
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- enum:
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- tq,imx6ul-tqma6ul2l-mba6ulx # using LGA adapter
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- tq,imx6ul-tqma6ul2l-mba6ulxl
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- const: tq,imx6ul-tqma6ul2l # MCIMX6G2, LGA SoM variant
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- const: fsl,imx6ul
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- description: i.MX6ULL based Boards
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items:
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- enum:
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@ -640,26 +658,44 @@ properties:
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- const: phytec,imx6ull-pcl063 # PHYTEC phyCORE-i.MX 6ULL
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- const: fsl,imx6ull
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- description: i.MX6ULL PHYTEC phyGATE-Tauri
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items:
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- enum:
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- phytec,imx6ull-phygate-tauri-emmc
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- phytec,imx6ull-phygate-tauri-nand
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- const: phytec,imx6ull-phygate-tauri # PHYTEC phyGATE-Tauri with i.MX6 ULL
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- const: phytec,imx6ull-pcl063 # PHYTEC phyCORE-i.MX 6ULL
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- const: fsl,imx6ull
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- description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Modules
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items:
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- enum:
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- toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Evaluation Board
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- toradex,colibri-imx6ull-aster # Colibri iMX6ULL Module on Aster Carrier Board
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- toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Evaluation Board V3
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- toradex,colibri-imx6ull-iris # Colibri iMX6ULL Module on Iris Carrier Board
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- toradex,colibri-imx6ull-iris-v2 # Colibri iMX6ULL Module on Iris V2 Carrier Board
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- const: toradex,colibri-imx6ull # Colibri iMX6ULL Module
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- const: fsl,imx6dl
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- const: fsl,imx6ull
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- description: i.MX6ULL Boards with Toradex Colibri iMX6ULL 1GB (eMMC) Module
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items:
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- enum:
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- toradex,colibri-imx6ull-emmc-eval # Colibri iMX6ULL 1GB (eMMC) M. on Colibri Evaluation Board
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- const: toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module
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- const: fsl,imx6dl
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- toradex,colibri-imx6ull-emmc-aster # Colibri iMX6ULL 1G (eMMC) on Aster Carrier Board
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- toradex,colibri-imx6ull-emmc-eval # Colibri iMX6ULL 1G (eMMC) on Colibri Evaluation B. V3
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- toradex,colibri-imx6ull-emmc-iris # Colibri iMX6ULL 1G (eMMC) on Iris Carrier Board
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- toradex,colibri-imx6ull-emmc-iris-v2 # Colibri iMX6ULL 1G (eMMC) on Iris V2 Carrier Board
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- const: toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module
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- const: fsl,imx6ull
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- description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Wi-Fi / BT Modules
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items:
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- enum:
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- toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / BT M. on Colibri Evaluation Board
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- const: toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Module
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- const: fsl,imx6dl
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- toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / BT M. on Colibri Eval. B. V3
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- toradex,colibri-imx6ull-wifi-aster # Colibri iMX6ULL Wi-Fi / BT M. on Aster Carrier Board
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- toradex,colibri-imx6ull-wifi-iris # Colibri iMX6ULL Wi-Fi / BT M. on Iris Carrier Board
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- toradex,colibri-imx6ull-wifi-iris-v2 # Colibri iMX6ULL Wi-Fi / BT M. on Iris V2 Carrier Board
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- const: toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Module
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- const: fsl,imx6ull
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- description: Kontron N6411 S Board
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items:
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@ -667,6 +703,21 @@ properties:
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- const: kontron,imx6ull-n6411-som
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- const: fsl,imx6ull
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- description: TQ Systems TQMa6ULLx SoM on MBa6ULx board
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items:
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- enum:
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- tq,imx6ull-tqma6ull2-mba6ulx
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- const: tq,imx6ull-tqma6ull2 # MCIMX6Y2
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- const: fsl,imx6ull
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- description: TQ Systems TQMa6ULLxL SoM on MBa6ULx[L] board
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items:
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- enum:
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- tq,imx6ull-tqma6ull2l-mba6ulx # using LGA adapter
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- tq,imx6ull-tqma6ull2l-mba6ulxl
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- const: tq,imx6ull-tqma6ull2l # MCIMX6Y2, LGA SoM variant
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- const: fsl,imx6ull
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- description: i.MX6ULZ based Boards
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items:
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- enum:
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@ -707,6 +758,7 @@ properties:
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- kam,imx7d-flex-concentrator-mfg # Kamstrup OMNIA Flex Concentrator in manufacturing mode
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- novtech,imx7d-meerkat96 # i.MX7 Meerkat96 Board
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- remarkable,imx7d-remarkable2 # i.MX7D ReMarkable 2 E-Ink Tablet
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- storopack,imx7d-smegw01 # Storopack i.MX7D SMEGW01
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- technexion,imx7d-pico-dwarf # TechNexion i.MX7D Pico-Dwarf
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- technexion,imx7d-pico-hobbit # TechNexion i.MX7D Pico-Hobbit
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- technexion,imx7d-pico-nymph # TechNexion i.MX7D Pico-Nymph
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@ -762,6 +814,7 @@ properties:
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- enum:
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- beacon,imx8mm-beacon-kit # i.MX8MM Beacon Development Kit
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- boundary,imx8mm-nitrogen8mm # i.MX8MM Nitrogen Board
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- dmo,imx8mm-data-modul-edm-sbc # i.MX8MM eDM SBC
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- emtrion,emcon-mx8mm-avari # emCON-MX8MM SoM on Avari Base
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- fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board
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- fsl,imx8mm-evk # i.MX8MM EVK Board
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@ -772,6 +825,7 @@ properties:
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- gw,imx8mm-gw7902 # i.MX8MM Gateworks Board
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- gw,imx8mm-gw7903 # i.MX8MM Gateworks Board
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- kontron,imx8mm-n801x-som # i.MX8MM Kontron SL (N801X) SOM
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- menlo,mx8menlo # i.MX8MM Menlo board with Verdin SoM
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- toradex,verdin-imx8mm # Verdin iMX8M Mini Modules
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- toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Modules without Wi-Fi / BT
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- toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Modules
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@ -834,6 +888,7 @@ properties:
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- beacon,imx8mn-beacon-kit # i.MX8MN Beacon Development Kit
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- bsh,imx8mn-bsh-smm-s2 # i.MX8MN BSH SystemMaster S2
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- bsh,imx8mn-bsh-smm-s2pro # i.MX8MN BSH SystemMaster S2 PRO
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- fsl,imx8mn-ddr3l-evk # i.MX8MN DDR3L EVK Board
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- fsl,imx8mn-ddr4-evk # i.MX8MN DDR4 EVK Board
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- fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board
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- gw,imx8mn-gw7902 # i.MX8MM Gateworks Board
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@ -860,6 +915,17 @@ properties:
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items:
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- enum:
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- fsl,imx8mp-evk # i.MX8MP EVK Board
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- gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board
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- toradex,verdin-imx8mp # Verdin iMX8M Plus Modules
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- toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Modules without Wi-Fi / BT
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- toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules
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- const: fsl,imx8mp
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- description: Engicam i.Core MX8M Plus SoM based boards
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items:
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- enum:
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- engicam,icore-mx8mp-edimm2.2 # i.MX8MP Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit
|
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- const: engicam,icore-mx8mp # i.MX8MP Engicam i.Core MX8M Plus SoM
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- const: fsl,imx8mp
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- description: PHYTEC phyCORE-i.MX8MP SoM based boards
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@ -868,6 +934,24 @@ properties:
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- const: phytec,imx8mp-phycore-som # phyCORE-i.MX8MP SoM
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- const: fsl,imx8mp
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- description: Toradex Boards with Verdin iMX8M Plus Modules
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items:
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- enum:
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- toradex,verdin-imx8mp-nonwifi-dahlia # Verdin iMX8M Plus Module on Dahlia
|
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- toradex,verdin-imx8mp-nonwifi-dev # Verdin iMX8M Plus Module on Verdin Development Board
|
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- const: toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Module without Wi-Fi / BT
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- const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module
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- const: fsl,imx8mp
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- description: Toradex Boards with Verdin iMX8M Plus Wi-Fi / BT Modules
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items:
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- enum:
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- toradex,verdin-imx8mp-wifi-dahlia # Verdin iMX8M Plus Wi-Fi / BT Module on Dahlia
|
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- toradex,verdin-imx8mp-wifi-dev # Verdin iMX8M Plus Wi-Fi / BT M. on Verdin Development B.
|
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- const: toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Module
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- const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module
|
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- const: fsl,imx8mp
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- description: i.MX8MQ based Boards
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items:
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- enum:
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@ -999,6 +1083,7 @@ properties:
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- description: LS1021A based Boards
|
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items:
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- enum:
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- fsl,ls1021a-iot
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- fsl,ls1021a-moxa-uc-8410a
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- fsl,ls1021a-qds
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- fsl,ls1021a-tsn
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@ -17,14 +17,15 @@ properties:
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- const: hisilicon,hip04-bootwrapper
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boot-method:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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description: |
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Address and size of boot method.
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[0]: bootwrapper physical address
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[1]: bootwrapper size
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[2]: relocation physical address
|
||||
[3]: relocation size
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
minItems: 2
|
||||
maxItems: 4
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
27
Bindings/arm/hpe,gxp.yaml
Normal file
27
Bindings/arm/hpe,gxp.yaml
Normal file
@ -0,0 +1,27 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/hpe,gxp.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: HPE BMC GXP platforms
|
||||
|
||||
maintainers:
|
||||
- Nick Hawkins <nick.hawkins@hpe.com>
|
||||
- Jean-Marie Verdun <verdun@hpe.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: GXP Based Boards
|
||||
items:
|
||||
- enum:
|
||||
- hpe,gxp-dl360gen10
|
||||
- const: hpe,gxp
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
...
|
||||
@ -18,6 +18,7 @@ properties:
|
||||
items:
|
||||
- enum:
|
||||
- intel,n5x-socdk
|
||||
- intel,socfpga-agilex-n6000
|
||||
- intel,socfpga-agilex-socdk
|
||||
- const: intel,socfpga-agilex
|
||||
|
||||
|
||||
@ -133,6 +133,11 @@ properties:
|
||||
- const: mediatek,mt8183
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8192-evb
|
||||
- const: mediatek,mt8192
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8195-demo
|
||||
- mediatek,mt8195-evb
|
||||
- const: mediatek,mt8195
|
||||
- description: Google Burnet (HP Chromebook x360 11MK G3 EE)
|
||||
|
||||
81
Bindings/arm/mediatek/mediatek,infracfg.yaml
Normal file
81
Bindings/arm/mediatek/mediatek,infracfg.yaml
Normal file
@ -0,0 +1,81 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: MediaTek Infrastructure System Configuration Controller
|
||||
|
||||
maintainers:
|
||||
- Matthias Brugger <matthias.bgg@gmail.com>
|
||||
|
||||
description:
|
||||
The Mediatek infracfg controller provides various clocks and reset outputs
|
||||
to the system. The clock values can be found in <dt-bindings/clock/mt*-clk.h>,
|
||||
and reset values in <dt-bindings/reset/mt*-reset.h> and
|
||||
<dt-bindings/reset/mt*-resets.h>.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt2701-infracfg
|
||||
- mediatek,mt2712-infracfg
|
||||
- mediatek,mt6765-infracfg
|
||||
- mediatek,mt6779-infracfg_ao
|
||||
- mediatek,mt6797-infracfg
|
||||
- mediatek,mt7622-infracfg
|
||||
- mediatek,mt7629-infracfg
|
||||
- mediatek,mt7986-infracfg
|
||||
- mediatek,mt8135-infracfg
|
||||
- mediatek,mt8167-infracfg
|
||||
- mediatek,mt8173-infracfg
|
||||
- mediatek,mt8183-infracfg
|
||||
- mediatek,mt8516-infracfg
|
||||
- const: syscon
|
||||
- items:
|
||||
- const: mediatek,mt7623-infracfg
|
||||
- const: mediatek,mt2701-infracfg
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- mediatek,mt2701-infracfg
|
||||
- mediatek,mt2712-infracfg
|
||||
- mediatek,mt7622-infracfg
|
||||
- mediatek,mt7986-infracfg
|
||||
- mediatek,mt8135-infracfg
|
||||
- mediatek,mt8173-infracfg
|
||||
- mediatek,mt8183-infracfg
|
||||
then:
|
||||
required:
|
||||
- '#reset-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
infracfg: clock-controller@10001000 {
|
||||
compatible = "mediatek,mt8173-infracfg", "syscon";
|
||||
reg = <0x10001000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -31,6 +31,7 @@ properties:
|
||||
- mediatek,mt8183-mmsys
|
||||
- mediatek,mt8186-mmsys
|
||||
- mediatek,mt8192-mmsys
|
||||
- mediatek,mt8195-mmsys
|
||||
- mediatek,mt8365-mmsys
|
||||
- const: syscon
|
||||
- items:
|
||||
@ -41,6 +42,30 @@ properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
description:
|
||||
A phandle and PM domain specifier as defined by bindings
|
||||
of the power controller specified by phandle. See
|
||||
Documentation/devicetree/bindings/power/power-domain.yaml for details.
|
||||
|
||||
mboxes:
|
||||
description:
|
||||
Using mailbox to communicate with GCE, it should have this
|
||||
property and list of phandle, mailbox specifiers. See
|
||||
Documentation/devicetree/bindings/mailbox/mtk-gce.txt for details.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
|
||||
mediatek,gce-client-reg:
|
||||
description:
|
||||
The register of client driver can be configured by gce with 4 arguments
|
||||
defined in this property, such as phandle of gce, subsys id,
|
||||
register offset and size.
|
||||
Each subsys id is mapping to a base address of display function blocks
|
||||
register which is defined in the gce header
|
||||
include/dt-bindings/gce/<chip>-gce.h.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
@ -56,9 +81,16 @@ additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/power/mt8173-power.h>
|
||||
#include <dt-bindings/gce/mt8173-gce.h>
|
||||
|
||||
mmsys: syscon@14000000 {
|
||||
compatible = "mediatek,mt8173-mmsys", "syscon";
|
||||
reg = <0x14000000 0x1000>;
|
||||
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
|
||||
<&gce 1 CMDQ_THR_PRIO_HIGHEST>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
|
||||
};
|
||||
|
||||
42
Bindings/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml
Normal file
42
Bindings/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml
Normal file
@ -0,0 +1,42 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: MediaTek PCIE Mirror Controller for MT7622
|
||||
|
||||
maintainers:
|
||||
- Lorenzo Bianconi <lorenzo@kernel.org>
|
||||
- Felix Fietkau <nbd@nbd.name>
|
||||
|
||||
description:
|
||||
The mediatek PCIE mirror provides a configuration interface for PCIE
|
||||
controller on MT7622 soc.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- mediatek,mt7622-pcie-mirror
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
pcie_mirror: pcie-mirror@10000400 {
|
||||
compatible = "mediatek,mt7622-pcie-mirror", "syscon";
|
||||
reg = <0 0x10000400 0 0x10>;
|
||||
};
|
||||
};
|
||||
50
Bindings/arm/mediatek/mediatek,mt7622-wed.yaml
Normal file
50
Bindings/arm/mediatek/mediatek,mt7622-wed.yaml
Normal file
@ -0,0 +1,50 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-wed.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: MediaTek Wireless Ethernet Dispatch Controller for MT7622
|
||||
|
||||
maintainers:
|
||||
- Lorenzo Bianconi <lorenzo@kernel.org>
|
||||
- Felix Fietkau <nbd@nbd.name>
|
||||
|
||||
description:
|
||||
The mediatek wireless ethernet dispatch controller can be configured to
|
||||
intercept and handle access to the WLAN DMA queues and PCIe interrupts
|
||||
and implement hardware flow offloading from ethernet to WLAN.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- mediatek,mt7622-wed
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
wed0: wed@1020a000 {
|
||||
compatible = "mediatek,mt7622-wed","syscon";
|
||||
reg = <0 0x1020a000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
56
Bindings/arm/mediatek/mediatek,mt8186-clock.yaml
Normal file
56
Bindings/arm/mediatek/mediatek,mt8186-clock.yaml
Normal file
@ -0,0 +1,56 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-clock.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: MediaTek Functional Clock Controller for MT8186
|
||||
|
||||
maintainers:
|
||||
- Chun-Jie Chen <chun-jie.chen@mediatek.com>
|
||||
|
||||
description: |
|
||||
The clock architecture in MediaTek like below
|
||||
PLLs -->
|
||||
dividers -->
|
||||
muxes
|
||||
-->
|
||||
clock gate
|
||||
|
||||
The devices provide clock gate control in different IP blocks.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- mediatek,mt8186-imp_iic_wrap
|
||||
- mediatek,mt8186-mfgsys
|
||||
- mediatek,mt8186-wpesys
|
||||
- mediatek,mt8186-imgsys1
|
||||
- mediatek,mt8186-imgsys2
|
||||
- mediatek,mt8186-vdecsys
|
||||
- mediatek,mt8186-vencsys
|
||||
- mediatek,mt8186-camsys
|
||||
- mediatek,mt8186-camsys_rawa
|
||||
- mediatek,mt8186-camsys_rawb
|
||||
- mediatek,mt8186-mdpsys
|
||||
- mediatek,mt8186-ipesys
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
imp_iic_wrap: clock-controller@11017000 {
|
||||
compatible = "mediatek,mt8186-imp_iic_wrap";
|
||||
reg = <0x11017000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
54
Bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml
Normal file
54
Bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml
Normal file
@ -0,0 +1,54 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-sys-clock.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: MediaTek System Clock Controller for MT8186
|
||||
|
||||
maintainers:
|
||||
- Chun-Jie Chen <chun-jie.chen@mediatek.com>
|
||||
|
||||
description: |
|
||||
The clock architecture in MediaTek like below
|
||||
PLLs -->
|
||||
dividers -->
|
||||
muxes
|
||||
-->
|
||||
clock gate
|
||||
|
||||
The apmixedsys provides most of PLLs which generated from SoC 26m.
|
||||
The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
|
||||
The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks.
|
||||
The mcusys provides mux control to select the clock source in AP MCU.
|
||||
The device nodes also provide the system control capacity for configuration.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- mediatek,mt8186-mcusys
|
||||
- mediatek,mt8186-topckgen
|
||||
- mediatek,mt8186-infracfg_ao
|
||||
- mediatek,mt8186-apmixedsys
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
topckgen: syscon@10000000 {
|
||||
compatible = "mediatek,mt8186-topckgen", "syscon";
|
||||
reg = <0x10000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@ -26,6 +26,7 @@ properties:
|
||||
- mediatek,mt8135-pericfg
|
||||
- mediatek,mt8173-pericfg
|
||||
- mediatek,mt8183-pericfg
|
||||
- mediatek,mt8195-pericfg
|
||||
- mediatek,mt8516-pericfg
|
||||
- const: syscon
|
||||
- items:
|
||||
|
||||
@ -23,6 +23,8 @@ properties:
|
||||
enum:
|
||||
- qcom,sc7180-llcc
|
||||
- qcom,sc7280-llcc
|
||||
- qcom,sc8180x-llcc
|
||||
- qcom,sc8280xp-llcc
|
||||
- qcom,sdm845-llcc
|
||||
- qcom,sm6350-llcc
|
||||
- qcom,sm8150-llcc
|
||||
|
||||
@ -31,12 +31,17 @@ Required properties:
|
||||
(base address and length)
|
||||
- clocks: clocks for this module
|
||||
- clockdomains: clockdomains for this module
|
||||
- #clock-cells: From common clock binding
|
||||
- clock-output-names: From common clock binding
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
cm: cm@48004000 {
|
||||
cm: clock@48004000 {
|
||||
compatible = "ti,omap3-cm";
|
||||
reg = <0x48004000 0x4000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "cm";
|
||||
|
||||
cm_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
|
||||
@ -39,8 +39,11 @@ description: |
|
||||
msm8994
|
||||
msm8996
|
||||
sa8155p
|
||||
sa8540p
|
||||
sc7180
|
||||
sc7280
|
||||
sc8180x
|
||||
sc8280xp
|
||||
sdm630
|
||||
sdm632
|
||||
sdm660
|
||||
@ -99,6 +102,7 @@ properties:
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- asus,sparrow
|
||||
- lg,lenok
|
||||
- const: qcom,apq8026
|
||||
|
||||
@ -225,6 +229,18 @@ properties:
|
||||
- google,senor
|
||||
- const: qcom,sc7280
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- lenovo,flex-5g
|
||||
- microsoft,surface-prox
|
||||
- qcom,sc8180x-primus
|
||||
- const: qcom,sc8180x
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,sc8280xp-qrd
|
||||
- const: qcom,sc8280xp
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- fairphone,fp3
|
||||
@ -258,6 +274,11 @@ properties:
|
||||
- qcom,sa8155p-adp
|
||||
- const: qcom,sa8155p
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,sa8295p-adp
|
||||
- const: qcom,sa8540p
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- fairphone,fp4
|
||||
|
||||
@ -327,6 +327,18 @@ properties:
|
||||
- const: renesas,spider-cpu
|
||||
- const: renesas,r8a779f0
|
||||
|
||||
- description: R-Car V4H (R8A779G0)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,white-hawk-cpu # White Hawk CPU board (RTP8A779G0ASKB0FC0SA000)
|
||||
- const: renesas,r8a779g0
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- renesas,white-hawk-breakout # White Hawk BreakOut board (RTP8A779G0ASKB0SB0SA000)
|
||||
- const: renesas,white-hawk-cpu
|
||||
- const: renesas,r8a779g0
|
||||
|
||||
- description: R-Car H3e (R8A779M0)
|
||||
items:
|
||||
- enum:
|
||||
@ -405,6 +417,8 @@ properties:
|
||||
|
||||
- description: RZ/G2UL (R9A07G043)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,smarc-evk # SMARC EVK
|
||||
- enum:
|
||||
- renesas,r9a07g043u11 # RZ/G2UL Type-1
|
||||
- renesas,r9a07g043u12 # RZ/G2UL Type-2
|
||||
@ -430,6 +444,12 @@ properties:
|
||||
- renesas,r9a07g054l2 # Dual Cortex-A55 RZ/V2L
|
||||
- const: renesas,r9a07g054
|
||||
|
||||
- description: RZ/V2M (R9A09G011)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,rzv2mevk2 # RZ/V2M Eval Board v2.0
|
||||
- const: renesas,r9a09g011
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
...
|
||||
|
||||
@ -133,6 +133,11 @@ properties:
|
||||
- firefly,roc-rk3399-pc-plus
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: Firefly Station M2
|
||||
items:
|
||||
- const: firefly,rk3566-roc-pc
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: FriendlyElec NanoPi R2S
|
||||
items:
|
||||
- const: friendlyarm,nanopi-r2s
|
||||
@ -502,9 +507,18 @@ properties:
|
||||
- const: pine64,rockpro64
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: Pine64 Quartz64 Model A
|
||||
- description: Pine64 Quartz64 Model A/B
|
||||
items:
|
||||
- const: pine64,quartz64-a
|
||||
- enum:
|
||||
- pine64,quartz64-a
|
||||
- pine64,quartz64-b
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: Pine64 SoQuartz SoM
|
||||
items:
|
||||
- enum:
|
||||
- pine64,soquartz-cm4io
|
||||
- const: pine64,soquartz
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: Radxa Rock
|
||||
@ -545,6 +559,11 @@ properties:
|
||||
- const: radxa,rock2-square
|
||||
- const: rockchip,rk3288
|
||||
|
||||
- description: Radxa ROCK3 Model A
|
||||
items:
|
||||
- const: radxa,rock3a
|
||||
- const: rockchip,rk3568
|
||||
|
||||
- description: Rikomagic MK808 v1
|
||||
items:
|
||||
- const: rikomagic,mk808
|
||||
|
||||
80
Bindings/arm/sp810.yaml
Normal file
80
Bindings/arm/sp810.yaml
Normal file
@ -0,0 +1,80 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/sp810.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM Versatile Express SP810 System Controller bindings
|
||||
|
||||
maintainers:
|
||||
- Andre Przywara <andre.przywara@arm.com>
|
||||
|
||||
description:
|
||||
The Arm SP810 system controller provides clocks, timers and a watchdog.
|
||||
|
||||
# We need a select here so we don't match all nodes with 'arm,primecell'
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: arm,sp810
|
||||
required:
|
||||
- compatible
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: arm,sp810
|
||||
- const: arm,primecell
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: refclk
|
||||
- const: timclk
|
||||
- const: apb_pclk
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: reference clock
|
||||
- description: timer clock
|
||||
- description: APB register access clock
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 4
|
||||
|
||||
assigned-clocks:
|
||||
maxItems: 4
|
||||
|
||||
assigned-clock-parents:
|
||||
maxItems: 4
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- "#clock-cells"
|
||||
|
||||
examples:
|
||||
- |
|
||||
sysctl@20000 {
|
||||
compatible = "arm,sp810", "arm,primecell";
|
||||
reg = <0x020000 0x1000>;
|
||||
clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
|
||||
clock-names = "refclk", "timclk", "apb_pclk";
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "timerclken0", "timerclken1",
|
||||
"timerclken2", "timerclken3";
|
||||
assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>,
|
||||
<&v2m_sysctl 3>, <&v2m_sysctl 3>;
|
||||
assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>,
|
||||
<&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
|
||||
};
|
||||
@ -14,21 +14,6 @@ properties:
|
||||
const: "/"
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: DH STM32MP1 SoM based Boards
|
||||
items:
|
||||
- enum:
|
||||
- arrow,stm32mp157a-avenger96 # Avenger96
|
||||
- dh,stm32mp153c-dhcom-drc02
|
||||
- dh,stm32mp157c-dhcom-pdk2
|
||||
- dh,stm32mp157c-dhcom-picoitx
|
||||
- enum:
|
||||
- dh,stm32mp153c-dhcom-som
|
||||
- dh,stm32mp157a-dhcor-som
|
||||
- dh,stm32mp157c-dhcom-som
|
||||
- enum:
|
||||
- st,stm32mp153
|
||||
- st,stm32mp157
|
||||
|
||||
- description: emtrion STM32MP1 Argon based Boards
|
||||
items:
|
||||
- const: emtrion,stm32mp157c-emsbc-argon
|
||||
@ -65,6 +50,21 @@ properties:
|
||||
- enum:
|
||||
- st,stm32mp135f-dk
|
||||
- const: st,stm32mp135
|
||||
|
||||
- description: ST STM32MP151 based Boards
|
||||
items:
|
||||
- enum:
|
||||
- prt,prtt1a # Protonic PRTT1A
|
||||
- prt,prtt1c # Protonic PRTT1C
|
||||
- prt,prtt1s # Protonic PRTT1S
|
||||
- const: st,stm32mp151
|
||||
|
||||
- description: DH STM32MP153 SoM based Boards
|
||||
items:
|
||||
- const: dh,stm32mp153c-dhcom-drc02
|
||||
- const: dh,stm32mp153c-dhcom-som
|
||||
- const: st,stm32mp153
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- shiratech,stm32mp157a-iot-box # IoT Box
|
||||
@ -72,12 +72,44 @@ properties:
|
||||
- st,stm32mp157c-ed1
|
||||
- st,stm32mp157a-dk1
|
||||
- st,stm32mp157c-dk2
|
||||
- const: st,stm32mp157
|
||||
|
||||
- items:
|
||||
- const: st,stm32mp157a-dk1-scmi
|
||||
- const: st,stm32mp157a-dk1
|
||||
- const: st,stm32mp157
|
||||
- items:
|
||||
- const: st,stm32mp157c-dk2-scmi
|
||||
- const: st,stm32mp157c-dk2
|
||||
- const: st,stm32mp157
|
||||
- items:
|
||||
- const: st,stm32mp157c-ed1-scmi
|
||||
- const: st,stm32mp157c-ed1
|
||||
- const: st,stm32mp157
|
||||
- items:
|
||||
- const: st,stm32mp157c-ev1
|
||||
- const: st,stm32mp157c-ed1
|
||||
- const: st,stm32mp157
|
||||
- items:
|
||||
- const: st,stm32mp157c-ev1-scmi
|
||||
- const: st,stm32mp157c-ev1
|
||||
- const: st,stm32mp157c-ed1
|
||||
- const: st,stm32mp157
|
||||
|
||||
- description: DH STM32MP1 SoM based Boards
|
||||
items:
|
||||
- enum:
|
||||
- arrow,stm32mp157a-avenger96 # Avenger96
|
||||
- const: dh,stm32mp157a-dhcor-som
|
||||
- const: st,stm32mp157
|
||||
|
||||
- description: DH STM32MP1 SoM based Boards
|
||||
items:
|
||||
- enum:
|
||||
- dh,stm32mp157c-dhcom-pdk2
|
||||
- dh,stm32mp157c-dhcom-picoitx
|
||||
- const: dh,stm32mp157c-dhcom-som
|
||||
- const: st,stm32mp157
|
||||
|
||||
- description: Engicam i.Core STM32MP1 SoM based Boards
|
||||
items:
|
||||
@ -103,6 +135,7 @@ properties:
|
||||
- const: oct,stm32mp15xx-osd32
|
||||
- enum:
|
||||
- st,stm32mp157
|
||||
|
||||
- description: Odyssey STM32MP1 SoM based Boards
|
||||
items:
|
||||
- enum:
|
||||
|
||||
@ -391,6 +391,11 @@ properties:
|
||||
- const: libretech,all-h5-cc-h5
|
||||
- const: allwinner,sun50i-h5
|
||||
|
||||
- description: Lichee Pi Nano
|
||||
items:
|
||||
- const: licheepi,licheepi-nano
|
||||
- const: allwinner,suniv-f1c100s
|
||||
|
||||
- description: Lichee Pi One
|
||||
items:
|
||||
- const: licheepi,licheepi-one
|
||||
|
||||
@ -18,10 +18,6 @@ stable binding/ABI.
|
||||
|
||||
---------------------------------------------------------------
|
||||
|
||||
Boards with the Synaptics AS370 SoC shall have the following properties:
|
||||
Required root node property:
|
||||
compatible: "syna,as370"
|
||||
|
||||
Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
|
||||
shall have the following properties:
|
||||
|
||||
|
||||
52
Bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml
Normal file
52
Bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml
Normal file
@ -0,0 +1,52 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra-ccplex-cluster.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: NVIDIA Tegra CPU COMPLEX CLUSTER area device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Sumit Gupta <sumitg@nvidia.com>
|
||||
- Mikko Perttunen <mperttunen@nvidia.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
|
||||
description: |+
|
||||
The Tegra CPU COMPLEX CLUSTER area contains memory-mapped
|
||||
registers that initiate CPU frequency/voltage transitions.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "ccplex@([0-9a-f]+)$"
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra186-ccplex-cluster
|
||||
- nvidia,tegra234-ccplex-cluster
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
nvidia,bpmp:
|
||||
$ref: '/schemas/types.yaml#/definitions/phandle'
|
||||
description: |
|
||||
Specifies the BPMP node that needs to be queried to get
|
||||
operating point data for all CPUs.
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- nvidia,bpmp
|
||||
- status
|
||||
|
||||
examples:
|
||||
- |
|
||||
ccplex@e000000 {
|
||||
compatible = "nvidia,tegra234-ccplex-cluster";
|
||||
reg = <0x0e000000 0x5ffff>;
|
||||
nvidia,bpmp = <&bpmp>;
|
||||
status = "okay";
|
||||
};
|
||||
@ -40,6 +40,11 @@ properties:
|
||||
- const: samsung,codina
|
||||
- const: st-ericsson,u8500
|
||||
|
||||
- description: Samsung Galaxy Exhibit (SGH-T599)
|
||||
items:
|
||||
- const: samsung,codina-tmo
|
||||
- const: st-ericsson,u8500
|
||||
|
||||
- description: Samsung Galaxy Beam (GT-I8530)
|
||||
items:
|
||||
- const: samsung,gavini
|
||||
|
||||
285
Bindings/arm/vexpress-config.yaml
Normal file
285
Bindings/arm/vexpress-config.yaml
Normal file
@ -0,0 +1,285 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/vexpress-config.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM Versatile Express configuration bus bindings
|
||||
|
||||
maintainers:
|
||||
- Andre Przywara <andre.przywara@arm.com>
|
||||
|
||||
description:
|
||||
This is a system control register block, acting as a bridge to the
|
||||
platform's configuration bus via "system control" interface, addressing
|
||||
devices with site number, position in the board stack, config controller,
|
||||
function and device numbers - see motherboard's TRM for more details.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: arm,vexpress,config-bus
|
||||
|
||||
arm,vexpress,config-bridge:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to the sysreg node.
|
||||
|
||||
muxfpga:
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: arm,vexpress-muxfpga
|
||||
|
||||
arm,vexpress-sysreg,func:
|
||||
description: FPGA specifier
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
items:
|
||||
- const: 7
|
||||
- description: device number
|
||||
|
||||
additionalProperties: false
|
||||
required:
|
||||
- compatible
|
||||
- arm,vexpress-sysreg,func
|
||||
|
||||
shutdown:
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: arm,vexpress-shutdown
|
||||
|
||||
arm,vexpress-sysreg,func:
|
||||
description: shutdown identifier
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
items:
|
||||
- const: 8
|
||||
- description: device number
|
||||
|
||||
additionalProperties: false
|
||||
required:
|
||||
- compatible
|
||||
- arm,vexpress-sysreg,func
|
||||
|
||||
reboot:
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: arm,vexpress-reboot
|
||||
|
||||
arm,vexpress-sysreg,func:
|
||||
description: reboot identifier
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
items:
|
||||
- const: 9
|
||||
- description: device number
|
||||
|
||||
additionalProperties: false
|
||||
required:
|
||||
- compatible
|
||||
- arm,vexpress-sysreg,func
|
||||
|
||||
dvimode:
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: arm,vexpress-dvimode
|
||||
|
||||
arm,vexpress-sysreg,func:
|
||||
description: DVI mode identifier
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
items:
|
||||
- const: 11
|
||||
- description: device number
|
||||
|
||||
additionalProperties: false
|
||||
required:
|
||||
- compatible
|
||||
- arm,vexpress-sysreg,func
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- arm,vexpress,config-bridge
|
||||
|
||||
patternProperties:
|
||||
'clk[0-9]*$':
|
||||
type: object
|
||||
description:
|
||||
clocks
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: arm,vexpress-osc
|
||||
|
||||
arm,vexpress-sysreg,func:
|
||||
description: clock specifier
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
items:
|
||||
- const: 1
|
||||
- description: clock number
|
||||
|
||||
freq-range:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
items:
|
||||
- description: minimal clock frequency
|
||||
- description: maximum clock frequency
|
||||
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
additionalProperties: false
|
||||
required:
|
||||
- compatible
|
||||
- arm,vexpress-sysreg,func
|
||||
- "#clock-cells"
|
||||
|
||||
"^volt-.+$":
|
||||
$ref: /schemas/regulator/regulator.yaml#
|
||||
properties:
|
||||
compatible:
|
||||
const: arm,vexpress-volt
|
||||
|
||||
arm,vexpress-sysreg,func:
|
||||
description: regulator specifier
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
items:
|
||||
- const: 2
|
||||
- description: device number
|
||||
|
||||
label:
|
||||
maxItems: 1
|
||||
|
||||
unevaluatedProperties: false
|
||||
required:
|
||||
- compatible
|
||||
- arm,vexpress-sysreg,func
|
||||
|
||||
"^amp-.+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: arm,vexpress-amp
|
||||
|
||||
arm,vexpress-sysreg,func:
|
||||
description: current sensor identifier
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
items:
|
||||
- const: 3
|
||||
- description: device number
|
||||
|
||||
label:
|
||||
maxItems: 1
|
||||
|
||||
additionalProperties: false
|
||||
required:
|
||||
- compatible
|
||||
- arm,vexpress-sysreg,func
|
||||
|
||||
"^temp-.+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: arm,vexpress-temp
|
||||
|
||||
arm,vexpress-sysreg,func:
|
||||
description: temperature sensor identifier
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
items:
|
||||
- const: 4
|
||||
- description: device number
|
||||
|
||||
label:
|
||||
maxItems: 1
|
||||
|
||||
additionalProperties: false
|
||||
required:
|
||||
- compatible
|
||||
- arm,vexpress-sysreg,func
|
||||
|
||||
"^reset[0-9]*$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: arm,vexpress-reset
|
||||
|
||||
arm,vexpress-sysreg,func:
|
||||
description: reset specifier
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
items:
|
||||
- const: 5
|
||||
- description: reset device number
|
||||
|
||||
additionalProperties: false
|
||||
required:
|
||||
- compatible
|
||||
- arm,vexpress-sysreg,func
|
||||
|
||||
"^power-.+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: arm,vexpress-power
|
||||
|
||||
arm,vexpress-sysreg,func:
|
||||
description: power sensor identifier
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
items:
|
||||
- const: 12
|
||||
- description: device number
|
||||
|
||||
label:
|
||||
maxItems: 1
|
||||
|
||||
additionalProperties: false
|
||||
required:
|
||||
- compatible
|
||||
- arm,vexpress-sysreg,func
|
||||
|
||||
"^energy(-.+)?$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: arm,vexpress-energy
|
||||
|
||||
arm,vexpress-sysreg,func:
|
||||
description: energy sensor identifier
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
oneOf:
|
||||
- items:
|
||||
- const: 13
|
||||
- description: device number
|
||||
- items:
|
||||
- const: 13
|
||||
- description: device number
|
||||
- const: 13
|
||||
- description: second device number
|
||||
|
||||
label:
|
||||
maxItems: 1
|
||||
|
||||
additionalProperties: false
|
||||
required:
|
||||
- compatible
|
||||
- arm,vexpress-sysreg,func
|
||||
|
||||
examples:
|
||||
- |
|
||||
mcc {
|
||||
compatible = "arm,vexpress,config-bus";
|
||||
arm,vexpress,config-bridge = <&v2m_sysreg>;
|
||||
|
||||
clk0 {
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 0>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
energy {
|
||||
compatible = "arm,vexpress-energy";
|
||||
arm,vexpress-sysreg,func = <13 0>, <13 1>;
|
||||
};
|
||||
};
|
||||
90
Bindings/arm/vexpress-sysreg.yaml
Normal file
90
Bindings/arm/vexpress-sysreg.yaml
Normal file
@ -0,0 +1,90 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/vexpress-sysreg.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM Versatile Express system registers bindings
|
||||
|
||||
maintainers:
|
||||
- Andre Przywara <andre.przywara@arm.com>
|
||||
|
||||
description:
|
||||
This is a system control registers block, providing multiple low level
|
||||
platform functions like board detection and identification, software
|
||||
interrupt generation, MMC and NOR Flash control, etc.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: arm,vexpress-sysreg
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
"#size-cells":
|
||||
const: 1
|
||||
|
||||
ranges: true
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
patternProperties:
|
||||
'^gpio@[0-9a-f]+$':
|
||||
type: object
|
||||
additionalProperties: false
|
||||
description:
|
||||
GPIO children
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- arm,vexpress-sysreg,sys_led
|
||||
- arm,vexpress-sysreg,sys_mci
|
||||
- arm,vexpress-sysreg,sys_flash
|
||||
|
||||
gpio-controller: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
description: |
|
||||
The first cell is the function number:
|
||||
for sys_led : 0..7 = LED 0..7
|
||||
for sys_mci : 0 = MMC CARDIN, 1 = MMC WPROT
|
||||
for sys_flash : 0 = NOR FLASH WPn
|
||||
The second cell can take standard GPIO flags.
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- gpio-controller
|
||||
- "#gpio-cells"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
|
||||
examples:
|
||||
- |
|
||||
sysreg@0 {
|
||||
compatible = "arm,vexpress-sysreg";
|
||||
reg = <0x00000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x1000>;
|
||||
|
||||
v2m_led_gpios: gpio@8 {
|
||||
compatible = "arm,vexpress-sysreg,sys_led";
|
||||
reg = <0x008 4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@ -26,6 +26,7 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- renesas,sata-r8a774b1 # RZ/G2N
|
||||
- renesas,sata-r8a774e1 # RZ/G2H
|
||||
- renesas,sata-r8a7795 # R-Car H3
|
||||
- renesas,sata-r8a77965 # R-Car M3-N
|
||||
- const: renesas,rcar-gen3-sata # generic R-Car Gen3 or RZ/G2
|
||||
|
||||
147
Bindings/bus/qcom,ssc-block-bus.yaml
Normal file
147
Bindings/bus/qcom,ssc-block-bus.yaml
Normal file
@ -0,0 +1,147 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/bus/qcom,ssc-block-bus.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: The AHB Bus Providing a Global View of the SSC Block on (some) qcom SoCs
|
||||
|
||||
maintainers:
|
||||
- Michael Srba <Michael.Srba@seznam.cz>
|
||||
|
||||
description: |
|
||||
This binding describes the dependencies (clocks, resets, power domains) which
|
||||
need to be turned on in a sequence before communication over the AHB bus
|
||||
becomes possible.
|
||||
|
||||
Additionally, the reg property is used to pass to the driver the location of
|
||||
two sadly undocumented registers which need to be poked as part of the sequence.
|
||||
|
||||
The SSC (Snapdragon Sensor Core) block contains a gpio controller, i2c/spi/uart
|
||||
controllers, a hexagon core, and a clock controller which provides clocks for
|
||||
the above.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,msm8998-ssc-block-bus
|
||||
- const: qcom,ssc-block-bus
|
||||
|
||||
reg:
|
||||
description: |
|
||||
Shall contain the addresses of the SSCAON_CONFIG0 and SSCAON_CONFIG1
|
||||
registers
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: mpm_sscaon_config0
|
||||
- const: mpm_sscaon_config1
|
||||
|
||||
'#address-cells':
|
||||
enum: [ 1, 2 ]
|
||||
|
||||
'#size-cells':
|
||||
enum: [ 1, 2 ]
|
||||
|
||||
ranges: true
|
||||
|
||||
clocks:
|
||||
minItems: 6
|
||||
maxItems: 6
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xo
|
||||
- const: aggre2
|
||||
- const: gcc_im_sleep
|
||||
- const: aggre2_north
|
||||
- const: ssc_xo
|
||||
- const: ssc_ahbs
|
||||
|
||||
power-domains:
|
||||
description: Power domain phandles for the ssc_cx and ssc_mx power domains
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
power-domain-names:
|
||||
items:
|
||||
- const: ssc_cx
|
||||
- const: ssc_mx
|
||||
|
||||
resets:
|
||||
description: |
|
||||
Reset phandles for the ssc_reset and ssc_bcr resets (note: ssc_bcr is the
|
||||
branch control register associated with the ssc_xo and ssc_ahbs clocks)
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: ssc_reset
|
||||
- const: ssc_bcr
|
||||
|
||||
qcom,halt-regs:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
description: describes how to locate the ssc AXI halt register
|
||||
items:
|
||||
- items:
|
||||
- description: Phandle reference to a syscon representing TCSR
|
||||
- description: offset for the ssc AXI halt register
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- '#address-cells'
|
||||
- '#size-cells'
|
||||
- ranges
|
||||
- clocks
|
||||
- clock-names
|
||||
- power-domains
|
||||
- power-domain-names
|
||||
- resets
|
||||
- reset-names
|
||||
- qcom,halt-regs
|
||||
|
||||
additionalProperties:
|
||||
type: object
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-msm8998.h>
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
// devices under this node are physically located in the SSC block, connected to an ssc-internal bus;
|
||||
ssc_ahb_slave: bus@10ac008 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
compatible = "qcom,msm8998-ssc-block-bus", "qcom,ssc-block-bus";
|
||||
reg = <0x10ac008 0x4>, <0x10ac010 0x4>;
|
||||
reg-names = "mpm_sscaon_config0", "mpm_sscaon_config1";
|
||||
|
||||
clocks = <&xo>,
|
||||
<&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
|
||||
<&gcc GCC_IM_SLEEP>,
|
||||
<&gcc AGGRE2_SNOC_NORTH_AXI>,
|
||||
<&gcc SSC_XO>,
|
||||
<&gcc SSC_CNOC_AHBS_CLK>;
|
||||
clock-names = "xo", "aggre2", "gcc_im_sleep", "aggre2_north", "ssc_xo", "ssc_ahbs";
|
||||
|
||||
resets = <&gcc GCC_SSC_RESET>, <&gcc GCC_SSC_BCR>;
|
||||
reset-names = "ssc_reset", "ssc_bcr";
|
||||
|
||||
power-domains = <&rpmpd MSM8998_SSCCX>, <&rpmpd MSM8998_SSCMX>;
|
||||
power-domain-names = "ssc_cx", "ssc_mx";
|
||||
|
||||
qcom,halt-regs = <&tcsr_mutex_regs 0x26000>;
|
||||
};
|
||||
};
|
||||
58
Bindings/clock/airoha,en7523-scu.yaml
Normal file
58
Bindings/clock/airoha,en7523-scu.yaml
Normal file
@ -0,0 +1,58 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/airoha,en7523-scu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: EN7523 Clock Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Felix Fietkau <nbd@nbd.name>
|
||||
- John Crispin <nbd@nbd.name>
|
||||
|
||||
description: |
|
||||
This node defines the System Control Unit of the EN7523 SoC,
|
||||
a collection of registers configuring many different aspects of the SoC.
|
||||
|
||||
The clock driver uses it to read and configure settings of the
|
||||
PLL controller, which provides clocks for the CPU, the bus and
|
||||
other SoC internal peripherals.
|
||||
|
||||
Each clock is assigned an identifier and client nodes use this identifier
|
||||
to specify which clock they consume.
|
||||
|
||||
All these identifiers can be found in:
|
||||
[1]: <include/dt-bindings/clock/en7523-clk.h>.
|
||||
|
||||
The clocks are provided inside a system controller node.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: airoha,en7523-scu
|
||||
|
||||
reg:
|
||||
maxItems: 2
|
||||
|
||||
"#clock-cells":
|
||||
description:
|
||||
The first cell indicates the clock number, see [1] for available
|
||||
clocks.
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/en7523-clk.h>
|
||||
scu: system-controller@1fa20000 {
|
||||
compatible = "airoha,en7523-scu";
|
||||
reg = <0x1fa20000 0x400>,
|
||||
<0x1fb00000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@ -1,186 +1,2 @@
|
||||
This binding is a work-in-progress, and are based on some experimental
|
||||
work by benh[1].
|
||||
|
||||
Sources of clock signal can be represented by any node in the device
|
||||
tree. Those nodes are designated as clock providers. Clock consumer
|
||||
nodes use a phandle and clock specifier pair to connect clock provider
|
||||
outputs to clock inputs. Similar to the gpio specifiers, a clock
|
||||
specifier is an array of zero, one or more cells identifying the clock
|
||||
output on a device. The length of a clock specifier is defined by the
|
||||
value of a #clock-cells property in the clock provider node.
|
||||
|
||||
[1] https://patchwork.ozlabs.org/patch/31551/
|
||||
|
||||
==Clock providers==
|
||||
|
||||
Required properties:
|
||||
#clock-cells: Number of cells in a clock specifier; Typically 0 for nodes
|
||||
with a single clock output and 1 for nodes with multiple
|
||||
clock outputs.
|
||||
|
||||
Optional properties:
|
||||
clock-output-names: Recommended to be a list of strings of clock output signal
|
||||
names indexed by the first cell in the clock specifier.
|
||||
However, the meaning of clock-output-names is domain
|
||||
specific to the clock provider, and is only provided to
|
||||
encourage using the same meaning for the majority of clock
|
||||
providers. This format may not work for clock providers
|
||||
using a complex clock specifier format. In those cases it
|
||||
is recommended to omit this property and create a binding
|
||||
specific names property.
|
||||
|
||||
Clock consumer nodes must never directly reference
|
||||
the provider's clock-output-names property.
|
||||
|
||||
For example:
|
||||
|
||||
oscillator {
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "ckil", "ckih";
|
||||
};
|
||||
|
||||
- this node defines a device with two clock outputs, the first named
|
||||
"ckil" and the second named "ckih". Consumer nodes always reference
|
||||
clocks by index. The names should reflect the clock output signal
|
||||
names for the device.
|
||||
|
||||
clock-indices: If the identifying number for the clocks in the node
|
||||
is not linear from zero, then this allows the mapping of
|
||||
identifiers into the clock-output-names array.
|
||||
|
||||
For example, if we have two clocks <&oscillator 1> and <&oscillator 3>:
|
||||
|
||||
oscillator {
|
||||
compatible = "myclocktype";
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <1>, <3>;
|
||||
clock-output-names = "clka", "clkb";
|
||||
}
|
||||
|
||||
This ensures we do not have any empty strings in clock-output-names
|
||||
|
||||
|
||||
==Clock consumers==
|
||||
|
||||
Required properties:
|
||||
clocks: List of phandle and clock specifier pairs, one pair
|
||||
for each clock input to the device. Note: if the
|
||||
clock provider specifies '0' for #clock-cells, then
|
||||
only the phandle portion of the pair will appear.
|
||||
|
||||
Optional properties:
|
||||
clock-names: List of clock input name strings sorted in the same
|
||||
order as the clocks property. Consumers drivers
|
||||
will use clock-names to match clock input names
|
||||
with clocks specifiers.
|
||||
clock-ranges: Empty property indicating that child nodes can inherit named
|
||||
clocks from this node. Useful for bus nodes to provide a
|
||||
clock to their children.
|
||||
|
||||
For example:
|
||||
|
||||
device {
|
||||
clocks = <&osc 1>, <&ref 0>;
|
||||
clock-names = "baud", "register";
|
||||
};
|
||||
|
||||
|
||||
This represents a device with two clock inputs, named "baud" and "register".
|
||||
The baud clock is connected to output 1 of the &osc device, and the register
|
||||
clock is connected to output 0 of the &ref.
|
||||
|
||||
==Example==
|
||||
|
||||
/* external oscillator */
|
||||
osc: oscillator {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32678>;
|
||||
clock-output-names = "osc";
|
||||
};
|
||||
|
||||
/* phase-locked-loop device, generates a higher frequency clock
|
||||
* from the external oscillator reference */
|
||||
pll: pll@4c000 {
|
||||
compatible = "vendor,some-pll-interface"
|
||||
#clock-cells = <1>;
|
||||
clocks = <&osc 0>;
|
||||
clock-names = "ref";
|
||||
reg = <0x4c000 0x1000>;
|
||||
clock-output-names = "pll", "pll-switched";
|
||||
};
|
||||
|
||||
/* UART, using the low frequency oscillator for the baud clock,
|
||||
* and the high frequency switched PLL output for register
|
||||
* clocking */
|
||||
uart@a000 {
|
||||
compatible = "fsl,imx-uart";
|
||||
reg = <0xa000 0x1000>;
|
||||
interrupts = <33>;
|
||||
clocks = <&osc 0>, <&pll 1>;
|
||||
clock-names = "baud", "register";
|
||||
};
|
||||
|
||||
This DT fragment defines three devices: an external oscillator to provide a
|
||||
low-frequency reference clock, a PLL device to generate a higher frequency
|
||||
clock signal, and a UART.
|
||||
|
||||
* The oscillator is fixed-frequency, and provides one clock output, named "osc".
|
||||
* The PLL is both a clock provider and a clock consumer. It uses the clock
|
||||
signal generated by the external oscillator, and provides two output signals
|
||||
("pll" and "pll-switched").
|
||||
* The UART has its baud clock connected the external oscillator and its
|
||||
register clock connected to the PLL clock (the "pll-switched" signal)
|
||||
|
||||
==Assigned clock parents and rates==
|
||||
|
||||
Some platforms may require initial configuration of default parent clocks
|
||||
and clock frequencies. Such a configuration can be specified in a device tree
|
||||
node through assigned-clocks, assigned-clock-parents and assigned-clock-rates
|
||||
properties. The assigned-clock-parents property should contain a list of parent
|
||||
clocks in the form of a phandle and clock specifier pair and the
|
||||
assigned-clock-rates property should contain a list of frequencies in Hz. Both
|
||||
these properties should correspond to the clocks listed in the assigned-clocks
|
||||
property.
|
||||
|
||||
To skip setting parent or rate of a clock its corresponding entry should be
|
||||
set to 0, or can be omitted if it is not followed by any non-zero entry.
|
||||
|
||||
uart@a000 {
|
||||
compatible = "fsl,imx-uart";
|
||||
reg = <0xa000 0x1000>;
|
||||
...
|
||||
clocks = <&osc 0>, <&pll 1>;
|
||||
clock-names = "baud", "register";
|
||||
|
||||
assigned-clocks = <&clkcon 0>, <&pll 2>;
|
||||
assigned-clock-parents = <&pll 2>;
|
||||
assigned-clock-rates = <0>, <460800>;
|
||||
};
|
||||
|
||||
In this example the <&pll 2> clock is set as parent of clock <&clkcon 0> and
|
||||
the <&pll 2> clock is assigned a frequency value of 460800 Hz.
|
||||
|
||||
Configuring a clock's parent and rate through the device node that consumes
|
||||
the clock can be done only for clocks that have a single user. Specifying
|
||||
conflicting parent or rate configuration in multiple consumer nodes for
|
||||
a shared clock is forbidden.
|
||||
|
||||
Configuration of common clocks, which affect multiple consumer devices can
|
||||
be similarly specified in the clock provider node.
|
||||
|
||||
==Protected clocks==
|
||||
|
||||
Some platforms or firmwares may not fully expose all the clocks to the OS, such
|
||||
as in situations where those clks are used by drivers running in ARM secure
|
||||
execution levels. Such a configuration can be specified in device tree with the
|
||||
protected-clocks property in the form of a clock specifier list. This property should
|
||||
only be specified in the node that is providing the clocks being protected:
|
||||
|
||||
clock-controller@a000f000 {
|
||||
compatible = "vendor,clk95;
|
||||
reg = <0xa000f000 0x1000>
|
||||
#clocks-cells = <1>;
|
||||
...
|
||||
protected-clocks = <UART3_CLK>, <SPI5_CLK>;
|
||||
};
|
||||
This file has moved to the clock binding schema:
|
||||
https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/clock/clock.yaml
|
||||
|
||||
@ -45,7 +45,7 @@ description: |
|
||||
The case where SH and SP are both 1 is likely not very interesting.
|
||||
|
||||
maintainers:
|
||||
- Luca Ceresoli <luca@lucaceresoli.net>
|
||||
- Luca Ceresoli <luca.ceresoli@bootlin.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
61
Bindings/clock/mediatek,apmixedsys.yaml
Normal file
61
Bindings/clock/mediatek,apmixedsys.yaml
Normal file
@ -0,0 +1,61 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/clock/mediatek,apmixedsys.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: MediaTek AP Mixedsys Controller
|
||||
|
||||
maintainers:
|
||||
- Michael Turquette <mturquette@baylibre.com>
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
|
||||
description:
|
||||
The Mediatek apmixedsys controller provides PLLs to the system.
|
||||
The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- mediatek,mt6797-apmixedsys
|
||||
- mediatek,mt7622-apmixedsys
|
||||
- mediatek,mt7986-apmixedsys
|
||||
- mediatek,mt8135-apmixedsys
|
||||
- mediatek,mt8173-apmixedsys
|
||||
- mediatek,mt8516-apmixedsys
|
||||
- items:
|
||||
- const: mediatek,mt7623-apmixedsys
|
||||
- const: mediatek,mt2701-apmixedsys
|
||||
- const: syscon
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt2701-apmixedsys
|
||||
- mediatek,mt2712-apmixedsys
|
||||
- mediatek,mt6765-apmixedsys
|
||||
- mediatek,mt6779-apmixedsys
|
||||
- mediatek,mt7629-apmixedsys
|
||||
- mediatek,mt8167-apmixedsys
|
||||
- mediatek,mt8183-apmixedsys
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
apmixedsys: clock-controller@10209000 {
|
||||
compatible = "mediatek,mt8173-apmixedsys";
|
||||
reg = <0x10209000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
61
Bindings/clock/mediatek,topckgen.yaml
Normal file
61
Bindings/clock/mediatek,topckgen.yaml
Normal file
@ -0,0 +1,61 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/clock/mediatek,topckgen.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: MediaTek Top Clock Generator Controller
|
||||
|
||||
maintainers:
|
||||
- Michael Turquette <mturquette@baylibre.com>
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
|
||||
description:
|
||||
The Mediatek topckgen controller provides various clocks to the system.
|
||||
The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- mediatek,mt6797-topckgen
|
||||
- mediatek,mt7622-topckgen
|
||||
- mediatek,mt8135-topckgen
|
||||
- mediatek,mt8173-topckgen
|
||||
- mediatek,mt8516-topckgen
|
||||
- items:
|
||||
- const: mediatek,mt7623-topckgen
|
||||
- const: mediatek,mt2701-topckgen
|
||||
- const: syscon
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt2701-topckgen
|
||||
- mediatek,mt2712-topckgen
|
||||
- mediatek,mt6765-topckgen
|
||||
- mediatek,mt6779-topckgen
|
||||
- mediatek,mt7629-topckgen
|
||||
- mediatek,mt7986-topckgen
|
||||
- mediatek,mt8167-topckgen
|
||||
- mediatek,mt8183-topckgen
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
topckgen: clock-controller@10000000 {
|
||||
compatible = "mediatek,mt8173-topckgen";
|
||||
reg = <0x10000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@ -20,12 +20,10 @@ description: |
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-msm8960.h
|
||||
- dt-bindings/reset/qcom,gcc-msm8960.h
|
||||
- dt-bindings/clock/qcom,gcc-apq8084.h
|
||||
- dt-bindings/reset/qcom,gcc-apq8084.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-apq8084
|
||||
const: qcom,gcc-apq8064
|
||||
|
||||
nvmem-cells:
|
||||
minItems: 1
|
||||
|
||||
42
Bindings/clock/qcom,gcc-apq8084.yaml
Normal file
42
Bindings/clock/qcom,gcc-apq8084.yaml
Normal file
@ -0,0 +1,42 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-apq8084.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for APQ8084
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <quic_tdas@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on APQ8084.
|
||||
|
||||
See also::
|
||||
- dt-bindings/clock/qcom,gcc-apq8084.h
|
||||
- dt-bindings/reset/qcom,gcc-apq8084.h
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-apq8084
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@fc400000 {
|
||||
compatible = "qcom,gcc-apq8084";
|
||||
reg = <0xfc400000 0x4000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
128
Bindings/clock/qcom,gcc-sc8280xp.yaml
Normal file
128
Bindings/clock/qcom,gcc-sc8280xp.yaml
Normal file
@ -0,0 +1,128 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sc8280xp.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for SC8280xp
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on SC8280xp.
|
||||
|
||||
See also:
|
||||
- include/dt-bindings/clock/qcom,gcc-sc8280xp.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-sc8280xp
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: XO reference clock
|
||||
- description: Sleep clock
|
||||
- description: UFS memory first RX symbol clock
|
||||
- description: UFS memory second RX symbol clock
|
||||
- description: UFS memory first TX symbol clock
|
||||
- description: UFS card first RX symbol clock
|
||||
- description: UFS card second RX symbol clock
|
||||
- description: UFS card first TX symbol clock
|
||||
- description: Primary USB SuperSpeed pipe clock
|
||||
- description: USB4 PHY pipegmux clock source
|
||||
- description: USB4 PHY DP gmux clock source
|
||||
- description: USB4 PHY sys piegmux clock source
|
||||
- description: USB4 PHY PCIe pipe clock
|
||||
- description: USB4 PHY router max pipe clock
|
||||
- description: Primary USB4 RX0 clock
|
||||
- description: Primary USB4 RX1 clock
|
||||
- description: Secondary USB SuperSpeed pipe clock
|
||||
- description: Second USB4 PHY pipegmux clock source
|
||||
- description: Second USB4 PHY DP gmux clock source
|
||||
- description: Second USB4 PHY sys pipegmux clock source
|
||||
- description: Second USB4 PHY PCIe pipe clock
|
||||
- description: Second USB4 PHY router max pipe clock
|
||||
- description: Secondary USB4 RX0 clock
|
||||
- description: Secondary USB4 RX1 clock
|
||||
- description: Multiport USB first SupserSpeed pipe clock
|
||||
- description: Multiport USB second SuperSpeed pipe clock
|
||||
- description: PCIe 2a pipe clock
|
||||
- description: PCIe 2b pipe clock
|
||||
- description: PCIe 3a pipe clock
|
||||
- description: PCIe 3b pipe clock
|
||||
- description: PCIe 4 pipe clock
|
||||
- description: First EMAC controller reference clock
|
||||
- description: Second EMAC controller reference clock
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
protected-clocks:
|
||||
maxItems: 389
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sc8280xp";
|
||||
reg = <0x00100000 0x1f0000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&sleep_clk>,
|
||||
<&ufs_phy_rx_symbol_0_clk>,
|
||||
<&ufs_phy_rx_symbol_1_clk>,
|
||||
<&ufs_phy_tx_symbol_0_clk>,
|
||||
<&ufs_card_rx_symbol_0_clk>,
|
||||
<&ufs_card_rx_symbol_1_clk>,
|
||||
<&ufs_card_tx_symbol_0_clk>,
|
||||
<&usb_0_ssphy>,
|
||||
<&gcc_usb4_phy_pipegmux_clk_src>,
|
||||
<&gcc_usb4_phy_dp_gmux_clk_src>,
|
||||
<&gcc_usb4_phy_sys_pipegmux_clk_src>,
|
||||
<&usb4_phy_gcc_usb4_pcie_pipe_clk>,
|
||||
<&usb4_phy_gcc_usb4rtr_max_pipe_clk>,
|
||||
<&qusb4phy_gcc_usb4_rx0_clk>,
|
||||
<&qusb4phy_gcc_usb4_rx1_clk>,
|
||||
<&usb_1_ssphy>,
|
||||
<&gcc_usb4_1_phy_pipegmux_clk_src>,
|
||||
<&gcc_usb4_1_phy_dp_gmux_clk_src>,
|
||||
<&gcc_usb4_1_phy_sys_pipegmux_clk_src>,
|
||||
<&usb4_1_phy_gcc_usb4_pcie_pipe_clk>,
|
||||
<&usb4_1_phy_gcc_usb4rtr_max_pipe_clk>,
|
||||
<&qusb4phy_1_gcc_usb4_rx0_clk>,
|
||||
<&qusb4phy_1_gcc_usb4_rx1_clk>,
|
||||
<&usb_2_ssphy>,
|
||||
<&usb_3_ssphy>,
|
||||
<&pcie2a_lane>,
|
||||
<&pcie2b_lane>,
|
||||
<&pcie3a_lane>,
|
||||
<&pcie3b_lane>,
|
||||
<&pcie4_lane>,
|
||||
<&rxc0_ref_clk>,
|
||||
<&rxc1_ref_clk>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Qualcomm Multimedia Clock & Reset Controller Binding
|
||||
|
||||
maintainers:
|
||||
- Jeffrey Hugo <jhugo@codeaurora.org>
|
||||
- Jeffrey Hugo <quic_jhugo@quicinc.com>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
|
||||
75
Bindings/clock/qcom,rpmcc.yaml
Normal file
75
Bindings/clock/qcom,rpmcc.yaml
Normal file
@ -0,0 +1,75 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,rpmcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm RPM Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||||
|
||||
description: |
|
||||
The clock enumerators are defined in <dt-bindings/clock/qcom,rpmcc.h> and
|
||||
come in pairs:: FOO_CLK followed by FOO_A_CLK. The latter clock is
|
||||
an "active" clock, which means that the consumer only care that the clock is
|
||||
available when the apps CPU subsystem is active, i.e. not suspended or in
|
||||
deep idle. If it is important that the clock keeps running during system
|
||||
suspend, you need to specify the non-active clock, the one not containing
|
||||
*_A_* in the enumerator name.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- qcom,rpmcc-apq8060
|
||||
- qcom,rpmcc-apq8064
|
||||
- qcom,rpmcc-ipq806x
|
||||
- qcom,rpmcc-mdm9607
|
||||
- qcom,rpmcc-msm8226
|
||||
- qcom,rpmcc-msm8660
|
||||
- qcom,rpmcc-msm8916
|
||||
- qcom,rpmcc-msm8936
|
||||
- qcom,rpmcc-msm8953
|
||||
- qcom,rpmcc-msm8974
|
||||
- qcom,rpmcc-msm8976
|
||||
- qcom,rpmcc-msm8992
|
||||
- qcom,rpmcc-msm8994
|
||||
- qcom,rpmcc-msm8996
|
||||
- qcom,rpmcc-msm8998
|
||||
- qcom,rpmcc-qcm2290
|
||||
- qcom,rpmcc-qcs404
|
||||
- qcom,rpmcc-sdm660
|
||||
- qcom,rpmcc-sm6115
|
||||
- qcom,rpmcc-sm6125
|
||||
- const: qcom,rpmcc
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: xo
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
rpm {
|
||||
rpm-requests {
|
||||
compatible = "qcom,rpm-msm8916";
|
||||
qcom,smd-channels = "rpm_requests";
|
||||
|
||||
clock-controller {
|
||||
compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
172
Bindings/clock/qcom,sc7280-lpasscorecc.yaml
Normal file
172
Bindings/clock/qcom,sc7280-lpasscorecc.yaml
Normal file
@ -0,0 +1,172 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sc7280-lpasscorecc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm LPASS Core & Audio Clock Controller Binding for SC7280
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm LPASS core and audio clock control module which supports the
|
||||
clocks and power domains on SC7280.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,lpasscorecc-sc7280.h
|
||||
- dt-bindings/clock/qcom,lpassaudiocc-sc7280.h
|
||||
|
||||
properties:
|
||||
clocks: true
|
||||
|
||||
clock-names: true
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sc7280-lpassaoncc
|
||||
- qcom,sc7280-lpassaudiocc
|
||||
- qcom,sc7280-lpasscorecc
|
||||
- qcom,sc7280-lpasshm
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: qcom,sc7280-lpassaudiocc
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: LPASS_AON_CC_MAIN_RCG_CLK_SRC
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: lpass_aon_cc_main_rcg_clk_src
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,sc7280-lpassaoncc
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board XO active only source
|
||||
- description: LPASS_AON_CC_MAIN_RCG_CLK_SRC
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: bi_tcxo_ao
|
||||
- const: iface
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,sc7280-lpasshm
|
||||
- qcom,sc7280-lpasscorecc
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
|
||||
#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
|
||||
#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
|
||||
lpass_audiocc: clock-controller@3300000 {
|
||||
compatible = "qcom,sc7280-lpassaudiocc";
|
||||
reg = <0x3300000 0x30000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>;
|
||||
clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
|
||||
power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
|
||||
#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
|
||||
#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
|
||||
lpass_hm: clock-controller@3c00000 {
|
||||
compatible = "qcom,sc7280-lpasshm";
|
||||
reg = <0x3c00000 0x28>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "bi_tcxo";
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
|
||||
#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
|
||||
#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
|
||||
lpasscore: clock-controller@3900000 {
|
||||
compatible = "qcom,sc7280-lpasscorecc";
|
||||
reg = <0x3900000 0x50000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "bi_tcxo";
|
||||
power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>;
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
|
||||
#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
|
||||
#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
|
||||
lpass_aon: clock-controller@3380000 {
|
||||
compatible = "qcom,sc7280-lpassaoncc";
|
||||
reg = <0x3380000 0x30000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&lpasscore LPASS_CORE_CC_CORE_CLK>;
|
||||
clock-names = "bi_tcxo", "bi_tcxo_ao","iface";
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
...
|
||||
@ -49,6 +49,7 @@ properties:
|
||||
- renesas,r8a77995-cpg-mssr # R-Car D3
|
||||
- renesas,r8a779a0-cpg-mssr # R-Car V3U
|
||||
- renesas,r8a779f0-cpg-mssr # R-Car S4-8
|
||||
- renesas,r8a779g0-cpg-mssr # R-Car V4H
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@ -39,6 +39,17 @@ properties:
|
||||
'#power-domain-cells':
|
||||
const: 0
|
||||
|
||||
'#address-cells':
|
||||
const: 1
|
||||
|
||||
'#size-cells':
|
||||
const: 1
|
||||
|
||||
patternProperties:
|
||||
"^dma-router@[a-f0-9]+$":
|
||||
type: object
|
||||
$ref: "../dma/renesas,rzn1-dmamux.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
@ -4,14 +4,15 @@
|
||||
$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Renesas RZ/{G2L,V2L} Clock Pulse Generator / Module Standby Mode
|
||||
title: Renesas RZ/{G2L,V2L,V2M} Clock Pulse Generator / Module Standby Mode
|
||||
|
||||
maintainers:
|
||||
- Geert Uytterhoeven <geert+renesas@glider.be>
|
||||
|
||||
description: |
|
||||
On Renesas RZ/{G2L,V2L} SoC, the CPG (Clock Pulse Generator) and Module
|
||||
Standby Mode share the same register block.
|
||||
On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module
|
||||
Standby Mode share the same register block. On RZ/V2M, the functionality is
|
||||
similar, but does not have Clock Monitor Registers.
|
||||
|
||||
They provide the following functionalities:
|
||||
- The CPG block generates various core clocks,
|
||||
@ -23,8 +24,10 @@ description: |
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- renesas,r9a07g044-cpg # RZ/G2{L,LC}
|
||||
- renesas,r9a07g054-cpg # RZ/V2L
|
||||
- renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2}
|
||||
- renesas,r9a07g044-cpg # RZ/G2{L,LC}
|
||||
- renesas,r9a07g054-cpg # RZ/V2L
|
||||
- renesas,r9a09g011-cpg # RZ/V2M
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@ -42,9 +45,10 @@ properties:
|
||||
description: |
|
||||
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
|
||||
and a core clock reference, as defined in
|
||||
<dt-bindings/clock/r9a07g*-cpg.h>
|
||||
<dt-bindings/clock/r9a0*-cpg.h>
|
||||
- For module clocks, the two clock specifier cells must be "CPG_MOD" and
|
||||
a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h>.
|
||||
a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h> or
|
||||
<dt-bindings/clock/r9a09g011-cpg.h>.
|
||||
const: 2
|
||||
|
||||
'#power-domain-cells':
|
||||
@ -58,7 +62,7 @@ properties:
|
||||
'#reset-cells':
|
||||
description:
|
||||
The single reset specifier cell must be the module number, as defined in
|
||||
the <dt-bindings/clock/r9a07g0*-cpg.h>.
|
||||
the <dt-bindings/clock/r9a07g0*-cpg.h> or <dt-bindings/clock/r9a09g011-cpg.h>.
|
||||
const: 1
|
||||
|
||||
required:
|
||||
|
||||
119
Bindings/clock/rockchip,px30-cru.yaml
Normal file
119
Bindings/clock/rockchip,px30-cru.yaml
Normal file
@ -0,0 +1,119 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,px30-cru.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip PX30 Clock and Reset Unit (CRU)
|
||||
|
||||
maintainers:
|
||||
- Elaine Zhang <zhangqing@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description: |
|
||||
The PX30 clock controller generates and supplies clocks to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required
|
||||
- "xin32k" - rtc clock - optional
|
||||
- "i2sx_clkin" - external I2S clock - optional
|
||||
- "gmac_clkin" - external GMAC clock - optional
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,px30-cru
|
||||
- rockchip,px30-pmucru
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: Clock for both PMUCRU and CRU
|
||||
- description: Clock for CRU (sourced from PMUCRU)
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: xin24m
|
||||
- const: gpll
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to the syscon managing the "general register files" (GRF),
|
||||
if missing pll rates are not changeable, due to the missing pll
|
||||
lock status.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: rockchip,px30-cru
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 2
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
|
||||
else:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
maxItems: 1
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/px30-cru.h>
|
||||
|
||||
pmucru: clock-controller@ff2bc000 {
|
||||
compatible = "rockchip,px30-pmucru";
|
||||
reg = <0xff2bc000 0x1000>;
|
||||
clocks = <&xin24m>;
|
||||
clock-names = "xin24m";
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
cru: clock-controller@ff2b0000 {
|
||||
compatible = "rockchip,px30-cru";
|
||||
reg = <0xff2b0000 0x1000>;
|
||||
clocks = <&xin24m>, <&pmucru PLL_GPLL>;
|
||||
clock-names = "xin24m", "gpll";
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
72
Bindings/clock/rockchip,rk3036-cru.yaml
Normal file
72
Bindings/clock/rockchip,rk3036-cru.yaml
Normal file
@ -0,0 +1,72 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rk3036-cru.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip RK3036 Clock and Reset Unit (CRU)
|
||||
|
||||
maintainers:
|
||||
- Elaine Zhang <zhangqing@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description: |
|
||||
The RK3036 clock controller generates and supplies clocks to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required
|
||||
- "ext_i2s" - external I2S clock - optional
|
||||
- "rmii_clkin" - external EMAC clock - optional
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rk3036-cru
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: xin24m
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to the syscon managing the "general register files" (GRF),
|
||||
if missing pll rates are not changeable, due to the missing pll
|
||||
lock status.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
cru: clock-controller@20000000 {
|
||||
compatible = "rockchip,rk3036-cru";
|
||||
reg = <0x20000000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
78
Bindings/clock/rockchip,rk3188-cru.yaml
Normal file
78
Bindings/clock/rockchip,rk3188-cru.yaml
Normal file
@ -0,0 +1,78 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rk3188-cru.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip RK3188/RK3066 Clock and Reset Unit (CRU)
|
||||
|
||||
maintainers:
|
||||
- Elaine Zhang <zhangqing@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description: |
|
||||
The RK3188/RK3066 clock controller generates and supplies clocks to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
|
||||
dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
|
||||
Similar macros exist for the reset sources in these files.
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required
|
||||
- "xin32k" - RTC clock - optional
|
||||
- "xin27m" - 27mhz crystal input on RK3066 - optional
|
||||
- "ext_hsadc" - external HSADC clock - optional
|
||||
- "ext_cif0" - external camera clock - optional
|
||||
- "ext_rmii" - external RMII clock - optional
|
||||
- "ext_jtag" - external JTAG clock - optional
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rk3066a-cru
|
||||
- rockchip,rk3188-cru
|
||||
- rockchip,rk3188a-cru
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: xin24m
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to the syscon managing the "general register files" (GRF),
|
||||
if missing pll rates are not changeable, due to the missing pll
|
||||
lock status.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
cru: clock-controller@20000000 {
|
||||
compatible = "rockchip,rk3188-cru";
|
||||
reg = <0x20000000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
74
Bindings/clock/rockchip,rk3228-cru.yaml
Normal file
74
Bindings/clock/rockchip,rk3228-cru.yaml
Normal file
@ -0,0 +1,74 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rk3228-cru.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip RK3228 Clock and Reset Unit (CRU)
|
||||
|
||||
maintainers:
|
||||
- Elaine Zhang <zhangqing@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description: |
|
||||
The RK3228 clock controller generates and supplies clocks to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required
|
||||
- "ext_i2s" - external I2S clock - optional
|
||||
- "ext_gmac" - external GMAC clock - optional
|
||||
- "ext_hsadc" - external HSADC clock - optional
|
||||
- "phy_50m_out" - output clock of the pll in the mac phy
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rk3228-cru
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: xin24m
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to the syscon managing the "general register files" (GRF),
|
||||
if missing pll rates are not changeable, due to the missing pll
|
||||
lock status.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
cru: clock-controller@20000000 {
|
||||
compatible = "rockchip,rk3228-cru";
|
||||
reg = <0x20000000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
85
Bindings/clock/rockchip,rk3288-cru.yaml
Normal file
85
Bindings/clock/rockchip,rk3288-cru.yaml
Normal file
@ -0,0 +1,85 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rk3288-cru.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip RK3288 Clock and Reset Unit (CRU)
|
||||
|
||||
maintainers:
|
||||
- Elaine Zhang <zhangqing@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description: |
|
||||
The RK3288 clock controller generates and supplies clocks to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
A revision of this SoC is available: rk3288w. The clock tree is a bit
|
||||
different so another dt-compatible is available. Noticed that it is only
|
||||
setting the difference but there is no automatic revision detection. This
|
||||
should be performed by boot loaders.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "xin32k" - rtc clock - optional,
|
||||
- "ext_i2s" - external I2S clock - optional,
|
||||
- "ext_hsadc" - external HSADC clock - optional,
|
||||
- "ext_edp_24m" - external display port clock - optional,
|
||||
- "ext_vip" - external VIP clock - optional,
|
||||
- "ext_isp" - external ISP clock - optional,
|
||||
- "ext_jtag" - external JTAG clock - optional
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rk3288-cru
|
||||
- rockchip,rk3288w-cru
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: xin24m
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to the syscon managing the "general register files" (GRF),
|
||||
if missing pll rates are not changeable, due to the missing pll
|
||||
lock status.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
cru: clock-controller@ff760000 {
|
||||
compatible = "rockchip,rk3288-cru";
|
||||
reg = <0xff760000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
76
Bindings/clock/rockchip,rk3308-cru.yaml
Normal file
76
Bindings/clock/rockchip,rk3308-cru.yaml
Normal file
@ -0,0 +1,76 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rk3308-cru.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip RK3308 Clock and Reset Unit (CRU)
|
||||
|
||||
maintainers:
|
||||
- Elaine Zhang <zhangqing@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description: |
|
||||
The RK3308 clock controller generates and supplies clocks to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required
|
||||
- "xin32k" - rtc clock - optional
|
||||
- "mclk_i2s0_8ch_in", "mclk_i2s1_8ch_in",
|
||||
"mclk_i2s2_8ch_in", "mclk_i2s3_8ch_in",
|
||||
"mclk_i2s0_2ch_in", "mclk_i2s1_2ch_in" - external I2S or
|
||||
SPDIF clock - optional
|
||||
- "mac_clkin" - external MAC clock - optional
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rk3308-cru
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: xin24m
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to the syscon managing the "general register files" (GRF),
|
||||
if missing pll rates are not changeable, due to the missing pll
|
||||
lock status.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
cru: clock-controller@ff500000 {
|
||||
compatible = "rockchip,rk3308-cru";
|
||||
reg = <0xff500000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
78
Bindings/clock/rockchip,rk3368-cru.yaml
Normal file
78
Bindings/clock/rockchip,rk3368-cru.yaml
Normal file
@ -0,0 +1,78 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rk3368-cru.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip RK3368 Clock and Reset Unit (CRU)
|
||||
|
||||
maintainers:
|
||||
- Elaine Zhang <zhangqing@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description: |
|
||||
The RK3368 clock controller generates and supplies clocks to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3368-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required
|
||||
- "xin32k" - rtc clock - optional
|
||||
- "ext_i2s" - external I2S clock - optional
|
||||
- "ext_gmac" - external GMAC clock - optional
|
||||
- "ext_hsadc" - external HSADC clock - optional
|
||||
- "ext_isp" - external ISP clock - optional
|
||||
- "ext_jtag" - external JTAG clock - optional
|
||||
- "ext_vip" - external VIP clock - optional
|
||||
- "usbotg_out" - output clock of the pll in the otg phy
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rk3368-cru
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: xin24m
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to the syscon managing the "general register files" (GRF),
|
||||
if missing pll rates are not changeable, due to the missing pll
|
||||
lock status.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
cru: clock-controller@ff760000 {
|
||||
compatible = "rockchip,rk3368-cru";
|
||||
reg = <0xff760000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Rockchip RK3399 Clock and Reset Unit
|
||||
|
||||
maintainers:
|
||||
- Xing Zheng <zhengxing@rock-chips.com>
|
||||
- Elaine Zhang <zhangqing@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description: |
|
||||
@ -22,11 +22,11 @@ description: |
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "xin32k" - rtc clock - optional,
|
||||
- "clkin_gmac" - external GMAC clock - optional,
|
||||
- "clkin_i2s" - external I2S clock - optional,
|
||||
- "pclkin_cif" - external ISP clock - optional,
|
||||
- "xin24m" - crystal input - required,
|
||||
- "xin32k" - rtc clock - optional,
|
||||
- "clkin_gmac" - external GMAC clock - optional,
|
||||
- "clkin_i2s" - external I2S clock - optional,
|
||||
- "pclkin_cif" - external ISP clock - optional,
|
||||
- "clk_usbphy0_480m" - output clock of the pll in the usbphy0
|
||||
- "clk_usbphy1_480m" - output clock of the pll in the usbphy1
|
||||
|
||||
@ -46,24 +46,15 @@ properties:
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 1
|
||||
|
||||
assigned-clocks:
|
||||
minItems: 1
|
||||
maxItems: 64
|
||||
|
||||
assigned-clock-parents:
|
||||
minItems: 1
|
||||
maxItems: 64
|
||||
|
||||
assigned-clock-rates:
|
||||
minItems: 1
|
||||
maxItems: 64
|
||||
clock-names:
|
||||
const: xin24m
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: >
|
||||
phandle to the syscon managing the "general register files". It is used
|
||||
description:
|
||||
Phandle to the syscon managing the "general register files". It is used
|
||||
for GRF muxes, if missing any muxes present in the GRF will not be
|
||||
available.
|
||||
|
||||
@ -77,7 +68,7 @@ additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
pmucru: pmu-clock-controller@ff750000 {
|
||||
pmucru: clock-controller@ff750000 {
|
||||
compatible = "rockchip,rk3399-pmucru";
|
||||
reg = <0xff750000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
@ -34,6 +34,19 @@ properties:
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: xin24m
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to the syscon managing the "general register files" (GRF),
|
||||
if missing pll rates are not changeable, due to the missing pll
|
||||
lock status.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
75
Bindings/clock/rockchip,rv1108-cru.yaml
Normal file
75
Bindings/clock/rockchip,rv1108-cru.yaml
Normal file
@ -0,0 +1,75 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rv1108-cru.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip RV1108 Clock and Reset Unit (CRU)
|
||||
|
||||
maintainers:
|
||||
- Elaine Zhang <zhangqing@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description: |
|
||||
The RV1108 clock controller generates and supplies clocks to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rv1108-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required
|
||||
- "ext_vip" - external VIP clock - optional
|
||||
- "ext_i2s" - external I2S clock - optional
|
||||
- "ext_gmac" - external GMAC clock - optional
|
||||
- "hdmiphy" - external clock input derived from HDMI PHY - optional
|
||||
- "usbphy" - external clock input derived from USB PHY - optional
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rv1108-cru
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: xin24m
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to the syscon managing the "general register files" (GRF),
|
||||
if missing pll rates are not changeable, due to the missing pll
|
||||
lock status.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
cru: clock-controller@20200000 {
|
||||
compatible = "rockchip,rv1108-cru";
|
||||
reg = <0x20200000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -61,4 +61,3 @@ examples:
|
||||
clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>;
|
||||
clock-names = "aclk200", "aclk400_mcuisp";
|
||||
};
|
||||
|
||||
|
||||
219
Bindings/clock/samsung,exynosautov9-clock.yaml
Normal file
219
Bindings/clock/samsung,exynosautov9-clock.yaml
Normal file
@ -0,0 +1,219 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/samsung,exynosautov9-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos Auto v9 SoC clock controller
|
||||
|
||||
maintainers:
|
||||
- Chanho Park <chanho61.park@samsung.com>
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
- Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
- Tomasz Figa <tomasz.figa@gmail.com>
|
||||
|
||||
description: |
|
||||
Exynos Auto v9 clock controller is comprised of several CMU units, generating
|
||||
clocks for different domains. Those CMU units are modeled as separate device
|
||||
tree nodes, and might depend on each other. Root clocks in that clock tree are
|
||||
two external clocks:: OSCCLK/XTCXO (26 MHz) and RTCCLK/XrtcXTI (32768 Hz).
|
||||
The external OSCCLK must be defined as fixed-rate clock in dts.
|
||||
|
||||
CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
|
||||
dividers; all other clocks of function blocks (other CMUs) are usually
|
||||
derived from CMU_TOP.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All clocks available for usage
|
||||
in clock consumer nodes are defined as preprocessor macros in
|
||||
'include/dt-bindings/clock/samsung,exynosautov9.h' header.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynosautov9-cmu-top
|
||||
- samsung,exynosautov9-cmu-busmc
|
||||
- samsung,exynosautov9-cmu-core
|
||||
- samsung,exynosautov9-cmu-fsys2
|
||||
- samsung,exynosautov9-cmu-peric0
|
||||
- samsung,exynosautov9-cmu-peric1
|
||||
- samsung,exynosautov9-cmu-peris
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 5
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 5
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynosautov9-cmu-top
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynosautov9-cmu-busmc
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_BUSMC bus clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: dout_clkcmu_busmc_bus
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynosautov9-cmu-core
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_CORE bus clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: dout_clkcmu_core_bus
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynosautov9-cmu-fsys2
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_FSYS2 bus clock (from CMU_TOP)
|
||||
- description: UFS clock (from CMU_TOP)
|
||||
- description: Ethernet clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: dout_clkcmu_fsys2_bus
|
||||
- const: dout_fsys2_clkcmu_ufs_embd
|
||||
- const: dout_fsys2_clkcmu_ethernet
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynosautov9-cmu-peric0
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_PERIC0 bus clock (from CMU_TOP)
|
||||
- description: PERIC0 IP clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: dout_clkcmu_peric0_bus
|
||||
- const: dout_clkcmu_peric0_ip
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynosautov9-cmu-peric1
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_PERIC1 bus clock (from CMU_TOP)
|
||||
- description: PERIC1 IP clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: dout_clkcmu_peric1_bus
|
||||
- const: dout_clkcmu_peric1_ip
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynosautov9-cmu-peris
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_PERIS bus clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: dout_clkcmu_peris_bus
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Clock controller node for CMU_FSYS2
|
||||
- |
|
||||
#include <dt-bindings/clock/samsung,exynosautov9.h>
|
||||
|
||||
cmu_fsys2: clock-controller@17c00000 {
|
||||
compatible = "samsung,exynosautov9-cmu-fsys2";
|
||||
reg = <0x17c00000 0x8000>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&xtcxo>,
|
||||
<&cmu_top DOUT_CLKCMU_FSYS2_BUS>,
|
||||
<&cmu_top DOUT_CLKCMU_FSYS2_UFS_EMBD>,
|
||||
<&cmu_top DOUT_CLKCMU_FSYS2_ETHERNET>;
|
||||
clock-names = "oscclk",
|
||||
"dout_clkcmu_fsys2_bus",
|
||||
"dout_fsys2_clkcmu_ufs_embd",
|
||||
"dout_fsys2_clkcmu_ethernet";
|
||||
};
|
||||
|
||||
...
|
||||
@ -41,6 +41,7 @@ description: |
|
||||
|
||||
The list of valid indices for STM32MP1 is available in:
|
||||
include/dt-bindings/reset-controller/stm32mp1-resets.h
|
||||
include/dt-bindings/reset-controller/stm32mp13-resets.h
|
||||
|
||||
This file implements defines like:
|
||||
#define LTDC_R 3072
|
||||
@ -57,7 +58,10 @@ properties:
|
||||
- enum:
|
||||
- st,stm32mp1-rcc-secure
|
||||
- st,stm32mp1-rcc
|
||||
- st,stm32mp13-rcc
|
||||
- const: syscon
|
||||
clocks: true
|
||||
clock-names: true
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@ -68,14 +72,53 @@ required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- st,stm32mp1-rcc-secure
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
description: Specifies oscillators.
|
||||
maxItems: 5
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: hse
|
||||
- const: hsi
|
||||
- const: csi
|
||||
- const: lse
|
||||
- const: lsi
|
||||
required:
|
||||
- clocks
|
||||
- clock-names
|
||||
else:
|
||||
properties:
|
||||
clocks:
|
||||
description:
|
||||
Specifies the external RX clock for ethernet MAC.
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: ETH_RX_CLK/ETH_REF_CLK
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/stm32mp1-clks.h>
|
||||
rcc: rcc@50000000 {
|
||||
compatible = "st,stm32mp1-rcc-secure", "syscon";
|
||||
reg = <0x50000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
clock-names = "hse", "hsi", "csi", "lse", "lsi";
|
||||
clocks = <&scmi_clk CK_SCMI_HSE>,
|
||||
<&scmi_clk CK_SCMI_HSI>,
|
||||
<&scmi_clk CK_SCMI_CSI>,
|
||||
<&scmi_clk CK_SCMI_LSE>,
|
||||
<&scmi_clk CK_SCMI_LSI>;
|
||||
};
|
||||
...
|
||||
|
||||
@ -109,6 +109,25 @@ properties:
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
clkout-clock:
|
||||
description: A subnode with three clock cells for externally routed clocks,
|
||||
output clocks. These are two PRCMU-internal clocks that can be divided and
|
||||
muxed out on the pads of the DB8500 SoC.
|
||||
type: object
|
||||
|
||||
properties:
|
||||
'#clock-cells':
|
||||
description:
|
||||
The first cell indicates which output clock we are using,
|
||||
possible values are 0 (CLKOUT1) and 1 (CLKOUT2).
|
||||
The second cell indicates which clock we want to use as source,
|
||||
possible values are 0 thru 7, see the defines for the different
|
||||
source clocks.
|
||||
The third cell is a divider, legal values are 1 thru 63.
|
||||
const: 3
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
@ -119,3 +138,41 @@ required:
|
||||
- smp-twd-clock
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/ste-db8500-clkout.h>
|
||||
clocks@8012 {
|
||||
compatible = "stericsson,u8500-clks";
|
||||
reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
|
||||
<0x8000f000 0x1000>, <0xa03ff000 0x1000>,
|
||||
<0xa03cf000 0x1000>;
|
||||
|
||||
prcmu_clk: prcmu-clock {
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
prcc_pclk: prcc-periph-clock {
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
|
||||
prcc_kclk: prcc-kernel-clock {
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
|
||||
prcc_reset: prcc-reset-controller {
|
||||
#reset-cells = <2>;
|
||||
};
|
||||
|
||||
rtc_clk: rtc32k-clock {
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
smp_twd_clk: smp-twd-clock {
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
clkout_clk: clkout-clock {
|
||||
#clock-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -15,6 +15,7 @@ properties:
|
||||
- enum:
|
||||
- ti,am654-ehrpwm-tbclk
|
||||
- ti,am64-epwm-tbclk
|
||||
- ti,am62-epwm-tbclk
|
||||
- const: syscon
|
||||
|
||||
"#clock-cells":
|
||||
|
||||
@ -21,6 +21,7 @@ Required properties :
|
||||
"ti,clkctrl-l4-per"
|
||||
"ti,clkctrl-l4-secure"
|
||||
"ti,clkctrl-l4-wkup"
|
||||
- clock-output-names : from common clock binding
|
||||
- #clock-cells : shall contain 2 with the first entry being the instance
|
||||
offset from the clock domain base and the second being the
|
||||
clock index
|
||||
@ -32,7 +33,8 @@ Example: Clock controller node on omap 4430:
|
||||
l4per: cm@1400 {
|
||||
cm_l4per@0 {
|
||||
cm_l4per_clkctrl: clock@20 {
|
||||
compatible = "ti,clkctrl-l4-per", "ti,clkctrl";
|
||||
compatible = "ti,clkctrl";
|
||||
clock-output-names = "l4_per";
|
||||
reg = <0x20 0x1b0>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
|
||||
@ -17,6 +17,9 @@ Required properties:
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clocks : link phandles of clocks within this domain
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names : from common clock binding.
|
||||
|
||||
Examples:
|
||||
dss_clkdm: dss_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
|
||||
@ -27,6 +27,9 @@ Required properties:
|
||||
- clocks : link phandles of component clocks
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names : from common clock binding.
|
||||
|
||||
Examples:
|
||||
|
||||
usb_l4_gate_ick: usb_l4_gate_ick {
|
||||
|
||||
@ -16,6 +16,7 @@ Required properties:
|
||||
- clocks: parent clock.
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names : from common clock binding.
|
||||
- ti,autoidle-shift: bit shift of the autoidle enable bit for the clock,
|
||||
see [2]
|
||||
- reg: offset for the autoidle register of this clock, see [2]
|
||||
|
||||
@ -36,6 +36,7 @@ Required properties:
|
||||
ti,clkdm-gate-clock type
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names : from common clock binding.
|
||||
- ti,bit-shift : bit shift for programming the clock gate, invalid for
|
||||
ti,clkdm-gate-clock type
|
||||
- ti,set-bit-to-disable : inverts default gate programming. Setting the bit
|
||||
|
||||
@ -28,6 +28,7 @@ Required properties:
|
||||
- reg : base address for the control register
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names : from common clock binding.
|
||||
- ti,bit-shift : bit shift for the bit enabling/disabling the clock (default 0)
|
||||
|
||||
Examples:
|
||||
|
||||
@ -42,6 +42,7 @@ Required properties:
|
||||
- reg : register offset for register controlling adjustable mux
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names : from common clock binding.
|
||||
- ti,bit-shift : number of bits to shift the bit-mask, defaults to
|
||||
0 if not present
|
||||
- ti,index-starts-at-one : valid input select programming starts at 1, not
|
||||
|
||||
@ -16,7 +16,7 @@ has been processed. See [2] for more information on the brcm,l2-intc node.
|
||||
firmware. On some SoCs, this firmware supports DFS and DVFS in addition to
|
||||
Adaptive Voltage Scaling.
|
||||
|
||||
[2] Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt
|
||||
[2] Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.yaml
|
||||
|
||||
|
||||
Node brcm,avs-cpu-data-mem
|
||||
|
||||
@ -20,6 +20,13 @@ Optional properties:
|
||||
Vsram to fit SoC specific needs. When absent, the voltage scaling
|
||||
flow is handled by hardware, hence no software "voltage tracking" is
|
||||
needed.
|
||||
- mediatek,cci:
|
||||
Used to confirm the link status between cpufreq and mediatek cci. Because
|
||||
cpufreq and mediatek cci could share the same regulator in some MediaTek SoCs.
|
||||
To prevent the issue of high frequency and low voltage, we need to use this
|
||||
property to make sure mediatek cci is ready.
|
||||
For details of mediatek cci, please refer to
|
||||
Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
|
||||
- #cooling-cells:
|
||||
For details, please refer to
|
||||
Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml
|
||||
|
||||
@ -82,4 +82,3 @@ examples:
|
||||
clock-names = "bus", "mod";
|
||||
resets = <&ccu RST_BUS_CE>;
|
||||
};
|
||||
|
||||
|
||||
@ -15,6 +15,7 @@ properties:
|
||||
- ti,j721e-sa2ul
|
||||
- ti,am654-sa2ul
|
||||
- ti,am64-sa2ul
|
||||
- ti,am62-sa3ul
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@ -62,6 +62,7 @@ properties:
|
||||
- allwinner,sun8i-r40-display-engine
|
||||
- allwinner,sun8i-v3s-display-engine
|
||||
- allwinner,sun9i-a80-display-engine
|
||||
- allwinner,sun20i-d1-display-engine
|
||||
- allwinner,sun50i-a64-display-engine
|
||||
- allwinner,sun50i-h6-display-engine
|
||||
|
||||
@ -93,6 +94,7 @@ if:
|
||||
- allwinner,sun8i-a83t-display-engine
|
||||
- allwinner,sun8i-r40-display-engine
|
||||
- allwinner,sun9i-a80-display-engine
|
||||
- allwinner,sun20i-d1-display-engine
|
||||
- allwinner,sun50i-a64-display-engine
|
||||
|
||||
then:
|
||||
|
||||
@ -33,6 +33,8 @@ properties:
|
||||
- const: allwinner,sun8i-v3s-tcon
|
||||
- const: allwinner,sun9i-a80-tcon-lcd
|
||||
- const: allwinner,sun9i-a80-tcon-tv
|
||||
- const: allwinner,sun20i-d1-tcon-lcd
|
||||
- const: allwinner,sun20i-d1-tcon-tv
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
|
||||
@ -19,6 +19,8 @@ properties:
|
||||
- allwinner,sun8i-r40-de2-mixer-0
|
||||
- allwinner,sun8i-r40-de2-mixer-1
|
||||
- allwinner,sun8i-v3s-de2-mixer
|
||||
- allwinner,sun20i-d1-de2-mixer-0
|
||||
- allwinner,sun20i-d1-de2-mixer-1
|
||||
- allwinner,sun50i-a64-de2-mixer-0
|
||||
- allwinner,sun50i-a64-de2-mixer-1
|
||||
- allwinner,sun50i-h6-de3-mixer-0
|
||||
|
||||
@ -41,6 +41,7 @@ properties:
|
||||
compatible:
|
||||
enum:
|
||||
- allwinner,sun8i-r40-tcon-top
|
||||
- allwinner,sun20i-d1-tcon-top
|
||||
- allwinner,sun50i-h6-tcon-top
|
||||
|
||||
reg:
|
||||
@ -48,31 +49,15 @@ properties:
|
||||
|
||||
clocks:
|
||||
minItems: 2
|
||||
items:
|
||||
- description: The TCON TOP interface clock
|
||||
- description: The TCON TOP TV0 clock
|
||||
- description: The TCON TOP TVE0 clock
|
||||
- description: The TCON TOP TV1 clock
|
||||
- description: The TCON TOP TVE1 clock
|
||||
- description: The TCON TOP MIPI DSI clock
|
||||
maxItems: 6
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
items:
|
||||
- const: bus
|
||||
- const: tcon-tv0
|
||||
- const: tve0
|
||||
- const: tcon-tv1
|
||||
- const: tve1
|
||||
- const: dsi
|
||||
maxItems: 6
|
||||
|
||||
clock-output-names:
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
description: >
|
||||
The first item is the name of the clock created for the TV0
|
||||
channel, the second item is the name of the TCON TV1 channel
|
||||
clock and the third one is the name of the DSI channel clock.
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
@ -129,32 +114,92 @@ required:
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: allwinner,sun50i-h6-tcon-top
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: allwinner,sun8i-r40-tcon-top
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 2
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: The TCON TOP interface clock
|
||||
- description: The TCON TOP TV0 clock
|
||||
- description: The TCON TOP TVE0 clock
|
||||
- description: The TCON TOP TV1 clock
|
||||
- description: The TCON TOP TVE1 clock
|
||||
- description: The TCON TOP MIPI DSI clock
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
clock-names:
|
||||
items:
|
||||
- const: bus
|
||||
- const: tcon-tv0
|
||||
- const: tve0
|
||||
- const: tcon-tv1
|
||||
- const: tve1
|
||||
- const: dsi
|
||||
|
||||
else:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 6
|
||||
clock-output-names:
|
||||
items:
|
||||
- description: TCON TV0 output clock name
|
||||
- description: TCON TV1 output clock name
|
||||
- description: DSI output clock name
|
||||
|
||||
clock-output-names:
|
||||
minItems: 3
|
||||
ports:
|
||||
required:
|
||||
- port@2
|
||||
- port@3
|
||||
|
||||
ports:
|
||||
required:
|
||||
- port@2
|
||||
- port@3
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: allwinner,sun20i-d1-tcon-top
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: The TCON TOP interface clock
|
||||
- description: The TCON TOP TV0 clock
|
||||
- description: The TCON TOP TVE0 clock
|
||||
- description: The TCON TOP MIPI DSI clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bus
|
||||
- const: tcon-tv0
|
||||
- const: tve0
|
||||
- const: dsi
|
||||
|
||||
clock-output-names:
|
||||
items:
|
||||
- description: TCON TV0 output clock name
|
||||
- description: DSI output clock name
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: allwinner,sun50i-h6-tcon-top
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: The TCON TOP interface clock
|
||||
- description: The TCON TOP TV0 clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bus
|
||||
- const: tcon-tv0
|
||||
|
||||
clock-output-names:
|
||||
items:
|
||||
- description: TCON TV0 output clock name
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -150,4 +150,3 @@ examples:
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
89
Bindings/display/arm,hdlcd.yaml
Normal file
89
Bindings/display/arm,hdlcd.yaml
Normal file
@ -0,0 +1,89 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/arm,hdlcd.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Arm HDLCD display controller binding
|
||||
|
||||
maintainers:
|
||||
- Liviu Dudau <Liviu.Dudau@arm.com>
|
||||
- Andre Przywara <andre.przywara@arm.com>
|
||||
|
||||
description:
|
||||
The Arm HDLCD is a display controller found on several development platforms
|
||||
produced by ARM Ltd and in more modern of its Fast Models. The HDLCD is an
|
||||
RGB streamer that reads the data from a framebuffer and sends it to a single
|
||||
digital encoder (DVI or HDMI).
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: arm,hdlcd
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: pxlclk
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
description: The input reference for the pixel clock.
|
||||
|
||||
memory-region:
|
||||
maxItems: 1
|
||||
description:
|
||||
Phandle to a node describing memory to be used for the framebuffer.
|
||||
If not present, the framebuffer may be located anywhere in memory.
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
port:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
unevaluatedProperties: false
|
||||
description:
|
||||
Output endpoint of the controller, connecting the LCD panel signals.
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- port
|
||||
|
||||
examples:
|
||||
- |
|
||||
hdlcd@2b000000 {
|
||||
compatible = "arm,hdlcd";
|
||||
reg = <0x2b000000 0x1000>;
|
||||
interrupts = <0 85 4>;
|
||||
clocks = <&oscclk5>;
|
||||
clock-names = "pxlclk";
|
||||
port {
|
||||
hdlcd_output: endpoint {
|
||||
remote-endpoint = <&hdmi_enc_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* HDMI encoder on I2C bus */
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
hdmi-transmitter@70 {
|
||||
compatible = "nxp,tda998x";
|
||||
reg = <0x70>;
|
||||
port {
|
||||
hdmi_enc_input: endpoint {
|
||||
remote-endpoint = <&hdlcd_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
130
Bindings/display/arm,komeda.yaml
Normal file
130
Bindings/display/arm,komeda.yaml
Normal file
@ -0,0 +1,130 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/arm,komeda.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Arm Komeda display processor
|
||||
|
||||
maintainers:
|
||||
- Liviu Dudau <Liviu.Dudau@arm.com>
|
||||
- Andre Przywara <andre.przywara@arm.com>
|
||||
|
||||
description:
|
||||
The Arm Mali D71 display processor supports up to two displays with up
|
||||
to a 4K resolution each. Each pipeline can be composed of up to four
|
||||
layers. It is typically connected to a digital display connector like HDMI.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: arm,mali-d32
|
||||
- const: arm,mali-d71
|
||||
- const: arm,mali-d71
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: aclk
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
description: The main DPU processor clock
|
||||
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
"#size-cells":
|
||||
const: 0
|
||||
|
||||
memory-region:
|
||||
maxItems: 1
|
||||
description:
|
||||
Phandle to a node describing memory to be used for the framebuffer.
|
||||
If not present, the framebuffer may be located anywhere in memory.
|
||||
|
||||
iommus:
|
||||
description:
|
||||
The stream IDs for each of the used pipelines, each four IDs for the
|
||||
four layers, plus one for the write-back stream.
|
||||
minItems: 5
|
||||
maxItems: 10
|
||||
|
||||
patternProperties:
|
||||
'^pipeline@[01]$':
|
||||
type: object
|
||||
description:
|
||||
clocks
|
||||
|
||||
properties:
|
||||
reg:
|
||||
enum: [ 0, 1 ]
|
||||
|
||||
clock-names:
|
||||
const: pxclk
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
description: The input reference for the pixel clock.
|
||||
|
||||
port:
|
||||
$ref: /schemas/graph.yaml#/$defs/port-base
|
||||
unevaluatedProperties: false
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clock-names
|
||||
- clocks
|
||||
- pipeline@0
|
||||
|
||||
examples:
|
||||
- |
|
||||
display@c00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "arm,mali-d71";
|
||||
reg = <0xc00000 0x20000>;
|
||||
interrupts = <168>;
|
||||
clocks = <&dpu_aclk>;
|
||||
clock-names = "aclk";
|
||||
iommus = <&smmu 0>, <&smmu 1>, <&smmu 2>, <&smmu 3>,
|
||||
<&smmu 8>,
|
||||
<&smmu 4>, <&smmu 5>, <&smmu 6>, <&smmu 7>,
|
||||
<&smmu 9>;
|
||||
|
||||
dp0_pipe0: pipeline@0 {
|
||||
clocks = <&fpgaosc2>;
|
||||
clock-names = "pxclk";
|
||||
reg = <0>;
|
||||
|
||||
port {
|
||||
dp0_pipe0_out: endpoint {
|
||||
remote-endpoint = <&db_dvi0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dp0_pipe1: pipeline@1 {
|
||||
clocks = <&fpgaosc2>;
|
||||
clock-names = "pxclk";
|
||||
reg = <1>;
|
||||
|
||||
port {
|
||||
dp0_pipe1_out: endpoint {
|
||||
remote-endpoint = <&db_dvi1_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
119
Bindings/display/arm,malidp.yaml
Normal file
119
Bindings/display/arm,malidp.yaml
Normal file
@ -0,0 +1,119 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/arm,malidp.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Arm Mali Display Processor (Mali-DP) binding
|
||||
|
||||
maintainers:
|
||||
- Liviu Dudau <Liviu.Dudau@arm.com>
|
||||
- Andre Przywara <andre.przywara@arm.com>
|
||||
|
||||
description:
|
||||
The following bindings apply to a family of Display Processors sold as
|
||||
licensable IP by ARM Ltd. The bindings describe the Mali DP500, DP550 and
|
||||
DP650 processors that offer multiple composition layers, support for
|
||||
rotation and scaling output.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- arm,mali-dp500
|
||||
- arm,mali-dp550
|
||||
- arm,mali-dp650
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description:
|
||||
The interrupt used by the Display Engine (DE). Can be shared with
|
||||
the interrupt for the Scaling Engine (SE), but it will have to be
|
||||
listed individually.
|
||||
- description:
|
||||
The interrupt used by the Scaling Engine (SE). Can be shared with
|
||||
the interrupt for the Display Engine (DE), but it will have to be
|
||||
listed individually.
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: DE
|
||||
- const: SE
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pxlclk
|
||||
- const: mclk
|
||||
- const: aclk
|
||||
- const: pclk
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: the pixel clock feeding the output PLL of the processor
|
||||
- description: the main processor clock
|
||||
- description: the AXI interface clock
|
||||
- description: the APB interface clock
|
||||
|
||||
memory-region:
|
||||
maxItems: 1
|
||||
description:
|
||||
Phandle to a node describing memory to be used for the framebuffer.
|
||||
If not present, the framebuffer may be located anywhere in memory.
|
||||
|
||||
arm,malidp-output-port-lines:
|
||||
$ref: /schemas/types.yaml#/definitions/uint8-array
|
||||
description:
|
||||
Number of output lines/bits for each colour channel.
|
||||
items:
|
||||
- description: number of output lines for the red channel (R)
|
||||
- description: number of output lines for the green channel (G)
|
||||
- description: number of output lines for the blue channel (B)
|
||||
|
||||
arm,malidp-arqos-value:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Quality-of-Service value for the display engine FIFOs, to write
|
||||
into the RQOS register of the DP500.
|
||||
See the ARM Mali-DP500 TRM for details on the encoding.
|
||||
If omitted, the RQOS register will not be changed.
|
||||
|
||||
port:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
unevaluatedProperties: false
|
||||
description:
|
||||
Output endpoint of the controller, connecting the LCD panel signals.
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
- clocks
|
||||
- clock-names
|
||||
- port
|
||||
- arm,malidp-output-port-lines
|
||||
|
||||
examples:
|
||||
- |
|
||||
dp0: malidp@6f200000 {
|
||||
compatible = "arm,mali-dp650";
|
||||
reg = <0x6f200000 0x20000>;
|
||||
memory-region = <&display_reserved>;
|
||||
interrupts = <168>, <168>;
|
||||
interrupt-names = "DE", "SE";
|
||||
clocks = <&oscclk2>, <&fpgaosc0>, <&fpgaosc1>, <&fpgaosc1>;
|
||||
clock-names = "pxlclk", "mclk", "aclk", "pclk";
|
||||
arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
|
||||
arm,malidp-arqos-value = <0xd000d000>;
|
||||
|
||||
port {
|
||||
dp0_output: endpoint {
|
||||
remote-endpoint = <&tda998x_2_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
183
Bindings/display/arm,pl11x.yaml
Normal file
183
Bindings/display/arm,pl11x.yaml
Normal file
@ -0,0 +1,183 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/arm,pl11x.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Arm PrimeCell Color LCD Controller PL110/PL111
|
||||
|
||||
maintainers:
|
||||
- Liviu Dudau <Liviu.Dudau@arm.com>
|
||||
- Andre Przywara <andre.przywara@arm.com>
|
||||
|
||||
description:
|
||||
The Arm Primcell PL010/PL111 is an LCD controller IP, than scans out
|
||||
a framebuffer region in system memory, and creates timed signals for
|
||||
a variety of LCD panels.
|
||||
|
||||
# We need a select here so we don't match all nodes with 'arm,primecell'
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- arm,pl110
|
||||
- arm,pl111
|
||||
required:
|
||||
- compatible
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- arm,pl110
|
||||
- arm,pl111
|
||||
- const: arm,primecell
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-names:
|
||||
oneOf:
|
||||
- const: combined
|
||||
description:
|
||||
The IP provides four individual interrupt lines, but also one
|
||||
combined line. If the integration only connects this line to the
|
||||
interrupt controller, this single interrupt is noted here.
|
||||
- items:
|
||||
- const: mbe # CLCDMBEINTR
|
||||
- const: vcomp # CLCDVCOMPINTR
|
||||
- const: lnbu # CLCDLNBUINTR
|
||||
- const: fuf # CLCDFUFINTR
|
||||
|
||||
interrupts:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: clcdclk
|
||||
- const: apb_pclk
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: The CLCDCLK reference clock for the controller.
|
||||
- description: The HCLK AHB slave clock for the register access.
|
||||
|
||||
memory-region:
|
||||
maxItems: 1
|
||||
description:
|
||||
Phandle to a node describing memory to be used for the framebuffer.
|
||||
If not present, the framebuffer may be located anywhere in memory.
|
||||
|
||||
max-memory-bandwidth:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Maximum bandwidth in bytes per second that the cell's memory interface
|
||||
can handle.
|
||||
If not present, the memory interface is fast enough to handle all
|
||||
possible video modes.
|
||||
|
||||
port:
|
||||
$ref: /schemas/graph.yaml#/$defs/port-base
|
||||
additionalProperties: false
|
||||
|
||||
description:
|
||||
Output endpoint of the controller, connecting the LCD panel signals.
|
||||
|
||||
properties:
|
||||
endpoint:
|
||||
$ref: /schemas/graph.yaml#/$defs/endpoint-base
|
||||
unevaluatedProperties: false
|
||||
|
||||
properties:
|
||||
arm,pl11x,tft-r0g0b0-pads:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
items:
|
||||
- description: index of CLD pad used for first red bit (R0)
|
||||
- description: index of CLD pad used for first green bit (G0)
|
||||
- description: index of CLD pad used for first blue bit (G0)
|
||||
deprecated: true
|
||||
description: |
|
||||
DEPRECATED. An array of three 32-bit values, defining the way
|
||||
CLD[23:0] pads are wired up.
|
||||
The first value contains the index of the "CLD" external pin (pad)
|
||||
used as R0 (first bit of the red component), the second value for
|
||||
green, the third value for blue.
|
||||
See also "LCD panel signal multiplexing details" paragraphs in the
|
||||
PL110/PL111 Technical Reference Manuals.
|
||||
This implicitly defines available color modes, for example:
|
||||
- PL111 TFT 4:4:4 panel:
|
||||
arm,pl11x,tft-r0g0b0-pads = <4 15 20>;
|
||||
- PL110 TFT (1:)5:5:5 panel:
|
||||
arm,pl11x,tft-r0g0b0-pads = <1 7 13>;
|
||||
- PL111 TFT (1:)5:5:5 panel:
|
||||
arm,pl11x,tft-r0g0b0-pads = <3 11 19>;
|
||||
- PL111 TFT 5:6:5 panel:
|
||||
arm,pl11x,tft-r0g0b0-pads = <3 10 19>;
|
||||
- PL110 and PL111 TFT 8:8:8 panel:
|
||||
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
|
||||
- PL110 and PL111 TFT 8:8:8 panel, R & B components swapped:
|
||||
arm,pl11x,tft-r0g0b0-pads = <16 8 0>;
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clock-names
|
||||
- clocks
|
||||
- port
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
interrupts:
|
||||
minItems: 2
|
||||
required:
|
||||
- interrupts
|
||||
then:
|
||||
required:
|
||||
- interrupt-names
|
||||
|
||||
examples:
|
||||
- |
|
||||
clcd@10020000 {
|
||||
compatible = "arm,pl111", "arm,primecell";
|
||||
reg = <0x10020000 0x1000>;
|
||||
interrupt-names = "combined";
|
||||
interrupts = <44>;
|
||||
clocks = <&oscclk1>, <&oscclk2>;
|
||||
clock-names = "clcdclk", "apb_pclk";
|
||||
max-memory-bandwidth = <94371840>; /* Bps, 1024x768@60 16bpp */
|
||||
|
||||
port {
|
||||
clcd_pads: endpoint {
|
||||
remote-endpoint = <&clcd_panel>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
panel {
|
||||
compatible = "arm,rtsm-display", "panel-dpi";
|
||||
power-supply = <&vcc_supply>;
|
||||
|
||||
port {
|
||||
clcd_panel: endpoint {
|
||||
remote-endpoint = <&clcd_pads>;
|
||||
};
|
||||
};
|
||||
|
||||
panel-timing {
|
||||
clock-frequency = <25175000>;
|
||||
hactive = <640>;
|
||||
hback-porch = <40>;
|
||||
hfront-porch = <24>;
|
||||
hsync-len = <96>;
|
||||
vactive = <480>;
|
||||
vback-porch = <32>;
|
||||
vfront-porch = <11>;
|
||||
vsync-len = <2>;
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -41,10 +41,26 @@ properties:
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
$ref: /schemas/graph.yaml#/$defs/port-base
|
||||
unevaluatedProperties: false
|
||||
description:
|
||||
Video port for MIPI DSI input
|
||||
|
||||
properties:
|
||||
endpoint:
|
||||
$ref: /schemas/media/video-interfaces.yaml#
|
||||
unevaluatedProperties: false
|
||||
|
||||
properties:
|
||||
data-lanes:
|
||||
description: array of physical DSI data lane indexes.
|
||||
minItems: 1
|
||||
items:
|
||||
- const: 1
|
||||
- const: 2
|
||||
- const: 3
|
||||
- const: 4
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
|
||||
92
Bindings/display/bridge/fsl,ldb.yaml
Normal file
92
Bindings/display/bridge/fsl,ldb.yaml
Normal file
@ -0,0 +1,92 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/bridge/fsl,ldb.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale i.MX8MP DPI to LVDS bridge chip
|
||||
|
||||
maintainers:
|
||||
- Marek Vasut <marex@denx.de>
|
||||
|
||||
description: |
|
||||
The i.MX8MP mediamix contains two registers which are responsible
|
||||
for configuring the on-SoC DPI-to-LVDS serializer. This describes
|
||||
those registers as bridge within the DT.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx8mp-ldb
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: ldb
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Video port for DPI input.
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Video port for LVDS Channel-A output (panel or bridge).
|
||||
|
||||
port@2:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Video port for LVDS Channel-B output (panel or bridge).
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/imx8mp-clock.h>
|
||||
|
||||
blk-ctrl {
|
||||
bridge {
|
||||
compatible = "fsl,imx8mp-ldb";
|
||||
clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
|
||||
clock-names = "ldb";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
ldb_from_lcdif2: endpoint {
|
||||
remote-endpoint = <&lcdif2_to_ldb>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
ldb_lvds_ch0: endpoint {
|
||||
remote-endpoint = <&ldb_to_lvdsx4panel>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
|
||||
ldb_lvds_ch1: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -78,4 +78,3 @@ examples:
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -38,6 +38,9 @@ properties:
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
"#sound-dai-cells":
|
||||
const: 0
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
|
||||
117
Bindings/display/bridge/lontium,lt9211.yaml
Normal file
117
Bindings/display/bridge/lontium,lt9211.yaml
Normal file
@ -0,0 +1,117 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/bridge/lontium,lt9211.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Lontium LT9211 DSI/LVDS/DPI to DSI/LVDS/DPI bridge.
|
||||
|
||||
maintainers:
|
||||
- Marek Vasut <marex@denx.de>
|
||||
|
||||
description: |
|
||||
The LT9211 are bridge devices which convert Single/Dual-Link DSI/LVDS
|
||||
or Single DPI to Single/Dual-Link DSI/LVDS or Single DPI.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- lontium,lt9211
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
reset-gpios:
|
||||
maxItems: 1
|
||||
description: GPIO connected to active high RESET pin.
|
||||
|
||||
vccio-supply:
|
||||
description: Regulator for 1.8V IO power.
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
Primary MIPI DSI port-1 for MIPI input or
|
||||
LVDS port-1 for LVDS input or DPI input.
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
Additional MIPI port-2 for MIPI input or LVDS port-2
|
||||
for LVDS input. Used in combination with primary
|
||||
port-1 to drive higher resolution displays
|
||||
|
||||
port@2:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
Primary MIPI DSI port-1 for MIPI output or
|
||||
LVDS port-1 for LVDS output or DPI output.
|
||||
|
||||
port@3:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
Additional MIPI port-2 for MIPI output or LVDS port-2
|
||||
for LVDS output. Used in combination with primary
|
||||
port-1 to drive higher resolution displays.
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@2
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- vccio-supply
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
hdmi-bridge@3b {
|
||||
compatible = "lontium,lt9211";
|
||||
reg = <0x3b>;
|
||||
|
||||
reset-gpios = <&tlmm 128 GPIO_ACTIVE_HIGH>;
|
||||
interrupts-extended = <&tlmm 84 IRQ_TYPE_EDGE_FALLING>;
|
||||
|
||||
vccio-supply = <<9211_1v8>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
|
||||
endpoint {
|
||||
remote-endpoint = <&panel_in_lvds>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@ -119,4 +119,3 @@ examples:
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -53,16 +53,32 @@ properties:
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
$ref: /schemas/graph.yaml#/$defs/port-base
|
||||
unevaluatedProperties: false
|
||||
description: |
|
||||
DSI input port. The remote endpoint phandle should be a
|
||||
reference to a valid DSI output endpoint node
|
||||
|
||||
properties:
|
||||
endpoint:
|
||||
$ref: /schemas/media/video-interfaces.yaml#
|
||||
unevaluatedProperties: false
|
||||
|
||||
properties:
|
||||
data-lanes:
|
||||
description: array of physical DSI data lane indexes.
|
||||
minItems: 1
|
||||
items:
|
||||
- const: 1
|
||||
- const: 2
|
||||
- const: 3
|
||||
- const: 4
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: |
|
||||
DPI input port. The remote endpoint phandle should be a
|
||||
reference to a valid DPI output endpoint node
|
||||
DPI input/output port. The remote endpoint phandle should be a
|
||||
reference to a valid DPI output or input endpoint node.
|
||||
|
||||
port@2:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
|
||||
@ -58,6 +58,7 @@ properties:
|
||||
|
||||
properties:
|
||||
data-lines:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [ 16, 18, 24 ]
|
||||
|
||||
port@1:
|
||||
|
||||
@ -105,4 +105,3 @@ examples:
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -21,16 +21,19 @@ description: |
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: mediatek,mt8173-disp-aal
|
||||
- enum:
|
||||
- mediatek,mt8173-disp-aal
|
||||
- mediatek,mt8183-disp-aal
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt2712-disp-aal
|
||||
- mediatek,mt8183-disp-aal
|
||||
- const: mediatek,mt8173-disp-aal
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8186-disp-aal
|
||||
- mediatek,mt8192-disp-aal
|
||||
- mediatek,mt8195-disp-aal
|
||||
- enum:
|
||||
- mediatek,mt8173-disp-aal
|
||||
- const: mediatek,mt8183-disp-aal
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@ -28,8 +28,11 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8195-disp-ccorr
|
||||
- const: mediatek,mt8192-disp-ccorr
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8192-disp-ccorr
|
||||
- mediatek,mt8186-disp-ccorr
|
||||
- const: mediatek,mt8183-disp-ccorr
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@ -32,15 +32,14 @@ properties:
|
||||
- enum:
|
||||
- mediatek,mt7623-disp-color
|
||||
- mediatek,mt2712-disp-color
|
||||
- enum:
|
||||
- mediatek,mt2701-disp-color
|
||||
- const: mediatek,mt2701-disp-color
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8183-disp-color
|
||||
- mediatek,mt8186-disp-color
|
||||
- mediatek,mt8192-disp-color
|
||||
- mediatek,mt8195-disp-color
|
||||
- enum:
|
||||
- mediatek,mt8173-disp-color
|
||||
- const: mediatek,mt8173-disp-color
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
|
||||
@ -26,10 +26,10 @@ properties:
|
||||
- const: mediatek,mt8183-disp-dither
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8186-disp-dither
|
||||
- mediatek,mt8192-disp-dither
|
||||
- mediatek,mt8195-disp-dither
|
||||
- enum:
|
||||
- mediatek,mt8183-disp-dither
|
||||
- const: mediatek,mt8183-disp-dither
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@ -22,6 +22,7 @@ properties:
|
||||
- mediatek,mt7623-dpi
|
||||
- mediatek,mt8173-dpi
|
||||
- mediatek,mt8183-dpi
|
||||
- mediatek,mt8186-dpi
|
||||
- mediatek,mt8192-dpi
|
||||
|
||||
reg:
|
||||
|
||||
@ -27,10 +27,10 @@ properties:
|
||||
- const: mediatek,mt8183-disp-gamma
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8186-disp-gamma
|
||||
- mediatek,mt8192-disp-gamma
|
||||
- mediatek,mt8195-disp-gamma
|
||||
- enum:
|
||||
- mediatek,mt8183-disp-gamma
|
||||
- const: mediatek,mt8183-disp-gamma
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@ -102,4 +102,3 @@ examples:
|
||||
clock-names = "merge";
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -23,21 +23,16 @@ description: |
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: mediatek,mt2701-disp-mutex
|
||||
- items:
|
||||
- const: mediatek,mt2712-disp-mutex
|
||||
- items:
|
||||
- const: mediatek,mt8167-disp-mutex
|
||||
- items:
|
||||
- const: mediatek,mt8173-disp-mutex
|
||||
- items:
|
||||
- const: mediatek,mt8183-disp-mutex
|
||||
- items:
|
||||
- const: mediatek,mt8192-disp-mutex
|
||||
- items:
|
||||
- const: mediatek,mt8195-disp-mutex
|
||||
enum:
|
||||
- mediatek,mt2701-disp-mutex
|
||||
- mediatek,mt2712-disp-mutex
|
||||
- mediatek,mt8167-disp-mutex
|
||||
- mediatek,mt8173-disp-mutex
|
||||
- mediatek,mt8183-disp-mutex
|
||||
- mediatek,mt8186-disp-mutex
|
||||
- mediatek,mt8192-disp-mutex
|
||||
- mediatek,mt8195-disp-mutex
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
|
||||
@ -25,6 +25,10 @@ properties:
|
||||
- const: mediatek,mt8183-disp-ovl-2l
|
||||
- items:
|
||||
- const: mediatek,mt8192-disp-ovl-2l
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8186-disp-ovl-2l
|
||||
- const: mediatek,mt8192-disp-ovl-2l
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@ -33,13 +33,15 @@ properties:
|
||||
- enum:
|
||||
- mediatek,mt7623-disp-ovl
|
||||
- mediatek,mt2712-disp-ovl
|
||||
- enum:
|
||||
- mediatek,mt2701-disp-ovl
|
||||
- const: mediatek,mt2701-disp-ovl
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8195-disp-ovl
|
||||
- const: mediatek,mt8183-disp-ovl
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8183-disp-ovl
|
||||
- mediatek,mt8186-disp-ovl
|
||||
- const: mediatek,mt8192-disp-ovl
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@ -23,6 +23,10 @@ properties:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: mediatek,mt8192-disp-postmask
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8186-disp-postmask
|
||||
- const: mediatek,mt8192-disp-postmask
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user