Extend the ACPI power management support to wire a virtual power button up
to SIGTERM when ACPI is enabled. Sending SIGTERM to the hypervisor when an ACPI-aware OS is running will now trigger a soft-off allowing for a graceful shutdown of the guest. - Move constants for ACPI-related registers to acpi.h. - Implement an SMI_CMD register with commands to enable and disable ACPI. Currently the only change when ACPI is enabled is to enable the virtual power button via SIGTERM. - Implement a fixed-feature power button when ACPI is enabled by asserting PWRBTN_STS in PM1_EVT when SIGTERM is received. - Add support for EVFILT_SIGNAL events to mevent. - Implement support for the ACPI system command interrupt (SCI) and assert it when needed based on the values in PM1_EVT. Mark the SCI as active-low and level triggered in the MADT and MP Table. - Mark PCI interrupts in the MP Table as active-low in addition to level triggered. Reviewed by: neel
This commit is contained in:
John Baldwin
parent
cf952fe841
commit
058e24d34b
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=259998
@ -85,10 +85,6 @@ __FBSDID("$FreeBSD$");
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#define BHYVE_ASL_SUFFIX ".aml"
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#define BHYVE_ASL_COMPILER "/usr/sbin/iasl"
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#define BHYVE_PM1A_EVT_ADDR 0x400
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#define BHYVE_PM1A_CNT_ADDR 0x404
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#define BHYVE_PM_TIMER_ADDR 0x408
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static int basl_keep_temps;
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static int basl_verbose_iasl;
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static int basl_ncpu;
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@ -285,11 +281,11 @@ basl_fwrite_madt(FILE *fp)
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EFPRINTF(fp, "[0001]\t\tSubtable Type : 02\n");
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EFPRINTF(fp, "[0001]\t\tLength : 0A\n");
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EFPRINTF(fp, "[0001]\t\tBus : 00\n");
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EFPRINTF(fp, "[0001]\t\tSource : 09\n");
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EFPRINTF(fp, "[0004]\t\tInterrupt : 00000009\n");
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EFPRINTF(fp, "[0001]\t\tSource : %02X\n", SCI_INT);
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EFPRINTF(fp, "[0004]\t\tInterrupt : %08X\n", SCI_INT);
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EFPRINTF(fp, "[0002]\t\tFlags (decoded below) : 0000\n");
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EFPRINTF(fp, "\t\t\tPolarity : 0\n");
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EFPRINTF(fp, "\t\t\tTrigger Mode : 0\n");
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EFPRINTF(fp, "\t\t\tPolarity : 3\n");
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EFPRINTF(fp, "\t\t\tTrigger Mode : 3\n");
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EFPRINTF(fp, "\n");
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/* Local APIC NMI is connected to LINT 1 on all CPUs */
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@ -336,23 +332,27 @@ basl_fwrite_fadt(FILE *fp)
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basl_acpi_base + FACS_OFFSET);
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EFPRINTF(fp, "[0004]\t\tDSDT Address : %08X\n",
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basl_acpi_base + DSDT_OFFSET);
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EFPRINTF(fp, "[0001]\t\tModel : 00\n");
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EFPRINTF(fp, "[0001]\t\tModel : 01\n");
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EFPRINTF(fp, "[0001]\t\tPM Profile : 00 [Unspecified]\n");
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EFPRINTF(fp, "[0002]\t\tSCI Interrupt : 0009\n");
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EFPRINTF(fp, "[0004]\t\tSMI Command Port : 00000000\n");
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EFPRINTF(fp, "[0001]\t\tACPI Enable Value : 00\n");
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EFPRINTF(fp, "[0001]\t\tACPI Disable Value : 00\n");
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EFPRINTF(fp, "[0002]\t\tSCI Interrupt : %04X\n",
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SCI_INT);
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EFPRINTF(fp, "[0004]\t\tSMI Command Port : %08X\n",
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SMI_CMD);
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EFPRINTF(fp, "[0001]\t\tACPI Enable Value : %02X\n",
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BHYVE_ACPI_ENABLE);
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EFPRINTF(fp, "[0001]\t\tACPI Disable Value : %02X\n",
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BHYVE_ACPI_DISABLE);
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EFPRINTF(fp, "[0001]\t\tS4BIOS Command : 00\n");
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EFPRINTF(fp, "[0001]\t\tP-State Control : 00\n");
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EFPRINTF(fp, "[0004]\t\tPM1A Event Block Address : %08X\n",
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BHYVE_PM1A_EVT_ADDR);
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PM1A_EVT_ADDR);
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EFPRINTF(fp, "[0004]\t\tPM1B Event Block Address : 00000000\n");
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EFPRINTF(fp, "[0004]\t\tPM1A Control Block Address : %08X\n",
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BHYVE_PM1A_CNT_ADDR);
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PM1A_CNT_ADDR);
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EFPRINTF(fp, "[0004]\t\tPM1B Control Block Address : 00000000\n");
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EFPRINTF(fp, "[0004]\t\tPM2 Control Block Address : 00000000\n");
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EFPRINTF(fp, "[0004]\t\tPM Timer Block Address : %08X\n",
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BHYVE_PM_TIMER_ADDR);
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IO_PMTMR);
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EFPRINTF(fp, "[0004]\t\tGPE0 Block Address : 00000000\n");
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EFPRINTF(fp, "[0004]\t\tGPE1 Block Address : 00000000\n");
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EFPRINTF(fp, "[0001]\t\tPM1 Event Block Length : 04\n");
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@ -385,7 +385,7 @@ basl_fwrite_fadt(FILE *fp)
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EFPRINTF(fp, "\t\t\tWBINVD flushes all caches (V1) : 0\n");
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EFPRINTF(fp, "\t\t\tAll CPUs support C1 (V1) : 1\n");
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EFPRINTF(fp, "\t\t\tC2 works on MP system (V1) : 0\n");
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EFPRINTF(fp, "\t\t\tControl Method Power Button (V1) : 1\n");
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EFPRINTF(fp, "\t\t\tControl Method Power Button (V1) : 0\n");
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EFPRINTF(fp, "\t\t\tControl Method Sleep Button (V1) : 1\n");
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EFPRINTF(fp, "\t\t\tRTC wake not in fixed reg space (V1) : 0\n");
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EFPRINTF(fp, "\t\t\tRTC can wake system from S4 (V1) : 0\n");
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@ -427,7 +427,7 @@ basl_fwrite_fadt(FILE *fp)
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EFPRINTF(fp, "[0001]\t\tBit Offset : 00\n");
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EFPRINTF(fp, "[0001]\t\tEncoded Access Width : 02 [Word Access:16]\n");
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EFPRINTF(fp, "[0008]\t\tAddress : 00000000%08X\n",
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BHYVE_PM1A_EVT_ADDR);
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PM1A_EVT_ADDR);
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EFPRINTF(fp, "\n");
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EFPRINTF(fp,
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@ -447,7 +447,7 @@ basl_fwrite_fadt(FILE *fp)
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EFPRINTF(fp, "[0001]\t\tBit Offset : 00\n");
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EFPRINTF(fp, "[0001]\t\tEncoded Access Width : 02 [Word Access:16]\n");
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EFPRINTF(fp, "[0008]\t\tAddress : 00000000%08X\n",
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BHYVE_PM1A_CNT_ADDR);
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PM1A_CNT_ADDR);
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EFPRINTF(fp, "\n");
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EFPRINTF(fp,
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@ -479,7 +479,7 @@ basl_fwrite_fadt(FILE *fp)
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EFPRINTF(fp,
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"[0001]\t\tEncoded Access Width : 03 [DWord Access:32]\n");
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EFPRINTF(fp, "[0008]\t\tAddress : 00000000%08X\n",
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BHYVE_PM_TIMER_ADDR);
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IO_PMTMR);
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EFPRINTF(fp, "\n");
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EFPRINTF(fp, "[0012]\t\tGPE0 Block : [Generic Address Structure]\n");
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@ -29,6 +29,19 @@
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#ifndef _ACPI_H_
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#define _ACPI_H_
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#define SCI_INT 9
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#define SMI_CMD 0xb2
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#define BHYVE_ACPI_ENABLE 0xa0
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#define BHYVE_ACPI_DISABLE 0xa1
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#define PM1A_EVT_ADDR 0x400
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#define PM1A_CNT_ADDR 0x404
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#define IO_PMTMR 0x408 /* 4-byte i/o port for the timer */
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struct vmctx;
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int acpi_build(struct vmctx *ctx, int ncpu);
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#endif /* _ACPI_H_ */
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@ -135,6 +135,9 @@ mevent_kq_filter(struct mevent *mevp)
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if (mevp->me_type == EVF_TIMER)
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retval = EVFILT_TIMER;
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if (mevp->me_type == EVF_SIGNAL)
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retval = EVFILT_SIGNAL;
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return (retval);
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}
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@ -437,7 +440,7 @@ mevent_dispatch(void)
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* Block awaiting events
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*/
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ret = kevent(mfd, NULL, 0, eventlist, MEVENT_MAX, NULL);
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if (ret == -1) {
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if (ret == -1 && errno != EINTR) {
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perror("Error return from kevent monitor");
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}
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@ -32,7 +32,8 @@
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enum ev_type {
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EVF_READ,
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EVF_WRITE,
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EVF_TIMER
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EVF_TIMER,
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EVF_SIGNAL
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};
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struct mevent;
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@ -36,6 +36,7 @@ __FBSDID("$FreeBSD$");
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#include <stdio.h>
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#include <string.h>
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#include "acpi.h"
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#include "bhyverun.h"
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#include "mptbl.h"
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@ -227,13 +228,21 @@ mpt_build_ioint_entries(int_entry_ptr mpie, int num_pins, int id)
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mpie->int_type = INTENTRY_TYPE_INT;
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mpie->src_bus_irq = 0;
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break;
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case SCI_INT:
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/* ACPI SCI is level triggered and active-lo. */
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mpie->int_flags = INTENTRY_FLAGS_POLARITY_ACTIVELO |
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INTENTRY_FLAGS_TRIGGER_LEVEL;
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mpie->int_type = INTENTRY_TYPE_INT;
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mpie->src_bus_irq = SCI_INT;
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break;
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case 5:
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case 10:
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case 11:
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/*
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* PCI Irqs set to level triggered.
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* PCI Irqs set to level triggered and active-lo.
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*/
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mpie->int_flags = INTENTRY_FLAGS_TRIGGER_LEVEL;
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mpie->int_flags = INTENTRY_FLAGS_POLARITY_ACTIVELO |
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INTENTRY_FLAGS_TRIGGER_LEVEL;
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mpie->src_bus_id = 0;
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/* fall through.. */
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default:
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@ -29,11 +29,20 @@
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__FBSDID("$FreeBSD$");
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#include <sys/types.h>
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#include <machine/vmm.h>
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#include <assert.h>
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#include <pthread.h>
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#include <signal.h>
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#include <vmmapi.h>
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#include "acpi.h"
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#include "inout.h"
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#include "mevent.h"
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#define PM1A_EVT_ADDR 0x400
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#define PM1A_CNT_ADDR 0x404
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static pthread_mutex_t pm_lock = PTHREAD_MUTEX_INITIALIZER;
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static struct mevent *power_button;
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static sig_t old_power_handler;
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/*
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* Reset Control register at I/O port 0xcf9. Bit 2 forces a system
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@ -62,13 +71,76 @@ reset_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
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}
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INOUT_PORT(reset_reg, 0xCF9, IOPORT_F_INOUT, reset_handler);
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/*
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* ACPI's SCI is a level-triggered interrupt.
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*/
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static int sci_active;
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static void
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sci_assert(struct vmctx *ctx)
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{
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if (sci_active)
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return;
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vm_ioapic_assert_irq(ctx, SCI_INT);
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sci_active = 1;
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}
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static void
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sci_deassert(struct vmctx *ctx)
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{
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if (!sci_active)
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return;
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vm_ioapic_deassert_irq(ctx, SCI_INT);
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sci_active = 0;
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}
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/*
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* Power Management 1 Event Registers
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*
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* bhyve doesn't support any power management events currently, so the
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* status register always returns zero. The enable register preserves
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* its value but has no effect.
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* The only power management event supported is a power button upon
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* receiving SIGTERM.
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*/
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static uint16_t pm1_enable, pm1_status;
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#define PM1_TMR_STS 0x0001
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#define PM1_BM_STS 0x0010
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#define PM1_GBL_STS 0x0020
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#define PM1_PWRBTN_STS 0x0100
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#define PM1_SLPBTN_STS 0x0200
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#define PM1_RTC_STS 0x0400
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#define PM1_WAK_STS 0x8000
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#define PM1_TMR_EN 0x0001
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#define PM1_GBL_EN 0x0020
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#define PM1_PWRBTN_EN 0x0100
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#define PM1_SLPBTN_EN 0x0200
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#define PM1_RTC_EN 0x0400
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static void
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sci_update(struct vmctx *ctx)
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{
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int need_sci;
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/* See if the SCI should be active or not. */
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need_sci = 0;
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if ((pm1_enable & PM1_TMR_EN) && (pm1_status & PM1_TMR_STS))
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need_sci = 1;
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if ((pm1_enable & PM1_GBL_EN) && (pm1_status & PM1_GBL_STS))
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need_sci = 1;
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if ((pm1_enable & PM1_PWRBTN_EN) && (pm1_status & PM1_PWRBTN_STS))
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need_sci = 1;
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if ((pm1_enable & PM1_SLPBTN_EN) && (pm1_status & PM1_SLPBTN_STS))
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need_sci = 1;
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if ((pm1_enable & PM1_RTC_EN) && (pm1_status & PM1_RTC_STS))
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need_sci = 1;
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if (need_sci)
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sci_assert(ctx);
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else
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sci_deassert(ctx);
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}
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static int
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pm1_status_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
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uint32_t *eax, void *arg)
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@ -76,8 +148,20 @@ pm1_status_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
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if (bytes != 2)
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return (-1);
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pthread_mutex_lock(&pm_lock);
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if (in)
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*eax = 0;
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*eax = pm1_status;
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else {
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/*
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* Writes are only permitted to clear certain bits by
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* writing 1 to those flags.
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*/
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pm1_status &= ~(*eax & (PM1_WAK_STS | PM1_RTC_STS |
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PM1_SLPBTN_STS | PM1_PWRBTN_STS | PM1_BM_STS));
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sci_update(ctx);
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}
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pthread_mutex_unlock(&pm_lock);
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return (0);
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}
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@ -85,25 +169,51 @@ static int
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pm1_enable_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
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uint32_t *eax, void *arg)
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{
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static uint16_t pm1_enable;
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if (bytes != 2)
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return (-1);
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pthread_mutex_lock(&pm_lock);
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if (in)
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*eax = pm1_enable;
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else
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pm1_enable = *eax;
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else {
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/*
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* Only permit certain bits to be set. We never use
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* the global lock, but ACPI-CA whines profusely if it
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* can't set GBL_EN.
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*/
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pm1_enable = *eax & (PM1_PWRBTN_EN | PM1_GBL_EN);
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sci_update(ctx);
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}
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pthread_mutex_unlock(&pm_lock);
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return (0);
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}
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INOUT_PORT(pm1_status, PM1A_EVT_ADDR, IOPORT_F_INOUT, pm1_status_handler);
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INOUT_PORT(pm1_enable, PM1A_EVT_ADDR + 2, IOPORT_F_INOUT, pm1_enable_handler);
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static void
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power_button_handler(int signal, enum ev_type type, void *arg)
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{
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struct vmctx *ctx;
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ctx = arg;
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pthread_mutex_lock(&pm_lock);
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if (!(pm1_status & PM1_PWRBTN_STS)) {
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pm1_status |= PM1_PWRBTN_STS;
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sci_update(ctx);
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}
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pthread_mutex_unlock(&pm_lock);
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}
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/*
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* Power Management 1 Control Register
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*
|
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* This is mostly unimplemented except that we wish to handle writes that
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* set SPL_EN to handle S5 (soft power off).
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*/
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static uint16_t pm1_control;
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#define PM1_SCI_EN 0x0001
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#define PM1_SLP_TYP 0x1c00
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#define PM1_SLP_EN 0x2000
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#define PM1_ALWAYS_ZERO 0xc003
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@ -112,7 +222,6 @@ static int
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pm1_control_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
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uint32_t *eax, void *arg)
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{
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static uint16_t pm1_control;
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if (bytes != 2)
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return (-1);
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@ -121,9 +230,11 @@ pm1_control_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
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else {
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/*
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* Various bits are write-only or reserved, so force them
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* to zero in pm1_control.
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* to zero in pm1_control. Always preserve SCI_EN as OSPM
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* can never change it.
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*/
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pm1_control = *eax & ~(PM1_SLP_EN | PM1_ALWAYS_ZERO);
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pm1_control = (pm1_control & PM1_SCI_EN) |
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(*eax & ~(PM1_SLP_EN | PM1_ALWAYS_ZERO));
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/*
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* If SLP_EN is set, check for S5. Bhyve's _S5_ method
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@ -137,3 +248,41 @@ pm1_control_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
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return (0);
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}
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INOUT_PORT(pm1_control, PM1A_CNT_ADDR, IOPORT_F_INOUT, pm1_control_handler);
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|
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/*
|
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* ACPI SMI Command Register
|
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*
|
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* This write-only register is used to enable and disable ACPI.
|
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*/
|
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static int
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smi_cmd_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
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uint32_t *eax, void *arg)
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{
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assert(!in);
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if (bytes != 1)
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return (-1);
|
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|
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pthread_mutex_lock(&pm_lock);
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switch (*eax) {
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case BHYVE_ACPI_ENABLE:
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pm1_control |= PM1_SCI_EN;
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if (power_button == NULL) {
|
||||
power_button = mevent_add(SIGTERM, EVF_SIGNAL,
|
||||
power_button_handler, ctx);
|
||||
old_power_handler = signal(SIGTERM, SIG_IGN);
|
||||
}
|
||||
break;
|
||||
case BHYVE_ACPI_DISABLE:
|
||||
pm1_control &= ~PM1_SCI_EN;
|
||||
if (power_button != NULL) {
|
||||
mevent_delete(power_button);
|
||||
power_button = NULL;
|
||||
signal(SIGTERM, old_power_handler);
|
||||
}
|
||||
break;
|
||||
}
|
||||
pthread_mutex_unlock(&pm_lock);
|
||||
return (0);
|
||||
}
|
||||
INOUT_PORT(smi_cmd, SMI_CMD, IOPORT_F_OUT, smi_cmd_handler);
|
||||
|
||||
@ -40,6 +40,7 @@ __FBSDID("$FreeBSD$");
|
||||
#include <assert.h>
|
||||
#include <pthread.h>
|
||||
|
||||
#include "acpi.h"
|
||||
#include "inout.h"
|
||||
|
||||
/*
|
||||
@ -49,8 +50,6 @@ __FBSDID("$FreeBSD$");
|
||||
* This implementation will be 32-bits
|
||||
*/
|
||||
|
||||
#define IO_PMTMR 0x408 /* 4-byte i/o port for the timer */
|
||||
|
||||
#define PMTMR_FREQ 3579545 /* 3.579545MHz */
|
||||
|
||||
static pthread_mutex_t pmtmr_mtx;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user