arm64: Update the ID_AA64PFR0_EL1 fields
While here move to decimal for the _op and _CR definitions to be used by a future macro to define the register when the assembler doesn't know about it. Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D40895
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@ -1314,7 +1314,13 @@ static const struct mrs_field_value id_aa64pfr0_csv3[] = {
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static const struct mrs_field_value id_aa64pfr0_csv2[] = {
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MRS_FIELD_VALUE(ID_AA64PFR0_CSV2_NONE, ""),
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MRS_FIELD_VALUE(ID_AA64PFR0_CSV2_ISOLATED, "CSV2"),
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MRS_FIELD_VALUE(ID_AA64PFR0_CSV2_SCXTNUM, "SCXTNUM"),
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MRS_FIELD_VALUE(ID_AA64PFR0_CSV2_SCXTNUM, "CSV2_2"),
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MRS_FIELD_VALUE(ID_AA64PFR0_CSV2_3, "CSV2_3"),
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MRS_FIELD_VALUE_END,
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};
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static const struct mrs_field_value id_aa64pfr0_rme[] = {
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MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, RME, NONE, IMPL),
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MRS_FIELD_VALUE_END,
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};
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@ -1332,6 +1338,7 @@ static const struct mrs_field_hwcap id_aa64pfr0_dit_caps[] = {
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static const struct mrs_field_value id_aa64pfr0_amu[] = {
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MRS_FIELD_VALUE(ID_AA64PFR0_AMU_NONE, ""),
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MRS_FIELD_VALUE(ID_AA64PFR0_AMU_V1, "AMUv1"),
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MRS_FIELD_VALUE(ID_AA64PFR0_AMU_V1_1, "AMUv1p1"),
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MRS_FIELD_VALUE_END,
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};
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@ -1424,6 +1431,7 @@ static const struct mrs_field_value id_aa64pfr0_el0[] = {
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static const struct mrs_field id_aa64pfr0_fields[] = {
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MRS_FIELD(ID_AA64PFR0, CSV3, false, MRS_EXACT, id_aa64pfr0_csv3),
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MRS_FIELD(ID_AA64PFR0, CSV2, false, MRS_EXACT, id_aa64pfr0_csv2),
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MRS_FIELD(ID_AA64PFR0, RME, false, MRS_EXACT, id_aa64pfr0_rme),
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MRS_FIELD_HWCAP(ID_AA64PFR0, DIT, false, MRS_LOWER, id_aa64pfr0_dit,
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id_aa64pfr0_dit_caps),
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MRS_FIELD(ID_AA64PFR0, AMU, false, MRS_EXACT, id_aa64pfr0_amu),
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@ -1104,11 +1104,11 @@
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/* ID_AA64PFR0_EL1 */
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#define ID_AA64PFR0_EL1 MRS_REG(ID_AA64PFR0_EL1)
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#define ID_AA64PFR0_EL1_op0 0x3
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#define ID_AA64PFR0_EL1_op1 0x0
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#define ID_AA64PFR0_EL1_CRn 0x0
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#define ID_AA64PFR0_EL1_CRm 0x4
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#define ID_AA64PFR0_EL1_op2 0x0
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#define ID_AA64PFR0_EL1_op0 3
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#define ID_AA64PFR0_EL1_op1 0
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#define ID_AA64PFR0_EL1_CRn 0
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#define ID_AA64PFR0_EL1_CRm 4
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#define ID_AA64PFR0_EL1_op2 0
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#define ID_AA64PFR0_EL0_SHIFT 0
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#define ID_AA64PFR0_EL0_MASK (UL(0xf) << ID_AA64PFR0_EL0_SHIFT)
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#define ID_AA64PFR0_EL0_VAL(x) ((x) & ID_AA64PFR0_EL0_MASK)
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@ -1176,17 +1176,24 @@
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#define ID_AA64PFR0_AMU_VAL(x) ((x) & ID_AA64PFR0_AMU_MASK)
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#define ID_AA64PFR0_AMU_NONE (UL(0x0) << ID_AA64PFR0_AMU_SHIFT)
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#define ID_AA64PFR0_AMU_V1 (UL(0x1) << ID_AA64PFR0_AMU_SHIFT)
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#define ID_AA64PFR0_AMU_V1_1 (UL(0x2) << ID_AA64PFR0_AMU_SHIFT)
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#define ID_AA64PFR0_DIT_SHIFT 48
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#define ID_AA64PFR0_DIT_MASK (UL(0xf) << ID_AA64PFR0_DIT_SHIFT)
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#define ID_AA64PFR0_DIT_VAL(x) ((x) & ID_AA64PFR0_DIT_MASK)
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#define ID_AA64PFR0_DIT_NONE (UL(0x0) << ID_AA64PFR0_DIT_SHIFT)
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#define ID_AA64PFR0_DIT_PSTATE (UL(0x1) << ID_AA64PFR0_DIT_SHIFT)
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#define ID_AA64PFR0_RME_SHIFT 52
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#define ID_AA64PFR0_RME_MASK (UL(0xf) << ID_AA64PFR0_RME_SHIFT)
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#define ID_AA64PFR0_RME_VAL(x) ((x) & ID_AA64PFR0_RME_MASK)
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#define ID_AA64PFR0_RME_NONE (UL(0x0) << ID_AA64PFR0_RME_SHIFT)
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#define ID_AA64PFR0_RME_IMPL (UL(0x1) << ID_AA64PFR0_RME_SHIFT)
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#define ID_AA64PFR0_CSV2_SHIFT 56
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#define ID_AA64PFR0_CSV2_MASK (UL(0xf) << ID_AA64PFR0_CSV2_SHIFT)
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#define ID_AA64PFR0_CSV2_VAL(x) ((x) & ID_AA64PFR0_CSV2_MASK)
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#define ID_AA64PFR0_CSV2_NONE (UL(0x0) << ID_AA64PFR0_CSV2_SHIFT)
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#define ID_AA64PFR0_CSV2_ISOLATED (UL(0x1) << ID_AA64PFR0_CSV2_SHIFT)
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#define ID_AA64PFR0_CSV2_SCXTNUM (UL(0x2) << ID_AA64PFR0_CSV2_SHIFT)
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#define ID_AA64PFR0_CSV2_3 (UL(0x3) << ID_AA64PFR0_CSV2_SHIFT)
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#define ID_AA64PFR0_CSV3_SHIFT 60
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#define ID_AA64PFR0_CSV3_MASK (UL(0xf) << ID_AA64PFR0_CSV3_SHIFT)
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#define ID_AA64PFR0_CSV3_VAL(x) ((x) & ID_AA64PFR0_CSV3_MASK)
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