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dts: Import files from Linux 5.1

Browse Source 
MFC after:	2 months
This commit is contained in:
Emmanuel Vadot 2019-05-08 19:27:30 +00:00
commit 09001efbbe
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=347366
569 changed files with 23277 additions and 2804 deletions
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3
sys/gnu/dts/arm/alphascale-asm9260.dtsi
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@ -4,10 +4,11 @@
* Licensed under the X11 license or the GPL v2 (or later)
*/
#include "skeleton.dtsi"
#include <dt-bindings/clock/alphascale,asm9260.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&icoll>;
memory {

8
sys/gnu/dts/arm/alpine.dtsi
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@ -25,12 +25,18 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton64.dtsi"
/ {
#address-cells = <2>;
#size-cells = <2>;
/* SOC compatibility */
compatible = "al,alpine";
memory {
device_type = "memory";
reg = <0 0 0 0>;
};
/* CPU Configuration */
cpus {
#address-cells = <1>;

4
sys/gnu/dts/arm/am335x-baltos-ir2110.dts
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@ -72,7 +72,3 @@
dual_emac_res_vlan = <2>;
phy-handle = <&phy1>;
};
&phy_sel {
rmii-clock-ext = <1>;
};

4
sys/gnu/dts/arm/am335x-baltos-ir3220.dts
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@ -114,7 +114,3 @@
dual_emac_res_vlan = <2>;
phy-handle = <&phy1>;
};
&phy_sel {
rmii-clock-ext = <1>;
};

4
sys/gnu/dts/arm/am335x-baltos-ir5221.dts
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@ -133,10 +133,6 @@
phy-handle = <&phy1>;
};
&phy_sel {
rmii-clock-ext = <1>;
};
&dcan1 {
pinctrl-names = "default";
pinctrl-0 = <&dcan1_pins>;

8
sys/gnu/dts/arm/am335x-chiliboard.dts
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@ -14,6 +14,10 @@
compatible = "grinn,am335x-chiliboard", "grinn,am335x-chilisom",
"ti,am33xx";
chosen {
stdout-path = &uart0;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@ -151,10 +155,6 @@
phy-mode = "rmii";
};
&phy_sel {
rmii-clock-ext;
};
/* USB */
&usb {
status = "okay";

26
sys/gnu/dts/arm/am335x-evm.dts
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@ -57,6 +57,24 @@
enable-active-high;
};
/* TPS79501 */
v1_8d_reg: fixedregulator-v1_8d {
compatible = "regulator-fixed";
regulator-name = "v1_8d";
vin-supply = <&vbat>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
/* TPS79501 */
v3_3d_reg: fixedregulator-v3_3d {
compatible = "regulator-fixed";
regulator-name = "v3_3d";
vin-supply = <&vbat>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
matrix_keypad: matrix_keypad0 {
compatible = "gpio-matrix-keypad";
debounce-delay-ms = <5>;
@ -499,10 +517,10 @@
status = "okay";
/* Regulators */
AVDD-supply = <&vaux2_reg>;
IOVDD-supply = <&vaux2_reg>;
DRVDD-supply = <&vaux2_reg>;
DVDD-supply = <&vbat>;
AVDD-supply = <&v3_3d_reg>;
IOVDD-supply = <&v3_3d_reg>;
DRVDD-supply = <&v3_3d_reg>;
DVDD-supply = <&v1_8d_reg>;
};
};

26
sys/gnu/dts/arm/am335x-evmsk.dts
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@ -73,6 +73,24 @@
enable-active-high;
};
/* TPS79518 */
v1_8d_reg: fixedregulator-v1_8d {
compatible = "regulator-fixed";
regulator-name = "v1_8d";
vin-supply = <&vbat>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
/* TPS78633 */
v3_3d_reg: fixedregulator-v3_3d {
compatible = "regulator-fixed";
regulator-name = "v3_3d";
vin-supply = <&vbat>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
leds {
pinctrl-names = "default";
pinctrl-0 = <&user_leds_s0>;
@ -501,10 +519,10 @@
status = "okay";
/* Regulators */
AVDD-supply = <&vaux2_reg>;
IOVDD-supply = <&vaux2_reg>;
DRVDD-supply = <&vaux2_reg>;
DVDD-supply = <&vbat>;
AVDD-supply = <&v3_3d_reg>;
IOVDD-supply = <&v3_3d_reg>;
DRVDD-supply = <&v3_3d_reg>;
DVDD-supply = <&v1_8d_reg>;
};
};

511
sys/gnu/dts/arm/am335x-guardian.dts Normal file
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@ -0,0 +1,511 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2018 Robert Bosch Power Tools GmbH
*/
/dts-v1/;
#include "am33xx.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "Bosch AM335x Guardian";
compatible = "bosch,am335x-guardian", "ti,am33xx";
chosen {
stdout-path = &uart0;
tick-timer = &timer2;
};
cpus {
cpu@0 {
cpu0-supply = <&dcdc2_reg>;
};
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&gpio_keys_pins>;
button21 {
label = "guardian-power-button";
linux,code = <KEY_POWER>;
gpios = <&gpio2 21 0>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&leds_pins>;
led1 {
label = "green:heartbeat";
gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
led2 {
label = "green:mmc0";
gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
default-state = "off";
};
};
panel {
compatible = "ti,tilcdc,panel";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&lcd_pins_default &lcd_disen_pins>;
pinctrl-1 = <&lcd_pins_sleep>;
display-timings {
320x240 {
hactive = <320>;
vactive = <240>;
hback-porch = <68>;
hfront-porch = <20>;
hsync-len = <1>;
vback-porch = <18>;
vfront-porch = <4>;
vsync-len = <1>;
clock-frequency = <9000000>;
hsync-active = <0>;
vsync-active = <0>;
};
};
panel-info {
ac-bias = <255>;
ac-bias-intrpt = <0>;
dma-burst-sz = <16>;
bpp = <24>;
bus-width = <16>;
fdd = <0x80>;
sync-edge = <0>;
sync-ctrl = <1>;
raster-order = <0>;
fifo-th = <0>;
};
};
pwm7: dmtimer-pwm {
compatible = "ti,omap-dmtimer-pwm";
ti,timers = <&timer7>;
pinctrl-names = "default";
pinctrl-0 = <&dmtimer7_pins>;
};
vmmcsd_fixed: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "vmmcsd_fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&cppi41dma {
status = "okay";
};
&elm {
status = "okay";
};
&gpmc {
pinctrl-names = "default";
pinctrl-0 = <&nandflash_pins>;
ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
status = "okay";
nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
ti,nand-ecc-opt = "bch16";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <44>;
gpmc,cs-wr-off-ns = <44>;
gpmc,adv-on-ns = <6>;
gpmc,adv-rd-off-ns = <34>;
gpmc,adv-wr-off-ns = <44>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <40>;
gpmc,oe-on-ns = <0>;
gpmc,oe-off-ns = <54>;
gpmc,access-ns = <64>;
gpmc,rd-cycle-ns = <82>;
gpmc,wr-cycle-ns = <82>;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
/*
* MTD partition table
*
* All SPL-* partitions are sized to minimal length which can
* be independently programmable. For NAND flash this is equal
* to size of erase-block.
*/
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SPL";
reg = <0x0 0x40000>;
};
partition@1 {
label = "SPL.backup1";
reg = <0x40000 0x40000>;
};
partition@2 {
label = "SPL.backup2";
reg = <0x80000 0x40000>;
};
partition@3 {
label = "SPL.backup3";
reg = <0xc0000 0x40000>;
};
partition@4 {
label = "u-boot";
reg = <0x100000 0x100000>;
};
partition@5 {
label = "u-boot.backup1";
reg = <0x200000 0x100000>;
};
partition@6 {
label = "u-boot-env";
reg = <0x300000 0x40000>;
};
partition@7 {
label = "u-boot-env.backup1";
reg = <0x340000 0x40000>;
};
partition@8 {
label = "UBI";
reg = <0x380000 0x1fc80000>;
};
};
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
clock-frequency = <400000>;
status = "okay";
tps: tps@24 {
reg = <0x24>;
};
};
&lcdc {
blue-and-red-wiring = "crossed";
status = "okay";
};
&mmc1 {
bus-width = <0x4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
vmmc-supply = <&vmmcsd_fixed>;
status = "okay";
};
&rtc {
clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
system-power-controller;
};
&spi0 {
ti,pindir-d0-out-d1-in;
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
status = "okay";
};
#include "tps65217.dtsi"
&tps {
ti,pmic-shutdown-controller;
interrupt-parent = <&intc>;
interrupts = <7>; /* NMI */
backlight {
isel = <1>; /* 1 - ISET1, 2 ISET2 */
fdim = <100>; /* TPS65217_BL_FDIM_100HZ */
default-brightness = <100>;
};
regulators {
dcdc1_reg: regulator@0 {
regulator-name = "vdds_dpr";
regulator-always-on;
};
dcdc2_reg: regulator@1 {
regulator-name = "vdd_mpu";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <1351500>;
regulator-boot-on;
regulator-always-on;
};
dcdc3_reg: regulator@2 {
regulator-name = "vdd_core";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: regulator@3 {
regulator-name = "vio,vrtc,vdds";
regulator-always-on;
};
ldo2_reg: regulator@4 {
regulator-name = "vdd_3v3aux";
regulator-always-on;
};
ldo3_reg: regulator@5 {
regulator-name = "vdd_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo4_reg: regulator@6 {
regulator-name = "vdd_3v3a";
regulator-always-on;
};
};
};
&tscadc {
status = "okay";
adc {
ti,adc-channels = <0 1 2 3 4 5 6>;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&usb {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb0 {
dr_mode = "peripheral";
status = "okay";
};
&usb0_phy {
status = "okay";
};
&usb1 {
dr_mode = "host";
status = "okay";
};
&usb1_phy {
status = "okay";
};
&am33xx_pinmux {
pinctrl-names = "default";
pinctrl-0 = <&clkout2_pin &gpio_pins>;
clkout2_pin: pinmux_clkout2_pin {
pinctrl-single,pins = <
AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3)
>;
};
dmtimer7_pins: pinmux_dmtimer7_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE5)
>;
};
gpio_keys_pins: pinmux_gpio_keys_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE7)
>;
};
gpio_pins: pinmux_gpio_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE7)
>;
};
i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)
AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)
>;
};
lcd_disen_pins: pinmux_lcd_disen_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x9a4, PIN_OUTPUT_PULLUP | SLEWCTRL_SLOW | MUX_MODE7)
>;
};
lcd_pins_default: pinmux_lcd_pins_default {
pinctrl-single,pins = <
AM33XX_IOPAD(0x820, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
AM33XX_IOPAD(0x824, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
AM33XX_IOPAD(0x828, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
AM33XX_IOPAD(0x82c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
AM33XX_IOPAD(0x830, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
AM33XX_IOPAD(0x834, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
AM33XX_IOPAD(0x838, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
AM33XX_IOPAD(0x83c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
AM33XX_IOPAD(0x8a0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8a4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8a8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8ac, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8b0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8b4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8b8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8bc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8c0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8c4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8c8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8cc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8d0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8d4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8d8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8dc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8e0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8e4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8e8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8ec, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
>;
};
lcd_pins_sleep: pinmux_lcd_pins_sleep {
pinctrl-single,pins = <
AM33XX_IOPAD(0x8a0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8a4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8a8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8ac, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8b0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8b4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8b8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8bc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8c0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8c4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8c8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8cc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8d0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8d4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8d8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8dc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7)
>;
};
leds_pins: pinmux_leds_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x868, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x86c, PIN_OUTPUT | MUX_MODE7)
>;
};
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0)
AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0)
AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0)
AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0)
AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)
AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)
AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7)
>;
};
spi0_pins: pinmux_spi0_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x950, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
AM33XX_IOPAD(0x954, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0)
AM33XX_IOPAD(0x95c, PIN_OUTPUT_PULLUP | MUX_MODE0)
>;
};
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)
AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
>;
};
nandflash_pins: pinmux_nandflash_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x800, PIN_INPUT | MUX_MODE0)
AM33XX_IOPAD(0x804, PIN_INPUT | MUX_MODE0)
AM33XX_IOPAD(0x808, PIN_INPUT | MUX_MODE0)
AM33XX_IOPAD(0x80c, PIN_INPUT | MUX_MODE0)
AM33XX_IOPAD(0x810, PIN_INPUT | MUX_MODE0)
AM33XX_IOPAD(0x814, PIN_INPUT | MUX_MODE0)
AM33XX_IOPAD(0x818, PIN_INPUT | MUX_MODE0)
AM33XX_IOPAD(0x81c, PIN_INPUT | MUX_MODE0)
AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE0)
AM33XX_IOPAD(0x874, PIN_OUTPUT | MUX_MODE0)
AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)
AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)
AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)
AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)
AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)
>;
};
};

4
sys/gnu/dts/arm/am335x-icev2.dts
View File

@ -484,10 +484,6 @@
dual_emac;
};
&phy_sel {
rmii-clock-ext;
};
&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;

4
sys/gnu/dts/arm/am335x-igep0033.dtsi
View File

@ -123,10 +123,6 @@
phy-mode = "rmii";
};
&phy_sel {
rmii-clock-ext;
};
&elm {
status = "okay";
};

4
sys/gnu/dts/arm/am335x-lxm.dts
View File

@ -328,10 +328,6 @@
dual_emac_res_vlan = <3>;
};
&phy_sel {
rmii-clock-ext;
};
&mac {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;

5
sys/gnu/dts/arm/am335x-moxa-uc-2100-common.dtsi
View File

@ -159,11 +159,6 @@
status = "okay";
};
&phy_sel {
reg= <0x44e10650 0xf5>;
rmii-clock-ext;
};
&sham {
status = "okay";
};

5
sys/gnu/dts/arm/am335x-moxa-uc-8100-me-t.dts
View File

@ -446,11 +446,6 @@
dual_emac_res_vlan = <2>;
};
&phy_sel {
reg= <0x44e10650 0xf5>;
rmii-clock-ext;
};
&sham {
status = "okay";
};

4
sys/gnu/dts/arm/am335x-phycore-som.dtsi
View File

@ -100,10 +100,6 @@
status = "okay";
};
&phy_sel {
rmii-clock-ext;
};
/* I2C Busses */
&am33xx_pinmux {
i2c0_pins: pinmux_i2c0 {

4
sys/gnu/dts/arm/am335x-shc.dts
View File

@ -1,11 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
/*
* support for the bosch am335x based shc c3 board
*
* Copyright, C) 2015 Heiko Schocher <hs@denx.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;

21
sys/gnu/dts/arm/am33xx-l4.dtsi
View File

@ -279,17 +279,9 @@
#pinctrl-cells = <1>;
ranges = <0 0 0x2000>;
phy_sel: cpsw-phy-sel@650 {
compatible = "ti,am3352-cpsw-phy-sel";
reg= <0x650 0x4>;
reg-names = "gmii-sel";
};
am33xx_pinmux: pinmux@800 {
compatible = "pinctrl-single";
reg = <0x800 0x238>;
#address-cells = <1>;
#size-cells = <0>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x7f>;
@ -302,6 +294,12 @@
#size-cells = <1>;
ranges = <0 0 0x800>;
phy_gmii_sel: phy-gmii-sel {
compatible = "ti,am3352-phy-gmii-sel";
reg = <0x650 0x4>;
#phy-cells = <2>;
};
scm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
@ -717,7 +715,6 @@
interrupts = <40 41 42 43>;
ranges = <0 0 0x8000>;
syscon = <&scm_conf>;
cpsw-phy-sel = <&phy_sel>;
status = "disabled";
davinci_mdio: mdio@1000 {
@ -733,11 +730,13 @@
cpsw_emac0: slave@200 {
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
phys = <&phy_gmii_sel 1 1>;
};
cpsw_emac1: slave@300 {
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
phys = <&phy_gmii_sel 2 1>;
};
};
};
@ -1763,7 +1762,7 @@
reg = <0xcc000 0x4>;
reg-names = "rev";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
clocks = <&l4ls_clkctrl AM3_D_CAN0_CLKCTRL 0>;
clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN0_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
@ -1786,7 +1785,7 @@
reg = <0xd0000 0x4>;
reg-names = "rev";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
clocks = <&l4ls_clkctrl AM3_D_CAN1_CLKCTRL 0>;
clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN1_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;

496
sys/gnu/dts/arm/am3874-iceboard.dts Normal file
View File

@ -0,0 +1,496 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device tree for Winterland IceBoard
*
* http://mcgillcosmology.com
* http://threespeedlogic.com
*
* This is an ARM + FPGA instrumentation board used at telescopes in
* Antarctica (the South Pole Telescope), Chile (POLARBEAR), and at the DRAO
* observatory in British Columbia (CHIME).
*
* Copyright (c) 2019 Three-Speed Logic, Inc. <gsmecher@threespeedlogic.com>
*/
/dts-v1/;
#include "dm814x.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "Winterland IceBoard";
compatible = "ti,dm8148", "ti,dm814";
chosen {
stdout-path = "serial1:115200n8";
bootargs = "earlycon";
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x40000000>; /* 1 GB */
};
vmmcsd_fixed: fixedregulator0 {
compatible = "regulator-fixed";
regulator-name = "vmmcsd_fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
/* The MAC provides internal delay for the transmit path ONLY, which is enabled
* provided no -id/-txid/-rxid suffix is provided to "phy-mode".
*
* The receive path is delayed at the PHY. The recommended register settings
* are 0xf0 for the control bits, and 0x7777 for the data bits. However, the
* conversion code in the kernel lies: the PHY's registers are 120 ps per tap,
* and the kernel assumes 200 ps per tap. So we have fudged the numbers here to
* obtain the correct register settings.
*/
&mac { dual_emac = <1>; };
&cpsw_emac0 {
phy-handle = <&ethphy0>;
phy-mode = "rgmii";
dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
phy-handle = <&ethphy1>;
phy-mode = "rgmii";
dual_emac_res_vlan = <2>;
};
&davinci_mdio {
ethphy0: ethernet-phy@0 {
reg = <0x2>;
rxc-skew-ps = <3000>;
rxdv-skew-ps = <0>;
rxd3-skew-ps = <0>;
rxd2-skew-ps = <0>;
rxd1-skew-ps = <0>;
rxd0-skew-ps = <0>;
phy-reset-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
};
ethphy1: ethernet-phy@1 {
reg = <0x1>;
rxc-skew-ps = <3000>;
rxdv-skew-ps = <0>;
rxd3-skew-ps = <0>;
rxd2-skew-ps = <0>;
rxd1-skew-ps = <0>;
rxd0-skew-ps = <0>;
phy-reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
};
};
&mmc1 { status = "disabled"; };
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
vmmc-supply = <&vmmcsd_fixed>;
bus-width = <4>;
};
&mmc3 { status = "disabled"; };
&i2c1 {
/* Most I2C activity happens through this port, with the sole exception
* of the backplane. Since there are multiply assigned addresses, the
* "i2c-mux-idle-disconnect" is important.
*/
pca9548@70 {
compatible = "nxp,pca9548";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
/* FMC A */
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
i2c-mux-idle-disconnect;
};
i2c@1 {
/* FMC B */
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
i2c-mux-idle-disconnect;
};
i2c@2 {
/* QSFP A */
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
i2c-mux-idle-disconnect;
};
i2c@3 {
/* QSFP B */
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
i2c-mux-idle-disconnect;
};
i2c@4 {
/* SFP */
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
i2c-mux-idle-disconnect;
};
i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
i2c-mux-idle-disconnect;
ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <5000>; };
ina230@41 { compatible = "ti,ina230"; reg = <0x41>; shunt-resistor = <5000>; };
ina230@42 { compatible = "ti,ina230"; reg = <0x42>; shunt-resistor = <5000>; };
ina230@44 { compatible = "ti,ina230"; reg = <0x44>; shunt-resistor = <5000>; };
ina230@45 { compatible = "ti,ina230"; reg = <0x45>; shunt-resistor = <5000>; };
ina230@46 { compatible = "ti,ina230"; reg = <0x46>; shunt-resistor = <5000>; };
ina230@47 { compatible = "ti,ina230"; reg = <0x47>; shunt-resistor = <5500>; };
ina230@48 { compatible = "ti,ina230"; reg = <0x48>; shunt-resistor = <2360>; };
ina230@49 { compatible = "ti,ina230"; reg = <0x49>; shunt-resistor = <2360>; };
ina230@43 { compatible = "ti,ina230"; reg = <0x43>; shunt-resistor = <2360>; };
ina230@4b { compatible = "ti,ina230"; reg = <0x4b>; shunt-resistor = <5500>; };
ina230@4c { compatible = "ti,ina230"; reg = <0x4c>; shunt-resistor = <2360>; };
ina230@4d { compatible = "ti,ina230"; reg = <0x4d>; shunt-resistor = <770>; };
ina230@4e { compatible = "ti,ina230"; reg = <0x4e>; shunt-resistor = <770>; };
ina230@4f { compatible = "ti,ina230"; reg = <0x4f>; shunt-resistor = <770>; };
};
i2c@6 {
/* Backplane */
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
i2c-mux-idle-disconnect;
};
i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
i2c-mux-idle-disconnect;
u41: pca9575@20 {
compatible = "nxp,pca9575";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
"FMCA_EN_12V0", "FMCA_EN_3V3", "FMCA_EN_VADJ", "FMCA_PG_M2C",
"FMCA_PG_C2M", "FMCA_PRSNT_M2C_L", "FMCA_CLK_DIR", "SFP_LOS",
"FMCB_EN_12V0", "FMCB_EN_3V3", "FMCB_EN_VADJ", "FMCB_PG_M2C",
"FMCB_PG_C2M", "FMCB_PRSNT_M2C_L", "FMCB_CLK_DIR", "SFP_ModPrsL";
reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
};
u42: pca9575@21 {
compatible = "nxp,pca9575";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
"QSFPA_ModPrsL", "QSFPA_IntL", "QSFPA_ResetL", "QSFPA_ModSelL",
"QSFPA_LPMode", "QSFPB_ModPrsL", "QSFPB_IntL", "QSFPB_ResetL",
"SFP_TxFault", "SFP_TxDisable", "SFP_RS0", "SFP_RS1",
"QSFPB_ModSelL", "QSFPB_LPMode", "SEL_SFP", "ARM_MR";
reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
};
u48: pca9575@22 {
compatible = "nxp,pca9575";
reg=<0x22>;
gpio-controller;
#gpio-cells = <2>;
sw-gpios = <&u48 0 0>, <&u48 1 0>, <&u48 2 0>, <&u48 3 0>,
<&u48 4 0>, <&u48 5 0>, <&u48 6 0>, <&u48 7 0>;
led-gpios = <&u48 7 0>, <&u48 6 0>, <&u48 5 0>, <&u48 4 0>,
<&u48 3 0>, <&u48 2 0>, <&u48 1 0>, <&u48 0 0>;
gpio-line-names =
"GP_SW1", "GP_SW2", "GP_SW3", "GP_SW4",
"GP_SW5", "GP_SW6", "GP_SW7", "GP_SW8",
"GP_LED8", "GP_LED7", "GP_LED6", "GP_LED5",
"GP_LED4", "GP_LED3", "GP_LED2", "GP_LED1";
reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
};
u59: pca9575@23 {
compatible = "nxp,pca9575";
reg=<0x23>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
"GP_LED9", "GP_LED10", "GP_LED11", "GP_LED12",
"GTX1V8PowerFault", "PHYAPowerFault", "PHYBPowerFault", "ArmPowerFault",
"BP_SLOW_GPIO0", "BP_SLOW_GPIO1", "BP_SLOW_GPIO2", "BP_SLOW_GPIO3",
"BP_SLOW_GPIO4", "BP_SLOW_GPIO5", "__unused_u59_p16", "__unused_u59_p17";
reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
};
tmp100@48 { compatible = "ti,tmp100"; reg = <0x48>; };
tmp100@4a { compatible = "ti,tmp100"; reg = <0x4a>; };
tmp100@4b { compatible = "ti,tmp100"; reg = <0x4b>; };
tmp100@4c { compatible = "ti,tmp100"; reg = <0x4c>; };
/* EEPROM bank and serial number are treated as separate devices */
at24c01@57 { compatible = "atmel,24c01"; reg = <0x57>; };
at24cs01@5f { compatible = "atmel,24cs01"; reg = <0x5f>; };
};
};
};
&i2c2 {
pca9548@71 {
compatible = "nxp,pca9548";
reg = <0x71>;
#address-cells = <1>;
#size-cells = <0>;
i2c@6 {
/* Backplane */
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
multi-master;
/* All backplanes should have this -- it's how we know they're there. */
at24c08@54 { compatible="atmel,24c08"; reg=<0x54>; };
at24cs08@5c { compatible="atmel,24cs08"; reg=<0x5c>; };
/* 16 slot backplane */
tmp421@4d { compatible="ti,tmp421"; reg=<0x4d>; };
tmp421@4e { compatible="ti,tmp421"; reg=<0x4e>; };
ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <2360>; };
amc6821@18 { compatible = "ti,amc6821"; reg = <0x18>; };
/* Single slot backplane */
};
};
};
&pincntl {
mmc2_pins: pinmux_mmc2_pins {
pinctrl-single,pins = <
DM814X_IOPAD(0x0800, PIN_INPUT | 0x1) /* SD1_CLK */
DM814X_IOPAD(0x0804, PIN_INPUT_PULLUP | 0x1) /* SD1_CMD */
DM814X_IOPAD(0x0808, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[0] */
DM814X_IOPAD(0x080c, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[1] */
DM814X_IOPAD(0x0810, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[2] */
DM814X_IOPAD(0x0814, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[3] */
DM814X_IOPAD(0x0924, PIN_INPUT_PULLUP | 0x40) /* SD1_POW */
DM814X_IOPAD(0x0928, PIN_INPUT | 0x40) /* SD1_SDWP */
DM814X_IOPAD(0x093C, PIN_INPUT | 0x2) /* SD1_SDCD */
>;
};
usb0_pins: pinmux_usb0_pins {
pinctrl-single,pins = <
DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1) /* USB0_DRVVBUS */
>;
};
usb1_pins: pinmux_usb1_pins {
pinctrl-single,pins = <
DM814X_IOPAD(0x0834, PIN_OUTPUT | 0x80) /* USB1_DRVVBUS */
>;
};
gpio1_pins: pinmux_gpio1_pins {
pinctrl-single,pins = <
DM814X_IOPAD(0x081c, PIN_OUTPUT | 0x80) /* PROGRAM_B */
DM814X_IOPAD(0x0820, PIN_INPUT | 0x80) /* INIT_B */
DM814X_IOPAD(0x0824, PIN_INPUT | 0x80) /* DONE */
DM814X_IOPAD(0x0838, PIN_INPUT_PULLUP | 0x80) /* FMCA_TMS */
DM814X_IOPAD(0x083c, PIN_INPUT_PULLUP | 0x80) /* FMCA_TCK */
DM814X_IOPAD(0x0898, PIN_INPUT_PULLUP | 0x80) /* FMCA_TDO */
DM814X_IOPAD(0x089c, PIN_INPUT_PULLUP | 0x80) /* FMCA_TDI */
DM814X_IOPAD(0x08ac, PIN_INPUT_PULLUP | 0x80) /* FMCA_TRST */
DM814X_IOPAD(0x08b0, PIN_INPUT_PULLUP | 0x80) /* FMCB_TMS */
DM814X_IOPAD(0x0a88, PIN_INPUT_PULLUP | 0x80) /* FMCB_TCK */
DM814X_IOPAD(0x0a8c, PIN_INPUT_PULLUP | 0x80) /* FMCB_TDO */
DM814X_IOPAD(0x08bc, PIN_INPUT_PULLUP | 0x80) /* FMCB_TDI */
DM814X_IOPAD(0x0a94, PIN_INPUT_PULLUP | 0x80) /* FMCB_TRST */
DM814X_IOPAD(0x08d4, PIN_INPUT_PULLUP | 0x80) /* FPGA_TMS */
DM814X_IOPAD(0x0aa8, PIN_INPUT_PULLUP | 0x80) /* FPGA_TCK */
DM814X_IOPAD(0x0adc, PIN_INPUT_PULLUP | 0x80) /* FPGA_TDO */
DM814X_IOPAD(0x0ab0, PIN_INPUT_PULLUP | 0x80) /* FPGA_TDI */
>;
};
gpio2_pins: pinmux_gpio2_pins {
pinctrl-single,pins = <
DM814X_IOPAD(0x090c, PIN_INPUT_PULLUP | 0x80) /* PHY A IRQ */
DM814X_IOPAD(0x0910, PIN_INPUT_PULLUP | 0x80) /* PHY A RESET */
DM814X_IOPAD(0x08f4, PIN_INPUT_PULLUP | 0x80) /* PHY B IRQ */
DM814X_IOPAD(0x08f8, PIN_INPUT_PULLUP | 0x80) /* PHY B RESET */
//DM814X_IOPAD(0x0a14, PIN_INPUT_PULLUP | 0x80) /* ARM IRQ */
//DM814X_IOPAD(0x0900, PIN_INPUT | 0x80) /* GPIO IRQ */
DM814X_IOPAD(0x0a2c, PIN_INPUT_PULLUP | 0x80) /* GPIO RESET */
>;
};
gpio4_pins: pinmux_gpio4_pins {
pinctrl-single,pins = <
/* The PLL doesn't react well to the SPI controller reset, so
* we force the CS lines to pull up as GPIOs until we're ready.
* See https://e2e.ti.com/support/processors/f/791/t/276011?Linux-support-for-AM3874-DM8148-in-Arago-linux-omap3
*/
DM814X_IOPAD(0x0b3c, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO0 */
DM814X_IOPAD(0x0b40, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO1 */
DM814X_IOPAD(0x0b44, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO2 */
DM814X_IOPAD(0x0b48, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO3 */
DM814X_IOPAD(0x0b4c, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO4 */
DM814X_IOPAD(0x0b50, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO5 */
>;
};
spi2_pins: pinmux_spi2_pins {
pinctrl-single,pins = <
DM814X_IOPAD(0x0950, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS1 as GPIO */
DM814X_IOPAD(0x0818, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS2 as GPIO */
>;
};
spi4_pins: pinmux_spi4_pins {
pinctrl-single,pins = <
DM814X_IOPAD(0x0a7c, 0x20)
DM814X_IOPAD(0x0b74, 0x20)
DM814X_IOPAD(0x0b78, PIN_OUTPUT | 0x20)
DM814X_IOPAD(0x0b7c, PIN_OUTPUT_PULLDOWN | 0x20)
DM814X_IOPAD(0x0b80, PIN_INPUT | 0x20)
>;
};
};
&gpio1 {
pinctrl-names = "default";
pinctrl-0 = <&gpio1_pins>;
gpio-line-names =
"", "PROGRAM_B", "INIT_B", "DONE", /* 0-3 */
"", "", "", "", /* 4-7 */
"FMCA_TMS", "FMCA_TCK", "FMCA_TDO", "FMCA_TDI", /* 8-11 */
"", "", "", "FMCA_TRST", /* 12-15 */
"FMCB_TMS", "FMCB_TCK", "FMCB_TDO", "FMCB_TDI", /* 16-19 */
"FMCB_TRST", "", "", "", /* 20-23 */
"FPGA_TMS", "FPGA_TCK", "FPGA_TDO", "FPGA_TDI", /* 24-27 */
"", "", "", ""; /* 28-31 */
};
&gpio2 {
pinctrl-names = "default";
pinctrl-0 = <&gpio2_pins>;
gpio-line-names =
"PHYA_IRQ_N", "PHYA_RESET_N", "", "", /* 0-3 */
"", "", "", "PHYB_IRQ_N", /* 4-7 */
"PHYB_RESET_N", "ARM_IRQ", "GPIO_IRQ", ""; /* 8-11 */
};
&gpio3 {
pinctrl-names = "default";
/*pinctrl-0 = <&gpio3_pins>;*/
gpio-line-names =
"", "", "ARMClkSel0", "", /* 0-3 */
"EnFPGARef", "", "", "ARMClkSel1"; /* 4-7 */
};
&gpio4 {
pinctrl-names = "default";
pinctrl-0 = <&gpio4_pins>;
gpio-line-names =
"BP_ARM_GPIO0", "BP_ARM_GPIO1", "BP_ARM_GPIO2", "BP_ARM_GPIO3",
"BP_ARM_GPIO4", "BP_ARM_GPIO5";
};
&usb0 {
pinctrl-names = "default";
pinctrl-0 = <&usb0_pins>;
dr_mode = "host";
};
&usb1 {
pinctrl-names = "default";
pinctrl-0 = <&usb1_pins>;
dr_mode = "host";
};
&mcspi1 {
s25fl256@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
fsbl@0 {
/* 256 kB */
label = "U-Boot-min";
reg = <0 0x40000>;
};
ssbl@1 {
/* 512 kB */
label = "U-Boot";
reg = <0x40000 0x80000>;
};
bootenv@2 {
/* 256 kB */
label = "U-Boot Env";
reg = <0xc0000 0x40000>;
};
kernel@3 {
/* 4 MB */
label = "Kernel";
reg = <0x100000 0x400000>;
};
ipmi@4 {
label = "IPMI FRU";
reg = <0x500000 0x40000>;
};
fs@5 {
label = "File System";
reg = <0x540000 0x1ac0000>;
};
};
};
&mcspi3 {
/* DMA event numbers stolen from MCASP */
dmas = <&edma_xbar 8 0 16 &edma_xbar 9 0 17
&edma_xbar 10 0 18 &edma_xbar 11 0 19>;
dma-names = "tx0", "rx0", "tx1", "rx1";
};
&mcspi4 {
pinctrl-names = "default";
pinctrl-0 = <&spi4_pins>;
/* DMA event numbers stolen from MCASP, MCBSP */
dmas = <&edma_xbar 12 0 20 &edma_xbar 13 0 21>;
dma-names = "tx0", "rx0";
};

2
sys/gnu/dts/arm/am437x-gp-evm.dts
View File

@ -71,7 +71,7 @@
pinctrl-0 = <&matrix_keypad_default>;
pinctrl-1 = <&matrix_keypad_sleep>;
linux,wakeup;
wakeup-source;
row-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH /* Bank0, pin3 */
&gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */

17
sys/gnu/dts/arm/am437x-l4.dtsi
View File

@ -280,12 +280,6 @@
#size-cells = <1>;
ranges = <0 0 0x4000>;
phy_sel: cpsw-phy-sel@650 {
compatible = "ti,am43xx-cpsw-phy-sel";
reg= <0x650 0x4>;
reg-names = "gmii-sel";
};
am43xx_pinmux: pinmux@800 {
compatible = "ti,am437-padconf",
"pinctrl-single";
@ -300,11 +294,17 @@
};
scm_conf: scm_conf@0 {
compatible = "syscon";
compatible = "syscon", "simple-bus";
reg = <0x0 0x800>;
#address-cells = <1>;
#size-cells = <1>;
phy_gmii_sel: phy-gmii-sel {
compatible = "ti,am43xx-phy-gmii-sel";
reg = <0x650 0x4>;
#phy-cells = <2>;
};
scm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
@ -555,7 +555,6 @@
cpts_clock_shift = <29>;
ranges = <0 0 0x8000>;
syscon = <&scm_conf>;
cpsw-phy-sel = <&phy_sel>;
davinci_mdio: mdio@1000 {
compatible = "ti,am4372-mdio","ti,cpsw-mdio","ti,davinci_mdio";
@ -572,11 +571,13 @@
cpsw_emac0: slave@200 {
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
phys = <&phy_gmii_sel 1 0>;
};
cpsw_emac1: slave@300 {
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
phys = <&phy_gmii_sel 2 0>;
};
};
};

5
sys/gnu/dts/arm/am43x-epos-evm.dts
View File

@ -584,10 +584,7 @@
&cpsw_emac0 {
phy-handle = <&ethphy0>;
phy-mode = "rmii";
};
&phy_sel {
rmii-clock-ext;
phys = <&phy_gmii_sel 1 1>;
};
&i2c0 {

4
sys/gnu/dts/arm/arm-realview-eb.dtsi
View File

@ -22,9 +22,10 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include "skeleton.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "arm,realview-eb";
chosen { };
@ -38,6 +39,7 @@
};
memory {
device_type = "memory";
/* 128 MiB memory @ 0x0 */
reg = <0x00000000 0x08000000>;
};

4
sys/gnu/dts/arm/arm-realview-pb1176.dts
View File

@ -23,9 +23,10 @@
/dts-v1/;
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include "skeleton.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "ARM RealView PB1176";
compatible = "arm,realview-pb1176";
@ -40,6 +41,7 @@
};
memory {
device_type = "memory";
/* 128 MiB memory @ 0x0 */
reg = <0x00000000 0x08000000>;
};

4
sys/gnu/dts/arm/arm-realview-pb11mp.dts
View File

@ -23,9 +23,10 @@
/dts-v1/;
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include "skeleton.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "ARM RealView PB11MPcore";
compatible = "arm,realview-pb11mp";
@ -39,6 +40,7 @@
};
memory {
device_type = "memory";
/*
* The PB11MPCore has 512 MiB memory @ 0x70000000
* and the first 256 are also remapped @ 0x00000000

4
sys/gnu/dts/arm/arm-realview-pbx.dtsi
View File

@ -22,9 +22,10 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include "skeleton.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "arm,realview-pbx";
chosen { };
@ -39,6 +40,7 @@
};
memory {
device_type = "memory";
/* 128 MiB memory @ 0x0 */
reg = <0x00000000 0x08000000>;
};

42
sys/gnu/dts/arm/armada-370-rd.dts
View File

@ -114,48 +114,6 @@
};
};
};
dsa {
status = "disabled";
compatible = "marvell,dsa";
#address-cells = <2>;
#size-cells = <0>;
dsa,ethernet = <&eth1>;
dsa,mii-bus = <&mdio>;
switch@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10 0>; /* MDIO address 16, switch 0 in tree */
port@0 {
reg = <0>;
label = "lan0";
};
port@1 {
reg = <1>;
label = "lan1";
};
port@2 {
reg = <2>;
label = "lan2";
};
port@3 {
reg = <3>;
label = "lan3";
};
port@5 {
reg = <5>;
label = "cpu";
};
};
};
};
&pciec {

58
sys/gnu/dts/arm/armada-388-clearfog.dts
View File

@ -30,64 +30,6 @@
};
};
dsa@0 {
status = "disabled";
compatible = "marvell,dsa";
dsa,ethernet = <&eth1>;
dsa,mii-bus = <&mdio>;
pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
pinctrl-names = "default";
#address-cells = <2>;
#size-cells = <0>;
switch@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4 0>;
port@0 {
reg = <0>;
label = "lan5";
};
port@1 {
reg = <1>;
label = "lan4";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan2";
};
port@4 {
reg = <4>;
label = "lan1";
};
port@5 {
reg = <5>;
label = "cpu";
};
port@6 {
/* 88E1512 external phy */
reg = <6>;
label = "lan6";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&rear_button_pins>;

2
sys/gnu/dts/arm/armada-388-clearfog.dtsi
View File

@ -93,6 +93,7 @@
bm,pool-long = <2>;
bm,pool-short = <1>;
buffer-manager = <&bm>;
phys = <&comphy1 1>;
phy-mode = "sgmii";
status = "okay";
};
@ -103,6 +104,7 @@
bm,pool-short = <1>;
buffer-manager = <&bm>;
managed = "in-band-status";
phys = <&comphy5 2>;
phy-mode = "sgmii";
sfp = <&sfp>;
status = "okay";

41
sys/gnu/dts/arm/armada-38x.dtsi
View File

@ -9,13 +9,15 @@
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*/
#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "Marvell Armada 38x family SoC";
compatible = "marvell,armada380";
@ -335,6 +337,43 @@
#clock-cells = <1>;
};
comphy: phy@18300 {
compatible = "marvell,armada-380-comphy";
reg = <0x18300 0x100>;
#address-cells = <1>;
#size-cells = <0>;
comphy0: phy@0 {
reg = <0>;
#phy-cells = <1>;
};
comphy1: phy@1 {
reg = <1>;
#phy-cells = <1>;
};
comphy2: phy@2 {
reg = <2>;
#phy-cells = <1>;
};
comphy3: phy@3 {
reg = <3>;
#phy-cells = <1>;
};
comphy4: phy@4 {
reg = <4>;
#phy-cells = <1>;
};
comphy5: phy@5 {
reg = <5>;
#phy-cells = <1>;
};
};
coreclk: mvebu-sar@18600 {
compatible = "marvell,armada-380-core-clock";
reg = <0x18600 0x04>;

3
sys/gnu/dts/arm/armada-39x.dtsi
View File

@ -7,13 +7,14 @@
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*/
#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "Marvell Armada 39x family SoC";
compatible = "marvell,armada390";

47
sys/gnu/dts/arm/armada-xp-linksys-mamba.dts
View File

@ -210,53 +210,6 @@
compatible = "pwm-fan";
pwms = <&gpio0 24 4000>;
};
dsa {
status = "disabled";
compatible = "marvell,dsa";
#address-cells = <2>;
#size-cells = <0>;
dsa,ethernet = <&eth0>;
dsa,mii-bus = <&mdio>;
switch@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0>; /* MDIO address 0, switch 0 in tree */
port@0 {
reg = <0>;
label = "lan4";
};
port@1 {
reg = <1>;
label = "lan3";
};
port@2 {
reg = <2>;
label = "lan2";
};
port@3 {
reg = <3>;
label = "lan1";
};
port@4 {
reg = <4>;
label = "internet";
};
port@5 {
reg = <5>;
label = "cpu";
};
};
};
};
&pciec {

3
sys/gnu/dts/arm/artpec6.dtsi
View File

@ -43,9 +43,10 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/dma/nbpfaxi.h>
#include <dt-bindings/clock/axis,artpec6-clkctrl.h>
#include "skeleton.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "axis,artpec6";
interrupt-parent = <&intc>;

10
sys/gnu/dts/arm/aspeed-bmc-arm-stardragon4800-rep2.dts
View File

@ -173,6 +173,16 @@
};
};
};
dps650ab@58 {
compatible = "delta,dps650ab";
reg = <0x58>;
};
dps650ab@59 {
compatible = "delta,dps650ab";
reg = <0x59>;
};
};
&i2c9 {

55
sys/gnu/dts/arm/aspeed-bmc-facebook-tiogapass.dts
View File

@ -21,6 +21,17 @@
memory@80000000 {
reg = <0x80000000 0x20000000>;
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
<&adc 4>, <&adc 5>, <&adc 6>;
};
iio-hwmon-battery {
compatible = "iio-hwmon";
io-channels = <&adc 7>;
};
};
&fmc {
@ -43,6 +54,16 @@
};
};
&lpc_snoop {
status = "okay";
snoop-ports = <0x80>;
};
&lpc_ctrl {
// Enable lpc clock
status = "okay";
};
&uart1 {
// Host Console
status = "okay";
@ -51,11 +72,33 @@
&pinctrl_rxd1_default>;
};
&uart2 {
// SoL Host Console
status = "okay";
};
&uart3 {
// SoL BMC Console
status = "okay";
};
&uart5 {
// BMC Console
status = "okay";
};
&kcs2 {
// BMC KCS channel 2
status = "okay";
kcs_addr = <0xca8>;
};
&kcs3 {
// BMC KCS channel 3
status = "okay";
kcs_addr = <0xca2>;
};
&mac0 {
status = "okay";
@ -64,6 +107,10 @@
use-ncsi;
};
&adc {
status = "okay";
};
&i2c0 {
status = "okay";
//Airmax Conn B, CPU0 PIROM, CPU1 PIROM
@ -122,6 +169,10 @@
&i2c8 {
status = "okay";
tmp421@1f {
compatible = "ti,tmp421";
reg = <0x1f>;
};
//Mezz Sensor SMBus
};
@ -140,7 +191,7 @@
};
fan@1 {
reg = <0x00>;
aspeed,fan-tach-ch = /bits/ 8 <0x01>;
reg = <0x01>;
aspeed,fan-tach-ch = /bits/ 8 <0x02>;
};
};

145
sys/gnu/dts/arm/aspeed-bmc-inspur-on5263m5.dts Normal file
View File

@ -0,0 +1,145 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018 Inspur Corporation
/dts-v1/;
#include "aspeed-g5.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
/ {
model = "ON5263M5 BMC";
compatible = "inspur,on5263m5-bmc", "aspeed,ast2500";
chosen {
stdout-path = &uart5;
bootargs = "earlyprintk";
};
memory {
reg = <0x80000000 0x20000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
vga_memory: framebuffer@9f000000 {
no-map;
reg = <0x9f000000 0x01000000>;
};
};
leds {
compatible = "gpio-leds";
bmc_alive {
label = "bmc_alive";
gpios = <&gpio ASPEED_GPIO(I, 1) GPIO_ACTIVE_LOW>;
linux,default-trigger = "timer";
};
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
<&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>;
};
};
&fmc {
status = "okay";
flash@0 {
status = "okay";
m25p,fast-read;
label = "bmc";
#include "openbmc-flash-layout.dtsi"
};
};
&spi1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1_default>;
flash@0 {
status = "okay";
m25p,fast-read;
label = "pnor";
};
};
&uart5 {
status = "okay";
};
&mac0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
use-ncsi;
};
&mac1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
};
&i2c6 {
status = "okay";
tmp421@4e {
compatible = "ti,tmp421";
reg = <0x4e>;
};
tmp112@48 {
compatible = "ti,tmp112";
reg = <0x48>;
};
eeprom@54 {
compatible = "atmel,24c64";
reg = <0x54>;
pagesize = <32>;
};
};
&i2c7 {
status = "okay";
adm1278@11 {
compatible = "adi,adm1278";
reg = <0x11>;
};
};
&gfx {
status = "okay";
};
&pinctrl {
aspeed,external-nodes = <&gfx &lhc>;
};
&pwm_tacho {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>;
fan@0 {
reg = <0x00>;
aspeed,fan-tach-ch = /bits/ 8 <0x00 0x01>;
};
fan@1 {
reg = <0x01>;
aspeed,fan-tach-ch = /bits/ 8 <0x02 0x03>;
};
};
&adc {
status = "okay";
};

5
sys/gnu/dts/arm/aspeed-bmc-opp-palmetto.dts
View File

@ -169,6 +169,11 @@
&i2c3 {
status = "okay";
occ-hwmon@50 {
compatible = "ibm,p8-occ-hwmon";
reg = <0x50>;
};
};
&i2c4 {

8
sys/gnu/dts/arm/aspeed-bmc-quanta-q71l.dts
View File

@ -116,6 +116,10 @@
status = "okay";
};
&lpc_ctrl {
status = "okay";
};
&lpc_snoop {
status = "okay";
snoop-ports = <0x80>;
@ -134,6 +138,10 @@
pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
};
&uart1 {
status = "okay";
};
&uart5 {
status = "okay";
};

1
sys/gnu/dts/arm/aspeed-g4.dtsi
View File

@ -197,6 +197,7 @@
gpio-ranges = <&pinctrl 0 0 220>;
clocks = <&syscon ASPEED_CLK_APB>;
interrupt-controller;
#interrupt-cells = <2>;
};
timer: timer@1e782000 {

41
sys/gnu/dts/arm/aspeed-g5.dtsi
View File

@ -47,6 +47,13 @@
reg = <0x80000000 0>;
};
edac: sdram@1e6e0000 {
compatible = "aspeed,ast2500-sdram-edac";
reg = <0x1e6e0000 0x174>;
interrupts = <0>;
status = "disabled";
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;
@ -250,6 +257,7 @@
gpio-ranges = <&pinctrl 0 0 220>;
clocks = <&syscon ASPEED_CLK_APB>;
interrupt-controller;
#interrupt-cells = <2>;
};
timer: timer@1e782000 {
@ -330,8 +338,32 @@
ranges = <0x0 0x1e789000 0x1000>;
lpc_bmc: lpc-bmc@0 {
compatible = "aspeed,ast2500-lpc-bmc";
compatible = "aspeed,ast2500-lpc-bmc", "simple-mfd", "syscon";
reg = <0x0 0x80>;
reg-io-width = <4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x80>;
kcs1: kcs1@0 {
compatible = "aspeed,ast2500-kcs-bmc";
interrupts = <8>;
kcs_chan = <1>;
status = "disabled";
};
kcs2: kcs2@0 {
compatible = "aspeed,ast2500-kcs-bmc";
interrupts = <8>;
kcs_chan = <2>;
status = "disabled";
};
kcs3: kcs3@0 {
compatible = "aspeed,ast2500-kcs-bmc";
interrupts = <8>;
kcs_chan = <3>;
status = "disabled";
};
};
lpc_host: lpc-host@80 {
@ -343,6 +375,13 @@
#size-cells = <1>;
ranges = <0x0 0x80 0x1e0>;
kcs4: kcs4@0 {
compatible = "aspeed,ast2500-kcs-bmc";
interrupts = <8>;
kcs_chan = <4>;
status = "disabled";
};
lpc_ctrl: lpc-ctrl@0 {
compatible = "aspeed,ast2500-lpc-ctrl";
reg = <0x0 0x80>;

2
sys/gnu/dts/arm/at91-nattis-2-natte-2.dts
View File

@ -22,7 +22,7 @@
wakeup {
label = "Wakeup";
linux,code = <10>;
gpio-key,wakeup;
wakeup-source;
gpios = <&pioB 27 GPIO_ACTIVE_LOW>;
};
};

30
sys/gnu/dts/arm/at91-sama5d27_som1.dtsi
View File

@ -62,6 +62,20 @@
ahb {
apb {
qspi1: spi@f0024000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi1_default>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <80000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
m25p,fast-read;
};
};
macb0: ethernet@f8008000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_default>;
@ -78,6 +92,22 @@
pinctrl@fc038000 {
pinctrl_qspi1_default: qspi1_default {
sck_cs {
pinmux = <PIN_PB5__QSPI1_SCK>,
<PIN_PB6__QSPI1_CS>;
bias-disable;
};
data {
pinmux = <PIN_PB7__QSPI1_IO0>,
<PIN_PB8__QSPI1_IO1>,
<PIN_PB9__QSPI1_IO2>,
<PIN_PB10__QSPI1_IO3>;
bias-pull-up;
};
};
pinctrl_macb0_default: macb0_default {
pinmux = <PIN_PD9__GTXCK>,
<PIN_PD10__GTXEN>,

4
sys/gnu/dts/arm/at91-sama5d27_som1_ek.dts
View File

@ -109,6 +109,10 @@
status = "okay";
};
qspi1: spi@f0024000 {
status = "okay";
};
spi0: spi@f8000000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0_default>;

2
sys/gnu/dts/arm/at91-wb45n.dts
View File

@ -22,7 +22,7 @@
label = "IRQBTN";
linux,code = <99>;
gpios = <&pioB 18 GPIO_ACTIVE_LOW>;
gpio-key,wakeup = <1>;
wakeup-source;
};
};
};

4
sys/gnu/dts/arm/at91-wb50n.dts
View File

@ -23,7 +23,7 @@
label = "BTNESC";
linux,code = <1>; /* ESC button */
gpios = <&pioA 10 GPIO_ACTIVE_LOW>;
gpio-key,wakeup = <1>;
wakeup-source;
};
irqbtn@31 {
@ -31,7 +31,7 @@
label = "IRQBTN";
linux,code = <99>; /* SysReq button */
gpios = <&pioE 31 GPIO_ACTIVE_LOW>;
gpio-key,wakeup = <1>;
wakeup-source;
};
};

4
sys/gnu/dts/arm/at91rm9200.dtsi
View File

@ -10,13 +10,14 @@
* Licensed under GPLv2 or later.
*/
#include "skeleton.dtsi"
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/at91.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "Atmel AT91RM9200 family SoC";
compatible = "atmel,at91rm9200";
interrupt-parent = <&aic>;
@ -49,6 +50,7 @@
};
memory {
device_type = "memory";
reg = <0x20000000 0x04000000>;
};

4
sys/gnu/dts/arm/at91sam9260.dtsi
View File

@ -8,13 +8,14 @@
* Licensed under GPLv2 or later.
*/
#include "skeleton.dtsi"
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/at91.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "Atmel AT91SAM9260 family SoC";
compatible = "atmel,at91sam9260";
interrupt-parent = <&aic>;
@ -46,6 +47,7 @@
};
memory {
device_type = "memory";
reg = <0x20000000 0x04000000>;
};

4
sys/gnu/dts/arm/at91sam9261.dtsi
View File

@ -6,13 +6,14 @@
* Licensed under GPLv2 only.
*/
#include "skeleton.dtsi"
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/at91.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "Atmel AT91SAM9261 family SoC";
compatible = "atmel,at91sam9261";
interrupt-parent = <&aic>;
@ -43,6 +44,7 @@
};
memory {
device_type = "memory";
reg = <0x20000000 0x08000000>;
};

4
sys/gnu/dts/arm/at91sam9263.dtsi
View File

@ -6,13 +6,14 @@
* Licensed under GPLv2 only.
*/
#include "skeleton.dtsi"
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/at91.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "Atmel AT91SAM9263 family SoC";
compatible = "atmel,at91sam9263";
interrupt-parent = <&aic>;
@ -45,6 +46,7 @@
};
memory {
device_type = "memory";
reg = <0x20000000 0x08000000>;
};

4
sys/gnu/dts/arm/at91sam9g45.dtsi
View File

@ -9,7 +9,6 @@
* Licensed under GPLv2 or later.
*/
#include "skeleton.dtsi"
#include <dt-bindings/dma/at91.h>
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
@ -17,6 +16,8 @@
#include <dt-bindings/clock/at91.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "Atmel AT91SAM9G45 family SoC";
compatible = "atmel,at91sam9g45";
interrupt-parent = <&aic>;
@ -51,6 +52,7 @@
};
memory {
device_type = "memory";
reg = <0x70000000 0x10000000>;
};

4
sys/gnu/dts/arm/at91sam9n12.dtsi
View File

@ -7,7 +7,6 @@
* Licensed under GPLv2 or later.
*/
#include "skeleton.dtsi"
#include <dt-bindings/dma/at91.h>
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
@ -15,6 +14,8 @@
#include <dt-bindings/clock/at91.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "Atmel AT91SAM9N12 SoC";
compatible = "atmel,at91sam9n12";
interrupt-parent = <&aic>;
@ -47,6 +48,7 @@
};
memory {
device_type = "memory";
reg = <0x20000000 0x10000000>;
};

4
sys/gnu/dts/arm/at91sam9rl.dtsi
View File

@ -7,7 +7,6 @@
* Licensed under GPLv2 or later.
*/
#include "skeleton.dtsi"
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/clock/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
@ -15,6 +14,8 @@
#include <dt-bindings/pwm/pwm.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "Atmel AT91SAM9RL family SoC";
compatible = "atmel,at91sam9rl", "atmel,at91sam9";
interrupt-parent = <&aic>;
@ -48,6 +49,7 @@
};
memory {
device_type = "memory";
reg = <0x20000000 0x04000000>;
};

4
sys/gnu/dts/arm/at91sam9x5.dtsi
View File

@ -9,7 +9,6 @@
* Licensed under GPLv2 or later.
*/
#include "skeleton.dtsi"
#include <dt-bindings/dma/at91.h>
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
@ -17,6 +16,8 @@
#include <dt-bindings/clock/at91.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "Atmel AT91SAM9x5 family SoC";
compatible = "atmel,at91sam9x5";
interrupt-parent = <&aic>;
@ -49,6 +50,7 @@
};
memory {
device_type = "memory";
reg = <0x20000000 0x10000000>;
};

1
sys/gnu/dts/arm/atlas6-evb.dts
View File

@ -15,6 +15,7 @@
compatible = "sirf,atlas6-cb", "sirf,atlas6";
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>;
};

1
sys/gnu/dts/arm/atlas6.dtsi
View File

@ -6,7 +6,6 @@
* Licensed under GPLv2 or later.
*/
/include/ "skeleton.dtsi"
/ {
compatible = "sirf,atlas6";
#address-cells = <1>;

1
sys/gnu/dts/arm/atlas7.dtsi
View File

@ -6,7 +6,6 @@
* Licensed under GPLv2 or later.
*/
/include/ "skeleton.dtsi"
/ {
compatible = "sirf,atlas7";
#address-cells = <1>;

4
sys/gnu/dts/arm/axm55xx.dtsi
View File

@ -12,9 +12,9 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/lsi,axm5516-clks.h>
#include "skeleton64.dtsi"
/ {
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
aliases {

9
sys/gnu/dts/arm/bcm-cygnus.dtsi
View File

@ -34,9 +34,9 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/bcm-cygnus.h>
#include "skeleton.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "brcm,cygnus";
model = "Broadcom Cygnus SoC";
interrupt-parent = <&gic>;
@ -45,6 +45,11 @@
ethernet0 = &eth0;
};
memory {
device_type = "memory";
reg = <0 0>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;

4
sys/gnu/dts/arm/bcm-nsp.dtsi
View File

@ -34,9 +34,9 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/bcm-nsp.h>
#include "skeleton.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "brcm,nsp";
model = "Broadcom Northstar Plus SoC";
interrupt-parent = <&gic>;

4
sys/gnu/dts/arm/bcm11351.dtsi
View File

@ -16,9 +16,9 @@
#include "dt-bindings/clock/bcm281xx.h"
#include "skeleton.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "BCM11351 SoC";
compatible = "brcm,bcm11351";
interrupt-parent = <&gic>;

1
sys/gnu/dts/arm/bcm21664-garnet.dts
View File

@ -22,6 +22,7 @@
compatible = "brcm,bcm21664-garnet", "brcm,bcm21664";
memory {
device_type = "memory";
reg = <0x80000000 0x40000000>; /* 1 GB */
};

4
sys/gnu/dts/arm/bcm21664.dtsi
View File

@ -16,9 +16,9 @@
#include "dt-bindings/clock/bcm21664.h"
#include "skeleton.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "BCM21664 SoC";
compatible = "brcm,bcm21664";
interrupt-parent = <&gic>;

1
sys/gnu/dts/arm/bcm23550-sparrow.dts
View File

@ -46,6 +46,7 @@
};
memory {
device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512 MB */
};
};

4
sys/gnu/dts/arm/bcm23550.dtsi
View File

@ -36,9 +36,9 @@
/* BCM23550 and BCM21664 have almost identical clocks */
#include "dt-bindings/clock/bcm21664.h"
#include "skeleton.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "BCM23550 SoC";
compatible = "brcm,bcm23550";
interrupt-parent = <&gic>;

1
sys/gnu/dts/arm/bcm28155-ap.dts
View File

@ -22,6 +22,7 @@
compatible = "brcm,bcm28155-ap", "brcm,bcm11351";
memory {
device_type = "memory";
reg = <0x80000000 0x40000000>; /* 1 GB */
};

4
sys/gnu/dts/arm/bcm2835-rpi-a-plus.dts
View File

@ -31,8 +31,8 @@
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
gpio-line-names = "SDA0",
"SCL0",
gpio-line-names = "ID_SDA",
"ID_SCL",
"SDA1",
"SCL1",
"GPIO_GCLK",

4
sys/gnu/dts/arm/bcm2835-rpi-b-plus.dts
View File

@ -33,8 +33,8 @@
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
gpio-line-names = "SDA0",
"SCL0",
gpio-line-names = "ID_SDA",
"ID_SCL",
"SDA1",
"SCL1",
"GPIO_GCLK",

2
sys/gnu/dts/arm/bcm2835-rpi-b-rev2.dts
View File

@ -93,7 +93,7 @@
};
&hdmi {
hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
};
&pwm {

11
sys/gnu/dts/arm/bcm2835-rpi-zero-w.dts
View File

@ -25,8 +25,6 @@
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&wl_on>;
reset-gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
};
};
@ -40,8 +38,8 @@
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
gpio-line-names = "GPIO0",
"GPIO1",
gpio-line-names = "ID_SDA",
"ID_SCL",
"SDA1",
"SCL1",
"GPIO_GCLK",
@ -98,11 +96,6 @@
"SD_DATA3_R";
pinctrl-0 = <&gpioout &alt0>;
wl_on: wl-on {
brcm,pins = <41>;
brcm,function = <BCM2835_FSEL_GPIO_OUT>;
};
};
&hdmi {

4
sys/gnu/dts/arm/bcm2835-rpi-zero.dts
View File

@ -28,8 +28,8 @@
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
gpio-line-names = "SDA0",
"SCL0",
gpio-line-names = "ID_SDA",
"ID_SCL",
"SDA1",
"SCL1",
"GPIO_GCLK",

8
sys/gnu/dts/arm/bcm2835-rpi.dtsi
View File

@ -1,7 +1,7 @@
#include <dt-bindings/power/raspberrypi-power.h>
/ {
memory {
memory@0 {
device_type = "memory";
reg = <0 0x10000000>;
};
@ -19,8 +19,6 @@
soc {
firmware: firmware {
compatible = "raspberrypi,bcm2835-firmware", "simple-bus";
#address-cells = <0>;
#size-cells = <0>;
mboxes = <&mailbox>;
};
@ -87,10 +85,6 @@
power-domains = <&power RPI_POWER_DOMAIN_USB>;
};
&v3d {
power-domains = <&power RPI_POWER_DOMAIN_V3D>;
};
&hdmi {
power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
status = "okay";

68
sys/gnu/dts/arm/bcm2836-rpi-2-b.dts
View File

@ -9,7 +9,7 @@
compatible = "raspberrypi,2-model-b", "brcm,bcm2836";
model = "Raspberry Pi 2 Model B";
memory {
memory@0 {
reg = <0 0x40000000>;
};
@ -28,6 +28,72 @@
};
&gpio {
/*
* Taken from rpi_SCH_2b_1p2_reduced.pdf and
* the official GPU firmware DT blob.
*
* Legend:
* "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
gpio-line-names = "ID_SDA",
"ID_SCL",
"SDA1",
"SCL1",
"GPIO_GCLK",
"GPIO5",
"GPIO6",
"SPI_CE1_N",
"SPI_CE0_N",
"SPI_MISO",
"SPI_MOSI",
"SPI_SCLK",
"GPIO12",
"GPIO13",
/* Serial port */
"TXD0",
"RXD0",
"GPIO16",
"GPIO17",
"GPIO18",
"GPIO19",
"GPIO20",
"GPIO21",
"GPIO22",
"GPIO23",
"GPIO24",
"GPIO25",
"GPIO26",
"GPIO27",
"SDA0",
"SCL0",
"", /* GPIO30 */
"LAN_RUN",
"CAM_GPIO1",
"", /* GPIO33 */
"", /* GPIO34 */
"PWR_LOW_N",
"", /* GPIO36 */
"", /* GPIO37 */
"USB_LIMIT",
"", /* GPIO39 */
"PWM0_OUT",
"CAM_GPIO0",
"SMPS_SCL",
"SMPS_SDA",
"ETHCLK",
"PWM1_OUT",
"HDMI_HPD_N",
"STATUS_LED",
/* Used by SD Card */
"SD_CLK_R",
"SD_CMD_R",
"SD_DATA0_R",
"SD_DATA1_R",
"SD_DATA2_R",
"SD_DATA3_R";
pinctrl-0 = <&gpioout &alt0 &i2s_alt0>;
/* I2S interface */

175
sys/gnu/dts/arm/bcm2837-rpi-3-a-plus.dts Normal file
View File

@ -0,0 +1,175 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "bcm2837.dtsi"
#include "bcm2836-rpi.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
/ {
compatible = "raspberrypi,3-model-a-plus", "brcm,bcm2837";
model = "Raspberry Pi 3 Model A+";
chosen {
/* 8250 auxiliary UART instead of pl011 */
stdout-path = "serial1:115200n8";
};
memory@0 {
reg = <0 0x20000000>;
};
leds {
act {
gpios = <&gpio 29 GPIO_ACTIVE_HIGH>;
};
pwr {
label = "PWR";
gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
};
};
};
&firmware {
expgpio: gpio {
compatible = "raspberrypi,firmware-gpio";
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "",
"BT_WL_ON",
"STATUS_LED_R",
"",
"",
"CAM_GPIO0",
"CAM_GPIO1",
"";
status = "okay";
};
};
&gpio {
/*
* This is mostly based on the official GPU firmware DT blob.
*
* Legend:
* "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
gpio-line-names = "ID_SDA",
"ID_SCL",
"SDA1",
"SCL1",
"GPIO_GCLK",
"GPIO5",
"GPIO6",
"SPI_CE1_N",
"SPI_CE0_N",
"SPI_MISO",
"SPI_MOSI",
"SPI_SCLK",
"GPIO12",
"GPIO13",
/* Serial port */
"TXD1",
"RXD1",
"GPIO16",
"GPIO17",
"GPIO18",
"GPIO19",
"GPIO20",
"GPIO21",
"GPIO22",
"GPIO23",
"GPIO24",
"GPIO25",
"GPIO26",
"GPIO27",
"HDMI_HPD_N",
"STATUS_LED_G",
/* Used by BT module */
"CTS0",
"RTS0",
"TXD0",
"RXD0",
/* Used by Wifi */
"SD1_CLK",
"SD1_CMD",
"SD1_DATA0",
"SD1_DATA1",
"SD1_DATA2",
"SD1_DATA3",
"PWM0_OUT",
"PWM1_OUT",
"", /* GPIO42 */
"WIFI_CLK",
"SDA0",
"SCL0",
"SMPS_SCL",
"SMPS_SDA",
/* Used by SD Card */
"SD_CLK_R",
"SD_CMD_R",
"SD_DATA0_R",
"SD_DATA1_R",
"SD_DATA2_R",
"SD_DATA3_R";
};
&hdmi {
hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>;
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>;
status = "okay";
};
/*
* SDHCI is used to control the SDIO for wireless
*
* WL_REG_ON and BT_REG_ON of the CYW43455 Wifi/BT module are driven
* by a single GPIO. We can't give GPIO control to one of the drivers,
* otherwise the other part would get unexpectedly disturbed.
*/
&sdhci {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_gpio34>;
status = "okay";
bus-width = <4>;
non-removable;
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
/* SDHOST is used to drive the SD card */
&sdhost {
pinctrl-names = "default";
pinctrl-0 = <&sdhost_gpio48>;
status = "okay";
bus-width = <4>;
};
/* uart0 communicates with the BT module */
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32 &gpclk2_gpio43>;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
max-speed = <2000000>;
};
};
/* uart1 is mapped to the pin header */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_gpio14>;
status = "okay";
};

74
sys/gnu/dts/arm/bcm2837-rpi-3-b-plus.dts
View File

@ -14,7 +14,7 @@
stdout-path = "serial1:115200n8";
};
memory {
memory@0 {
reg = <0 0x40000000>;
};
@ -42,7 +42,7 @@
#gpio-cells = <2>;
gpio-line-names = "BT_ON",
"WL_ON",
"STATUS_LED",
"STATUS_LED_R",
"LAN_RUN",
"",
"CAM_GPIO0",
@ -52,6 +52,76 @@
};
};
&gpio {
/*
* Taken from rpi_SCH_3bplus_1p0_reduced.pdf and
* the official GPU firmware DT blob.
*
* Legend:
* "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
gpio-line-names = "ID_SDA",
"ID_SCL",
"SDA1",
"SCL1",
"GPIO_GCLK",
"GPIO5",
"GPIO6",
"SPI_CE1_N",
"SPI_CE0_N",
"SPI_MISO",
"SPI_MOSI",
"SPI_SCLK",
"GPIO12",
"GPIO13",
/* Serial port */
"TXD1",
"RXD1",
"GPIO16",
"GPIO17",
"GPIO18",
"GPIO19",
"GPIO20",
"GPIO21",
"GPIO22",
"GPIO23",
"GPIO24",
"GPIO25",
"GPIO26",
"GPIO27",
"HDMI_HPD_N",
"STATUS_LED_G",
/* Used by BT module */
"CTS0",
"RTS0",
"TXD0",
"RXD0",
/* Used by Wifi */
"SD1_CLK",
"SD1_CMD",
"SD1_DATA0",
"SD1_DATA1",
"SD1_DATA2",
"SD1_DATA3",
"PWM0_OUT",
"PWM1_OUT",
"ETHCLK",
"WIFI_CLK",
"SDA0",
"SCL0",
"SMPS_SCL",
"SMPS_SDA",
/* Used by SD Card */
"SD_CLK_R",
"SD_CMD_R",
"SD_DATA0_R",
"SD_DATA1_R",
"SD_DATA2_R",
"SD_DATA3_R";
};
&hdmi {
hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>;
};

74
sys/gnu/dts/arm/bcm2837-rpi-3-b.dts
View File

@ -14,7 +14,7 @@
stdout-path = "serial1:115200n8";
};
memory {
memory@0 {
reg = <0 0x40000000>;
};
@ -39,7 +39,7 @@
"WL_ON",
"STATUS_LED",
"LAN_RUN",
"HPD_N",
"HDMI_HPD_N",
"CAM_GPIO0",
"CAM_GPIO1",
"PWR_LOW_N";
@ -47,6 +47,76 @@
};
};
&gpio {
/*
* Taken from rpi_SCH_3b_1p2_reduced.pdf and
* the official GPU firmware DT blob.
*
* Legend:
* "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
gpio-line-names = "ID_SDA",
"ID_SCL",
"SDA1",
"SCL1",
"GPIO_GCLK",
"GPIO5",
"GPIO6",
"SPI_CE1_N",
"SPI_CE0_N",
"SPI_MISO",
"SPI_MOSI",
"SPI_SCLK",
"GPIO12",
"GPIO13",
/* Serial port */
"TXD1",
"RXD1",
"GPIO16",
"GPIO17",
"GPIO18",
"GPIO19",
"GPIO20",
"GPIO21",
"GPIO22",
"GPIO23",
"GPIO24",
"GPIO25",
"GPIO26",
"GPIO27",
"", /* GPIO 28 */
"LAN_RUN_BOOT",
/* Used by BT module */
"CTS0",
"RTS0",
"TXD0",
"RXD0",
/* Used by Wifi */
"SD1_CLK",
"SD1_CMD",
"SD1_DATA0",
"SD1_DATA1",
"SD1_DATA2",
"SD1_DATA3",
"PWM0_OUT",
"PWM1_OUT",
"ETHCLK",
"WIFI_CLK",
"SDA0",
"SCL0",
"SMPS_SCL",
"SMPS_SDA",
/* Used by SD Card */
"SD_CLK_R",
"SD_CMD_R",
"SD_DATA0_R",
"SD_DATA1_R",
"SD_DATA2_R",
"SD_DATA3_R";
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>;

2
sys/gnu/dts/arm/bcm2837-rpi-cm3.dtsi
View File

@ -4,7 +4,7 @@
#include "bcm2836-rpi.dtsi"
/ {
memory {
memory@0 {
reg = <0 0x40000000>;
};

17
sys/gnu/dts/arm/bcm283x.dtsi
View File

@ -3,6 +3,7 @@
#include <dt-bindings/clock/bcm2835-aux.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/soc/bcm2835-pm.h>
/* firmware-provided startup stubs live here, where the secondary CPUs are
* spinning.
@ -120,9 +121,18 @@
#interrupt-cells = <2>;
};
watchdog@7e100000 {
compatible = "brcm,bcm2835-pm-wdt";
reg = <0x7e100000 0x28>;
pm: watchdog@7e100000 {
compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
#power-domain-cells = <1>;
#reset-cells = <1>;
reg = <0x7e100000 0x114>,
<0x7e00a000 0x24>;
clocks = <&clocks BCM2835_CLOCK_V3D>,
<&clocks BCM2835_CLOCK_PERI_IMAGE>,
<&clocks BCM2835_CLOCK_H264>,
<&clocks BCM2835_CLOCK_ISP>;
clock-names = "v3d", "peri_image", "h264", "isp";
system-power-controller;
};
clocks: cprman@7e101000 {
@ -629,6 +639,7 @@
compatible = "brcm,bcm2835-v3d";
reg = <0x7ec00000 0x1000>;
interrupts = <1 10>;
power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>;
};
vc4: gpu {

1
sys/gnu/dts/arm/bcm47081-asus-rt-n18u.dts
View File

@ -20,6 +20,7 @@
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x08000000>;
};

1
sys/gnu/dts/arm/bcm47081-buffalo-wzr-600dhp2.dts
View File

@ -20,6 +20,7 @@
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x08000000>;
};

1
sys/gnu/dts/arm/bcm47081-buffalo-wzr-900dhp.dts
View File

@ -20,6 +20,7 @@
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x08000000>;
};

1
sys/gnu/dts/arm/bcm47081-luxul-xap-1410.dts
View File

@ -16,6 +16,7 @@
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};

1
sys/gnu/dts/arm/bcm47081-luxul-xwr-1200.dts
View File

@ -17,6 +17,7 @@
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};

1
sys/gnu/dts/arm/bcm47081-tplink-archer-c5-v2.dts
View File

@ -16,6 +16,7 @@
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};

1
sys/gnu/dts/arm/bcm47094-dlink-dir-885l.dts
View File

@ -20,6 +20,7 @@
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x08000000>;
};

1
sys/gnu/dts/arm/bcm47094-linksys-panamera.dts
View File

@ -17,6 +17,7 @@
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x08000000>;
};

1
sys/gnu/dts/arm/bcm47094-luxul-abr-4500.dts
View File

@ -17,6 +17,7 @@
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x18000000>;
};

1
sys/gnu/dts/arm/bcm47094-luxul-xap-1610.dts
View File

@ -16,6 +16,7 @@
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};

1
sys/gnu/dts/arm/bcm47094-luxul-xbr-4500.dts
View File

@ -17,6 +17,7 @@
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x18000000>;
};

1
sys/gnu/dts/arm/bcm47094-luxul-xwr-3100.dts
View File

@ -17,6 +17,7 @@
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x08000000>;
};

1
sys/gnu/dts/arm/bcm47094-luxul-xwr-3150-v1.dts
View File

@ -17,6 +17,7 @@
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x18000000>;
};

1
sys/gnu/dts/arm/bcm47094-netgear-r8500.dts
View File

@ -17,6 +17,7 @@
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x18000000>;
};

71
sys/gnu/dts/arm/bcm47094-phicomm-k3.dts Normal file
View File

@ -0,0 +1,71 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (C) 2017 Hamster Tian <haotia@gmail.com>
* Copyright (C) 2019 Hao Dong <halbertdong@gmail.com>
*/
/dts-v1/;
#include "bcm47094.dtsi"
#include "bcm5301x-nand-cs0-bch4.dtsi"
/ {
compatible = "phicomm,k3", "brcm,bcm47094", "brcm,bcm4708";
model = "Phicomm K3";
memory {
reg = <0x00000000 0x08000000
0x88000000 0x18000000>;
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
};
};
};
&uart1 {
status = "okay";
};
&usb3_phy {
status = "okay";
};
&nandcs {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "boot";
reg = <0x0000000 0x0080000>;
read-only;
};
partition@80000 {
label = "nvram";
reg = <0x0080000 0x0100000>;
};
partition@180000{
label = "phicomm";
reg = <0x0180000 0x0280000>;
read-only;
};
partition@400000 {
label = "firmware";
reg = <0x0400000 0x7C00000>;
compatible = "brcm,trx";
};
};
};

4
sys/gnu/dts/arm/bcm47189-luxul-xap-1440.dts
View File

@ -1,7 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2017 Luxul Inc.
*
* Licensed under the ISC license.
*/
/dts-v1/;
@ -17,6 +16,7 @@
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};

4
sys/gnu/dts/arm/bcm47189-luxul-xap-810.dts
View File

@ -1,7 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2017 Luxul Inc.
*
* Licensed under the ISC license.
*/
/dts-v1/;
@ -17,6 +16,7 @@
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};

1
sys/gnu/dts/arm/bcm47189-tenda-ac9.dts
View File

@ -16,6 +16,7 @@
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};

3
sys/gnu/dts/arm/bcm5301x.dtsi
View File

@ -13,9 +13,10 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
chipcommonA {

1
sys/gnu/dts/arm/bcm53340-ubnt-unifi-switch8.dts
View File

@ -20,6 +20,7 @@
};
memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>,
<0x68000000 0x08000000>;
};

3
sys/gnu/dts/arm/bcm53573.dtsi
View File

@ -7,9 +7,10 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
aliases {

4
sys/gnu/dts/arm/bcm63138.dtsi
View File

@ -6,9 +6,9 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "skeleton.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "brcm,bcm63138";
model = "Broadcom BCM63138 DSL SoC";
interrupt-parent = <&gic>;

2
sys/gnu/dts/arm/bcm7445.dtsi
View File

@ -1,8 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi"
/ {
#address-cells = <2>;
#size-cells = <2>;

1
sys/gnu/dts/arm/bcm947189acdbmr.dts
View File

@ -18,6 +18,7 @@
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};

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