Add definitions for AMD Spectre/Meltdown CPUID information
No functional change, aside from printing recognized bits in CPU identification. The bits are documented in 111006-B "Indirect Branch Control Extension"[1] and 124441 "Speculative Store Bypass Disable."[2] Notably missing (left as future work): * Integration with hw.spec_store_bypass_disable and hw_ssb_active flag, which are currently Intel-specific * Integration with hw_ibrs_active global flag, which are currently Intel-specific * SSB_NO integration in hw_ssb_recalculate() * Bhyve integration (PR 235010) [1]: https://developer.amd.com/wp-content/resources/111006-B_AMD64TechnologyIndirectBranchControlExtenstion_WP_7-18Update_FNL.pdf [2]: https://developer.amd.com/wp-content/resources/124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf PR: 235010 (related, but does not fix) MFC after: a week
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=343120
@ -374,6 +374,17 @@
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#define AMDFEID_CLZERO 0x00000001
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#define AMDFEID_IRPERF 0x00000002
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#define AMDFEID_XSAVEERPTR 0x00000004
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#define AMDFEID_IBPB 0x00001000
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#define AMDFEID_IBRS 0x00004000
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#define AMDFEID_STIBP 0x00008000
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/* The below are only defined if the corresponding base feature above exists. */
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#define AMDFEID_IBRS_ALWAYSON 0x00010000
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#define AMDFEID_STIBP_ALWAYSON 0x00020000
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#define AMDFEID_PREFER_IBRS 0x00040000
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#define AMDFEID_SSBD 0x01000000
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/* SSBD via MSRC001_011F instead of MSR 0x48: */
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#define AMDFEID_VIRT_SSBD 0x02000000
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#define AMDFEID_SSB_NO 0x04000000
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/*
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* AMD extended function 8000_0008h ecx info
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@ -719,6 +730,10 @@
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/*
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* IA32_SPEC_CTRL and IA32_PRED_CMD MSRs are described in the Intel'
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* document 336996-001 Speculative Execution Side Channel Mitigations.
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*
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* AMD uses the same MSRs and bit definitions, as described in 111006-B
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* "Indirect Branch Control Extension" and 124441 "Speculative Store Bypass
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* Disable."
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*/
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/* MSR IA32_SPEC_CTRL */
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#define IA32_SPEC_CTRL_IBRS 0x00000001
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@ -1021,13 +1021,34 @@ printcpuinfo(void)
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}
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if (amd_extended_feature_extensions != 0) {
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u_int amd_fe_masked;
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amd_fe_masked = amd_extended_feature_extensions;
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if ((amd_fe_masked & AMDFEID_IBRS) == 0)
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amd_fe_masked &=
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~(AMDFEID_IBRS_ALWAYSON |
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AMDFEID_PREFER_IBRS);
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if ((amd_fe_masked & AMDFEID_STIBP) == 0)
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amd_fe_masked &=
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~AMDFEID_STIBP_ALWAYSON;
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printf("\n "
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"AMD Extended Feature Extensions ID EBX="
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"0x%b", amd_extended_feature_extensions,
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"0x%b", amd_fe_masked,
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"\020"
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"\001CLZERO"
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"\002IRPerf"
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"\003XSaveErPtr");
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"\003XSaveErPtr"
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"\015IBPB"
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"\017IBRS"
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"\020STIBP"
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"\021IBRS_ALWAYSON"
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"\022STIBP_ALWAYSON"
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"\023PREFER_IBRS"
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"\031SSBD"
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"\032VIRT_SSBD"
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"\033SSB_NO"
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);
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}
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if (via_feature_rng != 0 || via_feature_xcrypt != 0)
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