Import device-tree files from Linux 5.15
Sponsored by: Beckhoff Automation GmbH & Co. KG
This commit is contained in:
Emmanuel Vadot
commit
354d7675fe
@ -28,7 +28,7 @@ find_cmd = find $(srctree)/$(src) \( -name '*.yaml' ! \
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quiet_cmd_yamllint = LINT $(src)
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cmd_yamllint = ($(find_cmd) | \
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xargs $(DT_SCHEMA_LINT) -f parsable -c $(srctree)/$(src)/.yamllint) || true
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xargs $(DT_SCHEMA_LINT) -f parsable -c $(srctree)/$(src)/.yamllint >&2) || true
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quiet_cmd_chk_bindings = CHKDT $@
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cmd_chk_bindings = ($(find_cmd) | \
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@ -145,6 +145,11 @@ properties:
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- const: atmel,sama5d4
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- const: atmel,sama5
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- items:
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- const: microchip,sama7g5ek # SAMA7G5 Evaluation Kit
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- const: microchip,sama7g5
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- const: microchip,sama7
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- items:
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- enum:
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- atmel,sams70j19
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@ -45,7 +45,8 @@ RAMC SDRAM/DDR Controller required properties:
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"atmel,at91sam9260-sdramc",
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"atmel,at91sam9g45-ddramc",
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"atmel,sama5d3-ddramc",
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"microchip,sam9x60-ddramc"
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"microchip,sam9x60-ddramc",
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"microchip,sama7g5-uddrc"
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- reg: Should contain registers location and length
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Examples:
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@ -55,6 +56,17 @@ Examples:
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reg = <0xffffe800 0x200>;
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};
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RAMC PHY Controller required properties:
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- compatible: Should be "microchip,sama7g5-ddr3phy", "syscon"
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- reg: Should contain registers location and length
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Example:
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ddr3phy: ddr3phy@e3804000 {
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compatible = "microchip,sama7g5-ddr3phy", "syscon";
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reg = <0xe3804000 0x1000>;
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};
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SHDWC Shutdown Controller
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required properties:
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@ -221,9 +221,13 @@ properties:
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- prt,prti6q # Protonic PRTI6Q board
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- prt,prtwd2 # Protonic WD2 board
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- rex,imx6q-rex-pro # Rex Pro i.MX6 Quad Board
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- skov,imx6q-skov-revc-lt2 # SKOV IMX6 CPU QuadCore lt2
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- skov,imx6q-skov-revc-lt6 # SKOV IMX6 CPU QuadCore lt6
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- skov,imx6q-skov-reve-mi1010ait-1cp1 # SKOV IMX6 CPU QuadCore mi1010ait-1cp1
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- solidrun,cubox-i/q # SolidRun Cubox-i Dual/Quad
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- solidrun,hummingboard/q
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- solidrun,hummingboard2/q
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- solidrun,solidsense/q # SolidRun SolidSense Dual/Quad
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- tbs,imx6q-tbs2910 # TBS2910 Matrix ARM mini PC
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- technexion,imx6q-pico-dwarf # TechNexion i.MX6Q Pico-Dwarf
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- technexion,imx6q-pico-hobbit # TechNexion i.MX6Q Pico-Hobbit
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@ -377,9 +381,12 @@ properties:
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- prt,prtvt7 # Protonic VT7 board
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- rex,imx6dl-rex-basic # Rex Basic i.MX6 Dual Lite Board
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- riot,imx6s-riotboard # RIoTboard i.MX6S
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- skov,imx6dl-skov-revc-lt2 # SKOV IMX6 CPU SoloCore lt2
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- skov,imx6dl-skov-revc-lt6 # SKOV IMX6 CPU SoloCore lt6
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- solidrun,cubox-i/dl # SolidRun Cubox-i Solo/DualLite
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- solidrun,hummingboard/dl
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- solidrun,hummingboard2/dl # SolidRun HummingBoard2 Solo/DualLite
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- solidrun,solidsense/dl # SolidRun SolidSense Solo/DualLite
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- technexion,imx6dl-pico-dwarf # TechNexion i.MX6DL Pico-Dwarf
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- technexion,imx6dl-pico-hobbit # TechNexion i.MX6DL Pico-Hobbit
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- technexion,imx6dl-pico-nymph # TechNexion i.MX6DL Pico-Nymph
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@ -418,6 +425,12 @@ properties:
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- const: dfi,fs700e-m60
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- const: fsl,imx6dl
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- description: i.MX6DL DHCOM PicoITX Board
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items:
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- const: dh,imx6dl-dhcom-picoitx
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- const: dh,imx6dl-dhcom-som
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- const: fsl,imx6dl
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- description: i.MX6DL Gateworks Ventana Boards
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items:
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- enum:
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@ -469,6 +482,12 @@ properties:
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- const: toradex,colibri_imx6dl # Colibri iMX6 Module
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- const: fsl,imx6dl
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- description: i.MX6S DHCOM DRC02 Board
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items:
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- const: dh,imx6s-dhcom-drc02
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- const: dh,imx6s-dhcom-som
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- const: fsl,imx6dl
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- description: i.MX6SL based Boards
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items:
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- enum:
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@ -698,6 +717,7 @@ properties:
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- gw,imx8mm-gw72xx-0x # i.MX8MM Gateworks Development Kit
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- gw,imx8mm-gw73xx-0x # i.MX8MM Gateworks Development Kit
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- gw,imx8mm-gw7901 # i.MX8MM Gateworks Board
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- gw,imx8mm-gw7902 # i.MX8MM Gateworks Board
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- kontron,imx8mm-n801x-som # i.MX8MM Kontron SL (N801X) SOM
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- variscite,var-som-mx8mm # i.MX8MM Variscite VAR-SOM-MX8MM module
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- const: fsl,imx8mm
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@ -728,6 +748,7 @@ properties:
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- beacon,imx8mn-beacon-kit # i.MX8MN Beacon Development Kit
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- fsl,imx8mn-ddr4-evk # i.MX8MN DDR4 EVK Board
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- fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board
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- gw,imx8mn-gw7902 # i.MX8MM Gateworks Board
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- const: fsl,imx8mn
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- description: Variscite VAR-SOM-MX8MN based boards
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@ -752,10 +773,12 @@ properties:
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items:
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- enum:
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- boundary,imx8mq-nitrogen8m # i.MX8MQ NITROGEN Board
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- boundary,imx8mq-nitrogen8m-som # i.MX8MQ NITROGEN SoM
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- einfochips,imx8mq-thor96 # i.MX8MQ Thor96 Board
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- fsl,imx8mq-evk # i.MX8MQ EVK Board
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- google,imx8mq-phanbell # Google Coral Edge TPU
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- kontron,pitx-imx8m # Kontron pITX-imx8m Board
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- mntre,reform2 # MNT Reform2 Laptop
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- purism,librem5-devkit # Purism Librem5 devkit
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- solidrun,hummingboard-pulse # SolidRun Hummingboard Pulse
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- technexion,pico-pi-imx8m # TechNexion PICO-PI-8M evk
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@ -973,6 +996,12 @@ properties:
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- fsl,s32v234-evb # S32V234-EVB2 Customer Evaluation Board
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- const: fsl,s32v234
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- description: Traverse LS1088A based Boards
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items:
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- enum:
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- traverse,ten64 # Ten64 Networking Appliance / Board
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- const: fsl,ls1088a
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additionalProperties: true
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...
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95
sys/contrib/device-tree/Bindings/arm/gemini.yaml
Normal file
95
sys/contrib/device-tree/Bindings/arm/gemini.yaml
Normal file
@ -0,0 +1,95 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/gemini.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Cortina systems Gemini platforms
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description: |
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The Gemini SoC is the project name for an ARMv4 FA525-based SoC originally
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produced by Storlink Semiconductor around 2005. The company was renamed
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later renamed Storm Semiconductor. The chip product name is Storlink SL3516.
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It was derived from earlier products from Storm named SL3316 (Centroid) and
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SL3512 (Bulverde).
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Storm Semiconductor was acquired by Cortina Systems in 2008 and the SoC was
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produced and used for NAS and similar usecases. In 2014 Cortina Systems was
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in turn acquired by Inphi, who seem to have discontinued this product family.
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Many of the IP blocks used in the SoC comes from Faraday Technology.
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maintainers:
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- Linus Walleij <linus.walleij@linaro.org>
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properties:
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$nodename:
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const: '/'
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compatible:
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oneOf:
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- description: Storlink Semiconductor Gemini324 EV-Board also known
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as Storm Semiconductor SL93512R_BRD
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items:
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- const: storlink,gemini324
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- const: storm,sl93512r
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- const: cortina,gemini
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- description: D-Link DIR-685 Xtreme N Storage Router
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items:
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- const: dlink,dir-685
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- const: cortina,gemini
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- description: D-Link DNS-313 1-Bay Network Storage Enclosure
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items:
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- const: dlink,dns-313
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- const: cortina,gemini
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- description: Edimax NS-2502
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items:
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- const: edimax,ns-2502
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- const: cortina,gemini
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- description: ITian Square One SQ201
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items:
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- const: itian,sq201
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- const: cortina,gemini
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- description: Raidsonic NAS IB-4220-B
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items:
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- const: raidsonic,ib-4220-b
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- const: cortina,gemini
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- description: SSI 1328
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items:
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- const: ssi,1328
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- const: cortina,gemini
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- description: Teltonika RUT1xx Mobile Router
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items:
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- const: teltonika,rut1xx
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- const: cortina,gemini
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- description: Wiligear Wiliboard WBD-111
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items:
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- const: wiligear,wiliboard-wbd111
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- const: cortina,gemini
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- description: Wiligear Wiliboard WBD-222
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items:
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- const: wiligear,wiliboard-wbd222
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- const: cortina,gemini
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- description: Wiligear Wiliboard WBD-111 - old incorrect binding
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items:
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- const: wiliboard,wbd111
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- const: cortina,gemini
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deprecated: true
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- description: Wiligear Wiliboard WBD-222 - old incorrect binding
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items:
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- const: wiliboard,wbd222
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- const: cortina,gemini
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deprecated: true
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additionalProperties: true
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@ -13,6 +13,7 @@ Required Properties:
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- "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
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- "mediatek,mt8167-audiosys", "syscon"
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- "mediatek,mt8183-audiosys", "syscon"
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- "mediatek,mt8192-audsys", "syscon"
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- "mediatek,mt8516-audsys", "syscon"
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- #clock-cells: Must be 1
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@ -0,0 +1,59 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mmsys.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: MediaTek mmsys controller
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maintainers:
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- Matthias Brugger <matthias.bgg@gmail.com>
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description:
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The MediaTek mmsys system controller provides clock control, routing control,
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and miscellaneous control in mmsys partition.
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properties:
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$nodename:
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pattern: "^syscon@[0-9a-f]+$"
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compatible:
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oneOf:
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- items:
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- enum:
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- mediatek,mt2701-mmsys
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- mediatek,mt2712-mmsys
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- mediatek,mt6765-mmsys
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- mediatek,mt6779-mmsys
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- mediatek,mt6797-mmsys
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- mediatek,mt8167-mmsys
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- mediatek,mt8173-mmsys
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- mediatek,mt8183-mmsys
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- mediatek,mt8192-mmsys
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- mediatek,mt8365-mmsys
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- const: syscon
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- items:
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- const: mediatek,mt7623-mmsys
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- const: mediatek,mt2701-mmsys
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- const: syscon
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reg:
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maxItems: 1
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"#clock-cells":
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const: 1
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required:
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- compatible
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- reg
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- "#clock-cells"
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additionalProperties: false
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examples:
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- |
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mmsys: syscon@14000000 {
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compatible = "mediatek,mt8173-mmsys", "syscon";
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reg = <0x14000000 0x1000>;
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#clock-cells = <1>;
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};
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@ -0,0 +1,199 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-clock.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: MediaTek Functional Clock Controller for MT8192
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maintainers:
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- Chun-Jie Chen <chun-jie.chen@mediatek.com>
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description:
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The Mediatek functional clock controller provides various clocks on MT8192.
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properties:
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compatible:
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items:
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- enum:
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- mediatek,mt8192-scp_adsp
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- mediatek,mt8192-imp_iic_wrap_c
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- mediatek,mt8192-imp_iic_wrap_e
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- mediatek,mt8192-imp_iic_wrap_s
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- mediatek,mt8192-imp_iic_wrap_ws
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- mediatek,mt8192-imp_iic_wrap_w
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- mediatek,mt8192-imp_iic_wrap_n
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- mediatek,mt8192-msdc_top
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- mediatek,mt8192-msdc
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- mediatek,mt8192-mfgcfg
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- mediatek,mt8192-imgsys
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- mediatek,mt8192-imgsys2
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- mediatek,mt8192-vdecsys_soc
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- mediatek,mt8192-vdecsys
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- mediatek,mt8192-vencsys
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- mediatek,mt8192-camsys
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- mediatek,mt8192-camsys_rawa
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- mediatek,mt8192-camsys_rawb
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- mediatek,mt8192-camsys_rawc
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- mediatek,mt8192-ipesys
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- mediatek,mt8192-mdpsys
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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scp_adsp: clock-controller@10720000 {
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compatible = "mediatek,mt8192-scp_adsp";
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reg = <0x10720000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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imp_iic_wrap_c: clock-controller@11007000 {
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compatible = "mediatek,mt8192-imp_iic_wrap_c";
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reg = <0x11007000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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imp_iic_wrap_e: clock-controller@11cb1000 {
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compatible = "mediatek,mt8192-imp_iic_wrap_e";
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reg = <0x11cb1000 0x1000>;
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#clock-cells = <1>;
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};
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||||
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||||
- |
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imp_iic_wrap_s: clock-controller@11d03000 {
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compatible = "mediatek,mt8192-imp_iic_wrap_s";
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reg = <0x11d03000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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imp_iic_wrap_ws: clock-controller@11d23000 {
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compatible = "mediatek,mt8192-imp_iic_wrap_ws";
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reg = <0x11d23000 0x1000>;
|
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#clock-cells = <1>;
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};
|
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- |
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imp_iic_wrap_w: clock-controller@11e01000 {
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compatible = "mediatek,mt8192-imp_iic_wrap_w";
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reg = <0x11e01000 0x1000>;
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#clock-cells = <1>;
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};
|
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- |
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imp_iic_wrap_n: clock-controller@11f02000 {
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compatible = "mediatek,mt8192-imp_iic_wrap_n";
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reg = <0x11f02000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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msdc_top: clock-controller@11f10000 {
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compatible = "mediatek,mt8192-msdc_top";
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reg = <0x11f10000 0x1000>;
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#clock-cells = <1>;
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};
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||||
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- |
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msdc: clock-controller@11f60000 {
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compatible = "mediatek,mt8192-msdc";
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reg = <0x11f60000 0x1000>;
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#clock-cells = <1>;
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};
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||||
- |
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mfgcfg: clock-controller@13fbf000 {
|
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compatible = "mediatek,mt8192-mfgcfg";
|
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reg = <0x13fbf000 0x1000>;
|
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#clock-cells = <1>;
|
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};
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- |
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imgsys: clock-controller@15020000 {
|
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compatible = "mediatek,mt8192-imgsys";
|
||||
reg = <0x15020000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
- |
|
||||
imgsys2: clock-controller@15820000 {
|
||||
compatible = "mediatek,mt8192-imgsys2";
|
||||
reg = <0x15820000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
- |
|
||||
vdecsys_soc: clock-controller@1600f000 {
|
||||
compatible = "mediatek,mt8192-vdecsys_soc";
|
||||
reg = <0x1600f000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
- |
|
||||
vdecsys: clock-controller@1602f000 {
|
||||
compatible = "mediatek,mt8192-vdecsys";
|
||||
reg = <0x1602f000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
- |
|
||||
vencsys: clock-controller@17000000 {
|
||||
compatible = "mediatek,mt8192-vencsys";
|
||||
reg = <0x17000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
- |
|
||||
camsys: clock-controller@1a000000 {
|
||||
compatible = "mediatek,mt8192-camsys";
|
||||
reg = <0x1a000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
- |
|
||||
camsys_rawa: clock-controller@1a04f000 {
|
||||
compatible = "mediatek,mt8192-camsys_rawa";
|
||||
reg = <0x1a04f000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
- |
|
||||
camsys_rawb: clock-controller@1a06f000 {
|
||||
compatible = "mediatek,mt8192-camsys_rawb";
|
||||
reg = <0x1a06f000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
- |
|
||||
camsys_rawc: clock-controller@1a08f000 {
|
||||
compatible = "mediatek,mt8192-camsys_rawc";
|
||||
reg = <0x1a08f000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
- |
|
||||
ipesys: clock-controller@1b000000 {
|
||||
compatible = "mediatek,mt8192-ipesys";
|
||||
reg = <0x1b000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
- |
|
||||
mdpsys: clock-controller@1f000000 {
|
||||
compatible = "mediatek,mt8192-mdpsys";
|
||||
reg = <0x1f000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@ -0,0 +1,65 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-sys-clock.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: MediaTek System Clock Controller for MT8192
|
||||
|
||||
maintainers:
|
||||
- Chun-Jie Chen <chun-jie.chen@mediatek.com>
|
||||
|
||||
description:
|
||||
The Mediatek system clock controller provides various clocks and system configuration
|
||||
like reset and bus protection on MT8192.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- mediatek,mt8192-topckgen
|
||||
- mediatek,mt8192-infracfg
|
||||
- mediatek,mt8192-pericfg
|
||||
- mediatek,mt8192-apmixedsys
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
topckgen: syscon@10000000 {
|
||||
compatible = "mediatek,mt8192-topckgen", "syscon";
|
||||
reg = <0x10000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
- |
|
||||
infracfg: syscon@10001000 {
|
||||
compatible = "mediatek,mt8192-infracfg", "syscon";
|
||||
reg = <0x10001000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
- |
|
||||
pericfg: syscon@10003000 {
|
||||
compatible = "mediatek,mt8192-pericfg", "syscon";
|
||||
reg = <0x10003000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
- |
|
||||
apmixedsys: syscon@1000c000 {
|
||||
compatible = "mediatek,mt8192-apmixedsys", "syscon";
|
||||
reg = <0x1000c000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@ -31,6 +31,7 @@ description: |
|
||||
ipq6018
|
||||
ipq8074
|
||||
mdm9615
|
||||
msm8226
|
||||
msm8916
|
||||
msm8974
|
||||
msm8992
|
||||
@ -114,6 +115,11 @@ properties:
|
||||
- qcom,apq8084-sbc
|
||||
- const: qcom,apq8084
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,s3ve3g
|
||||
- const: qcom,msm8226
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,msm8960-cdp
|
||||
@ -129,6 +135,8 @@ properties:
|
||||
- const: qcom,msm8974
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- alcatel,idol347
|
||||
- const: qcom,msm8916-mtp/1
|
||||
- const: qcom,msm8916-mtp
|
||||
- const: qcom,msm8916
|
||||
@ -181,6 +189,8 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,sc7280-idp
|
||||
- qcom,sc7280-idp2
|
||||
- google,piglin
|
||||
- google,senor
|
||||
- const: qcom,sc7280
|
||||
|
||||
|
||||
@ -238,17 +238,29 @@ properties:
|
||||
- const: renesas,r8a77961
|
||||
|
||||
- description: Kingfisher (SBEV-RCAR-KF-M03)
|
||||
items:
|
||||
- const: shimafuji,kingfisher
|
||||
- enum:
|
||||
- renesas,h3ulcb
|
||||
- renesas,m3ulcb
|
||||
- renesas,m3nulcb
|
||||
- enum:
|
||||
- renesas,r8a7795
|
||||
- renesas,r8a7796
|
||||
- renesas,r8a77961
|
||||
- renesas,r8a77965
|
||||
oneOf:
|
||||
- items:
|
||||
- const: shimafuji,kingfisher
|
||||
- enum:
|
||||
- renesas,h3ulcb
|
||||
- renesas,m3ulcb
|
||||
- renesas,m3nulcb
|
||||
- enum:
|
||||
- renesas,r8a7795
|
||||
- renesas,r8a7796
|
||||
- renesas,r8a77961
|
||||
- renesas,r8a77965
|
||||
- items:
|
||||
- const: shimafuji,kingfisher
|
||||
- enum:
|
||||
- renesas,h3ulcb
|
||||
- renesas,m3ulcb
|
||||
- enum:
|
||||
- renesas,r8a779m1
|
||||
- renesas,r8a779m3
|
||||
- enum:
|
||||
- renesas,r8a7795
|
||||
- renesas,r8a77961
|
||||
|
||||
- description: R-Car M3-N (R8A77965)
|
||||
items:
|
||||
@ -296,6 +308,22 @@ properties:
|
||||
- const: renesas,falcon-cpu
|
||||
- const: renesas,r8a779a0
|
||||
|
||||
- description: R-Car H3e-2G (R8A779M1)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,h3ulcb # H3ULCB (R-Car Starter Kit Premier)
|
||||
- renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version)
|
||||
- const: renesas,r8a779m1
|
||||
- const: renesas,r8a7795
|
||||
|
||||
- description: R-Car M3e-2G (R8A779M3)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,m3ulcb # M3ULCB (R-Car Starter Kit Pro)
|
||||
- renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version)
|
||||
- const: renesas,r8a779m3
|
||||
- const: renesas,r8a77961
|
||||
|
||||
- description: RZ/N1D (R9A06G032)
|
||||
items:
|
||||
- enum:
|
||||
|
||||
@ -54,7 +54,7 @@ properties:
|
||||
- const: toradex,apalis_t30
|
||||
- const: nvidia,tegra30
|
||||
- items:
|
||||
- const: toradex,apalis_t30-eval-v1.1
|
||||
- const: toradex,apalis_t30-v1.1-eval
|
||||
- const: toradex,apalis_t30-eval
|
||||
- const: toradex,apalis_t30-v1.1
|
||||
- const: toradex,apalis_t30
|
||||
@ -111,6 +111,7 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,p2771-0000
|
||||
- nvidia,p3509-0000+p3636-0001
|
||||
- const: nvidia,tegra186
|
||||
- items:
|
||||
- enum:
|
||||
|
||||
@ -0,0 +1,61 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/ata/intel,ixp4xx-compact-flash.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Intel IXP4xx CompactFlash Card Controller
|
||||
|
||||
maintainers:
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
|
||||
description: |
|
||||
The IXP4xx network processors have a CompactFlash interface that presents
|
||||
a CompactFlash card to the system as a true IDE (parallel ATA) device. The
|
||||
device is always connected to the expansion bus of the IXP4xx SoCs using one
|
||||
or two chip select areas and address translating logic on the board. The
|
||||
node must be placed inside a chip select node on the IXP4xx expansion bus.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: intel,ixp4xx-compact-flash
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Command interface registers
|
||||
- description: Control interface registers
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
allOf:
|
||||
- $ref: pata-common.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
bus@c4000000 {
|
||||
compatible = "intel,ixp43x-expansion-bus-controller", "syscon";
|
||||
reg = <0xc4000000 0x1000>;
|
||||
native-endian;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x0 0x50000000 0x01000000>, <1 0x0 0x51000000 0x01000000>;
|
||||
dma-ranges = <0 0x0 0x50000000 0x01000000>, <1 0x0 0x51000000 0x01000000>;
|
||||
ide@1,0 {
|
||||
compatible = "intel,ixp4xx-compact-flash";
|
||||
reg = <1 0x00000000 0x1000>, <1 0x00040000 0x1000>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <12 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@ -0,0 +1,44 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/auxdisplay/arm,versatile-lcd.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM Versatile Character LCD
|
||||
|
||||
maintainers:
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
- Rob Herring <robh@kernel.org>
|
||||
|
||||
description:
|
||||
This binding defines the character LCD interface found on ARM Versatile AB
|
||||
and PB reference platforms.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: arm,versatile-lcd
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
lcd@10008000 {
|
||||
compatible = "arm,versatile-lcd";
|
||||
reg = <0x10008000 0x1000>;
|
||||
};
|
||||
@ -12,7 +12,10 @@ maintainers:
|
||||
description:
|
||||
The Hitachi HD44780 Character LCD Controller is commonly used on character
|
||||
LCDs that can display one or more lines of text. It exposes an M6800 bus
|
||||
interface, which can be used in either 4-bit or 8-bit mode.
|
||||
interface, which can be used in either 4-bit or 8-bit mode. By using a
|
||||
GPIO expander it is possible to use the driver with one of the popular I2C
|
||||
expander boards based on the PCF8574 available for these displays. For
|
||||
an example see below.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
@ -94,3 +97,29 @@ examples:
|
||||
display-height-chars = <2>;
|
||||
display-width-chars = <16>;
|
||||
};
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pcf8574: pcf8574@27 {
|
||||
compatible = "nxp,pcf8574";
|
||||
reg = <0x27>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
hd44780 {
|
||||
compatible = "hit,hd44780";
|
||||
display-height-chars = <2>;
|
||||
display-width-chars = <16>;
|
||||
data-gpios = <&pcf8574 4 0>,
|
||||
<&pcf8574 5 0>,
|
||||
<&pcf8574 6 0>,
|
||||
<&pcf8574 7 0>;
|
||||
enable-gpios = <&pcf8574 2 0>;
|
||||
rs-gpios = <&pcf8574 0 0>;
|
||||
rw-gpios = <&pcf8574 1 0>;
|
||||
backlight-gpios = <&pcf8574 3 0>;
|
||||
};
|
||||
|
||||
@ -0,0 +1,55 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/auxdisplay/img,ascii-lcd.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ASCII LCD displays on Imagination Technologies boards
|
||||
|
||||
maintainers:
|
||||
- Paul Burton <paulburton@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- img,boston-lcd
|
||||
- mti,malta-lcd
|
||||
- mti,sead3-lcd
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
offset:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Offset in bytes to the LCD registers within the system controller
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
oneOf:
|
||||
- required:
|
||||
- reg
|
||||
- required:
|
||||
- offset
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: img,boston-lcd
|
||||
then:
|
||||
required:
|
||||
- reg
|
||||
else:
|
||||
required:
|
||||
- offset
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
lcd: lcd@17fff000 {
|
||||
compatible = "img,boston-lcd";
|
||||
reg = <0x17fff000 0x8>;
|
||||
};
|
||||
@ -0,0 +1,168 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/bus/intel,ixp4xx-expansion-bus-controller.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Intel IXP4xx Expansion Bus Controller
|
||||
|
||||
description: |
|
||||
The IXP4xx expansion bus controller handles access to devices on the
|
||||
memory-mapped expansion bus on the Intel IXP4xx family of system on chips,
|
||||
including IXP42x, IXP43x, IXP45x and IXP46x.
|
||||
|
||||
maintainers:
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: '^bus@[0-9a-f]+$'
|
||||
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- intel,ixp42x-expansion-bus-controller
|
||||
- intel,ixp43x-expansion-bus-controller
|
||||
- intel,ixp45x-expansion-bus-controller
|
||||
- intel,ixp46x-expansion-bus-controller
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
description: Control registers for the expansion bus, these are not
|
||||
inside the memory range handled by the expansion bus.
|
||||
maxItems: 1
|
||||
|
||||
native-endian:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: The IXP4xx has a peculiar MMIO access scheme, as it changes
|
||||
the access pattern for words (swizzling) on the bus depending on whether
|
||||
the SoC is running in big-endian or little-endian mode. Thus the
|
||||
registers must always be accessed using native endianness.
|
||||
|
||||
"#address-cells":
|
||||
description: |
|
||||
The first cell is the chip select number.
|
||||
The second cell is the address offset within the bank.
|
||||
const: 2
|
||||
|
||||
"#size-cells":
|
||||
const: 1
|
||||
|
||||
ranges: true
|
||||
dma-ranges: true
|
||||
|
||||
patternProperties:
|
||||
"^.*@[0-7],[0-9a-f]+$":
|
||||
description: Devices attached to chip selects are represented as
|
||||
subnodes.
|
||||
type: object
|
||||
|
||||
properties:
|
||||
intel,ixp4xx-eb-t1:
|
||||
description: Address timing, extend address phase with n cycles.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 3
|
||||
|
||||
intel,ixp4xx-eb-t2:
|
||||
description: Setup chip select timing, extend setup phase with n cycles.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 3
|
||||
|
||||
intel,ixp4xx-eb-t3:
|
||||
description: Strobe timing, extend strobe phase with n cycles.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 15
|
||||
|
||||
intel,ixp4xx-eb-t4:
|
||||
description: Hold timing, extend hold phase with n cycles.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 3
|
||||
|
||||
intel,ixp4xx-eb-t5:
|
||||
description: Recovery timing, extend recovery phase with n cycles.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 15
|
||||
|
||||
intel,ixp4xx-eb-cycle-type:
|
||||
description: The type of cycles to use on the expansion bus for this
|
||||
chip select. 0 = Intel cycles, 1 = Motorola cycles, 2 = HPI cycles.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2]
|
||||
|
||||
intel,ixp4xx-eb-byte-access-on-halfword:
|
||||
description: Allow byte read access on half word devices.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
|
||||
intel,ixp4xx-eb-hpi-hrdy-pol-high:
|
||||
description: Set HPI HRDY polarity to active high when using HPI.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
|
||||
intel,ixp4xx-eb-mux-address-and-data:
|
||||
description: Multiplex address and data on the data bus.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
|
||||
intel,ixp4xx-eb-ahb-split-transfers:
|
||||
description: Enable AHB split transfers.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
|
||||
intel,ixp4xx-eb-write-enable:
|
||||
description: Enable write cycles.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
|
||||
intel,ixp4xx-eb-byte-access:
|
||||
description: Expansion bus uses only 8 bits. The default is to use
|
||||
16 bits.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- native-endian
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
- ranges
|
||||
- dma-ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
bus@50000000 {
|
||||
compatible = "intel,ixp42x-expansion-bus-controller", "syscon";
|
||||
reg = <0xc4000000 0x28>;
|
||||
native-endian;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x0 0x50000000 0x01000000>,
|
||||
<1 0x0 0x51000000 0x01000000>;
|
||||
dma-ranges = <0 0x0 0x50000000 0x01000000>,
|
||||
<1 0x0 0x51000000 0x01000000>;
|
||||
flash@0,0 {
|
||||
compatible = "intel,ixp4xx-flash", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
reg = <0 0x00000000 0x1000000>;
|
||||
intel,ixp4xx-eb-t3 = <3>;
|
||||
intel,ixp4xx-eb-cycle-type = <0>;
|
||||
intel,ixp4xx-eb-byte-access-on-halfword = <1>;
|
||||
intel,ixp4xx-eb-write-enable = <1>;
|
||||
intel,ixp4xx-eb-byte-access = <0>;
|
||||
};
|
||||
serial@1,0 {
|
||||
compatible = "exar,xr16l2551", "ns8250";
|
||||
reg = <1 0x00000000 0x10>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
|
||||
clock-frequency = <1843200>;
|
||||
intel,ixp4xx-eb-t3 = <3>;
|
||||
intel,ixp4xx-eb-cycle-type = <1>;
|
||||
intel,ixp4xx-eb-write-enable = <1>;
|
||||
intel,ixp4xx-eb-byte-access = <1>;
|
||||
};
|
||||
};
|
||||
@ -79,9 +79,9 @@ a different secondary CPU release mechanism)
|
||||
linux,usable-memory-range
|
||||
-------------------------
|
||||
|
||||
This property (arm64 only) holds a base address and size, describing a
|
||||
limited region in which memory may be considered available for use by
|
||||
the kernel. Memory outside of this range is not available for use.
|
||||
This property holds a base address and size, describing a limited region in
|
||||
which memory may be considered available for use by the kernel. Memory outside
|
||||
of this range is not available for use.
|
||||
|
||||
This property describes a limitation: memory within this range is only
|
||||
valid when also described through another mechanism that the kernel
|
||||
@ -106,9 +106,9 @@ respectively, of the root node.
|
||||
linux,elfcorehdr
|
||||
----------------
|
||||
|
||||
This property (currently used only on arm64) holds the memory range,
|
||||
the address and the size, of the elf core header which mainly describes
|
||||
the panicked kernel's memory layout as PT_LOAD segments of elf format.
|
||||
This property holds the memory range, the address and the size, of the elf
|
||||
core header which mainly describes the panicked kernel's memory layout as
|
||||
PT_LOAD segments of elf format.
|
||||
e.g.
|
||||
|
||||
/ {
|
||||
|
||||
@ -61,13 +61,30 @@ properties:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
true
|
||||
|
||||
clock-output-names:
|
||||
minItems: 1
|
||||
maxItems: 45
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- brcm,cygnus-armpll
|
||||
- brcm,nsp-armpll
|
||||
then:
|
||||
properties:
|
||||
'#clock-cells':
|
||||
const: 0
|
||||
else:
|
||||
properties:
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
required:
|
||||
- clock-output-names
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
@ -358,7 +375,6 @@ required:
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
- clock-output-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
@ -392,3 +408,10 @@ examples:
|
||||
clocks = <&osc2>;
|
||||
clock-output-names = "keypad", "adc/touch", "pwm";
|
||||
};
|
||||
- |
|
||||
arm_clk@0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "brcm,nsp-armpll";
|
||||
clocks = <&osc>;
|
||||
reg = <0x0 0x1000>;
|
||||
};
|
||||
|
||||
@ -30,6 +30,20 @@ description: |
|
||||
3 -- OUT3
|
||||
4 -- OUT4
|
||||
|
||||
The idt,shutdown and idt,output-enable-active properties control the
|
||||
SH (en_global_shutdown) and SP bits of the Primary Source and Shutdown
|
||||
Register, respectively. Their behavior is summarized by the following
|
||||
table:
|
||||
|
||||
SH SP Output when the SD/OE pin is Low/High
|
||||
== == =====================================
|
||||
0 0 Active/Inactive
|
||||
0 1 Inactive/Active
|
||||
1 0 Active/Shutdown
|
||||
1 1 Inactive/Shutdown
|
||||
|
||||
The case where SH and SP are both 1 is likely not very interesting.
|
||||
|
||||
maintainers:
|
||||
- Luca Ceresoli <luca@lucaceresoli.net>
|
||||
|
||||
@ -64,6 +78,26 @@ properties:
|
||||
maximum: 22760
|
||||
description: Optional load capacitor for XTAL1 and XTAL2
|
||||
|
||||
idt,shutdown:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
description: |
|
||||
If 1, this enables the shutdown functionality: the chip will be
|
||||
shut down if the SD/OE pin is driven high. If 0, this disables the
|
||||
shutdown functionality: the chip will never be shut down based on
|
||||
the value of the SD/OE pin. This property corresponds to the SH
|
||||
bit of the Primary Source and Shutdown Register.
|
||||
|
||||
idt,output-enable-active:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
description: |
|
||||
If 1, this enables output when the SD/OE pin is high, and disables
|
||||
output when the SD/OE pin is low. If 0, this disables output when
|
||||
the SD/OE pin is high, and enables output when the SD/OE pin is
|
||||
low. This corresponds to the SP bit of the Primary Source and
|
||||
Shutdown Register.
|
||||
|
||||
patternProperties:
|
||||
"^OUT[1-4]$":
|
||||
type: object
|
||||
@ -90,6 +124,8 @@ required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- idt,shutdown
|
||||
- idt,output-enable-active
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
@ -139,6 +175,10 @@ examples:
|
||||
clocks = <&ref25m>;
|
||||
clock-names = "xin";
|
||||
|
||||
/* Set the SD/OE pin's settings */
|
||||
idt,shutdown = <0>;
|
||||
idt,output-enable-active = <0>;
|
||||
|
||||
OUT1 {
|
||||
idt,mode = <VC5_CMOSD>;
|
||||
idt,voltage-microvolt = <1800000>;
|
||||
|
||||
@ -18,6 +18,7 @@ properties:
|
||||
enum:
|
||||
- qcom,ipq6018-a53pll
|
||||
- qcom,msm8916-a53pll
|
||||
- qcom,msm8939-a53pll
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@ -33,6 +34,8 @@ properties:
|
||||
items:
|
||||
- const: xo
|
||||
|
||||
operating-points-v2: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
72
sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm6115.yaml
Normal file
72
sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm6115.yaml
Normal file
@ -0,0 +1,72 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm6115.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for SM6115 and SM4250
|
||||
|
||||
maintainers:
|
||||
- Iskren Chernev <iskren.chernev@gmail.com>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on SM4250/6115.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-sm6115.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-sm6115
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Sleep clock source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: sleep_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
clock-controller@1400000 {
|
||||
compatible = "qcom,gcc-sm6115";
|
||||
reg = <0x01400000 0x1f0000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
clock-names = "bi_tcxo", "sleep_clk";
|
||||
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
|
||||
};
|
||||
...
|
||||
76
sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm6350.yaml
Normal file
76
sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm6350.yaml
Normal file
@ -0,0 +1,76 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm6350.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for SM6350
|
||||
|
||||
maintainers:
|
||||
- Konrad Dybcio <konrad.dybcio@somainline.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on SM6350.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-sm6350.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-sm6350
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board active XO source
|
||||
- description: Sleep clock source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: bi_tcxo_ao
|
||||
- const: sleep_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sm6350";
|
||||
reg = <0x00100000 0x1f0000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&sleep_clk>;
|
||||
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@ -23,6 +23,7 @@ description: |
|
||||
- dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
|
||||
- dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
|
||||
- dt-bindings/clock/qcom,gcc-msm8939.h
|
||||
- dt-bindings/clock/qcom,gcc-msm8953.h
|
||||
- dt-bindings/reset/qcom,gcc-msm8939.h
|
||||
- dt-bindings/clock/qcom,gcc-msm8660.h
|
||||
- dt-bindings/reset/qcom,gcc-msm8660.h
|
||||
@ -46,6 +47,7 @@ properties:
|
||||
- qcom,gcc-msm8660
|
||||
- qcom,gcc-msm8916
|
||||
- qcom,gcc-msm8939
|
||||
- qcom,gcc-msm8953
|
||||
- qcom,gcc-msm8960
|
||||
- qcom,gcc-msm8974
|
||||
- qcom,gcc-msm8974pro
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml#
|
||||
@ -11,11 +11,12 @@ maintainers:
|
||||
|
||||
description: |
|
||||
Qualcomm graphics clock control module which supports the clocks, resets and
|
||||
power domains on SDM845/SC7180/SM8150/SM8250.
|
||||
power domains on Qualcomm SoCs.
|
||||
|
||||
See also:
|
||||
dt-bindings/clock/qcom,gpucc-sdm845.h
|
||||
dt-bindings/clock/qcom,gpucc-sc7180.h
|
||||
dt-bindings/clock/qcom,gpucc-sc7280.h
|
||||
dt-bindings/clock/qcom,gpucc-sm8150.h
|
||||
dt-bindings/clock/qcom,gpucc-sm8250.h
|
||||
|
||||
@ -24,6 +25,8 @@ properties:
|
||||
enum:
|
||||
- qcom,sdm845-gpucc
|
||||
- qcom,sc7180-gpucc
|
||||
- qcom,sc7280-gpucc
|
||||
- qcom,sc8180x-gpucc
|
||||
- qcom,sm8150-gpucc
|
||||
- qcom,sm8250-gpucc
|
||||
|
||||
|
||||
@ -22,6 +22,8 @@ properties:
|
||||
- qcom,mmcc-msm8660
|
||||
- qcom,mmcc-msm8960
|
||||
- qcom,mmcc-msm8974
|
||||
- qcom,mmcc-msm8992
|
||||
- qcom,mmcc-msm8994
|
||||
- qcom,mmcc-msm8996
|
||||
- qcom,mmcc-msm8998
|
||||
- qcom,mmcc-sdm630
|
||||
|
||||
@ -10,11 +10,13 @@ Required properties :
|
||||
- compatible : shall contain only one of the following. The generic
|
||||
compatible "qcom,rpmcc" should be also included.
|
||||
|
||||
"qcom,rpmcc-mdm9607", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8660", "qcom,rpmcc"
|
||||
"qcom,rpmcc-apq8060", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8226", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8916", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8936", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8953", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8974", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8976", "qcom,rpmcc"
|
||||
"qcom,rpmcc-apq8064", "qcom,rpmcc"
|
||||
@ -25,6 +27,8 @@ Required properties :
|
||||
"qcom,rpmcc-msm8998", "qcom,rpmcc"
|
||||
"qcom,rpmcc-qcs404", "qcom,rpmcc"
|
||||
"qcom,rpmcc-sdm660", "qcom,rpmcc"
|
||||
"qcom,rpmcc-sm6115", "qcom,rpmcc"
|
||||
"qcom,rpmcc-sm6125", "qcom,rpmcc"
|
||||
|
||||
- #clock-cells : shall contain 1
|
||||
|
||||
|
||||
@ -22,6 +22,7 @@ properties:
|
||||
- qcom,sc8180x-rpmh-clk
|
||||
- qcom,sdm845-rpmh-clk
|
||||
- qcom,sdx55-rpmh-clk
|
||||
- qcom,sm6350-rpmh-clk
|
||||
- qcom,sm8150-rpmh-clk
|
||||
- qcom,sm8250-rpmh-clk
|
||||
- qcom,sm8350-rpmh-clk
|
||||
|
||||
@ -0,0 +1,94 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sc7280-dispcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display Clock & Reset Controller Binding for SC7280
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm display clock control module which supports the clocks, resets and
|
||||
power domains on SC7280.
|
||||
|
||||
See also dt-bindings/clock/qcom,dispcc-sc7280.h.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sc7280-dispcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: GPLL0 source from GCC
|
||||
- description: Byte clock from DSI PHY
|
||||
- description: Pixel clock from DSI PHY
|
||||
- description: Link clock from DP PHY
|
||||
- description: VCO DIV clock from DP PHY
|
||||
- description: Link clock from EDP PHY
|
||||
- description: VCO DIV clock from EDP PHY
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: gcc_disp_gpll0_clk
|
||||
- const: dsi0_phy_pll_out_byteclk
|
||||
- const: dsi0_phy_pll_out_dsiclk
|
||||
- const: dp_phy_pll_link_clk
|
||||
- const: dp_phy_pll_vco_div_clk
|
||||
- const: edp_phy_pll_link_clk
|
||||
- const: edp_phy_pll_vco_div_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@af00000 {
|
||||
compatible = "qcom,sc7280-dispcc";
|
||||
reg = <0x0af00000 0x200000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_DISP_GPLL0_CLK_SRC>,
|
||||
<&dsi_phy 0>,
|
||||
<&dsi_phy 1>,
|
||||
<&dp_phy 0>,
|
||||
<&dp_phy 1>,
|
||||
<&edp_phy 0>,
|
||||
<&edp_phy 1>;
|
||||
clock-names = "bi_tcxo",
|
||||
"gcc_disp_gpll0_clk",
|
||||
"dsi0_phy_pll_out_byteclk",
|
||||
"dsi0_phy_pll_out_dsiclk",
|
||||
"dp_phy_pll_link_clk",
|
||||
"dp_phy_pll_vco_div_clk",
|
||||
"edp_phy_pll_link_clk",
|
||||
"edp_phy_pll_vco_div_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@ -1,4 +1,4 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,videocc.yaml#
|
||||
@ -11,10 +11,11 @@ maintainers:
|
||||
|
||||
description: |
|
||||
Qualcomm video clock control module which supports the clocks, resets and
|
||||
power domains on SDM845/SC7180/SM8150/SM8250.
|
||||
power domains on Qualcomm SoCs.
|
||||
|
||||
See also:
|
||||
dt-bindings/clock/qcom,videocc-sc7180.h
|
||||
dt-bindings/clock/qcom,videocc-sc7280.h
|
||||
dt-bindings/clock/qcom,videocc-sdm845.h
|
||||
dt-bindings/clock/qcom,videocc-sm8150.h
|
||||
dt-bindings/clock/qcom,videocc-sm8250.h
|
||||
@ -23,6 +24,7 @@ properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sc7180-videocc
|
||||
- qcom,sc7280-videocc
|
||||
- qcom,sdm845-videocc
|
||||
- qcom,sm8150-videocc
|
||||
- qcom,sm8250-videocc
|
||||
|
||||
@ -0,0 +1,92 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rk3399-cru.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip RK3399 Clock and Reset Unit
|
||||
|
||||
maintainers:
|
||||
- Xing Zheng <zhengxing@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description: |
|
||||
The RK3399 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "xin32k" - rtc clock - optional,
|
||||
- "clkin_gmac" - external GMAC clock - optional,
|
||||
- "clkin_i2s" - external I2S clock - optional,
|
||||
- "pclkin_cif" - external ISP clock - optional,
|
||||
- "clk_usbphy0_480m" - output clock of the pll in the usbphy0
|
||||
- "clk_usbphy1_480m" - output clock of the pll in the usbphy1
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rk3399-pmucru
|
||||
- rockchip,rk3399-cru
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
|
||||
assigned-clocks:
|
||||
minItems: 1
|
||||
maxItems: 64
|
||||
|
||||
assigned-clock-parents:
|
||||
minItems: 1
|
||||
maxItems: 64
|
||||
|
||||
assigned-clock-rates:
|
||||
minItems: 1
|
||||
maxItems: 64
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: >
|
||||
phandle to the syscon managing the "general register files". It is used
|
||||
for GRF muxes, if missing any muxes present in the GRF will not be
|
||||
available.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
pmucru: pmu-clock-controller@ff750000 {
|
||||
compatible = "rockchip,rk3399-pmucru";
|
||||
reg = <0xff750000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
- |
|
||||
cru: clock-controller@ff760000 {
|
||||
compatible = "rockchip,rk3399-cru";
|
||||
reg = <0xff760000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -0,0 +1,80 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/samsung,exynos-audss-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos SoC Audio SubSystem clock controller
|
||||
|
||||
maintainers:
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
- Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
- Tomasz Figa <tomasz.figa@gmail.com>
|
||||
|
||||
description: |
|
||||
All available clocks are defined as preprocessor macros in
|
||||
include/dt-bindings/clock/exynos-audss-clk.h header.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynos4210-audss-clock
|
||||
- samsung,exynos5250-audss-clock
|
||||
- samsung,exynos5410-audss-clock
|
||||
- samsung,exynos5420-audss-clock
|
||||
|
||||
clocks:
|
||||
minItems: 2
|
||||
items:
|
||||
- description:
|
||||
Fixed rate PLL reference clock, parent of mout_audss. "fin_pll" is
|
||||
used if not specified.
|
||||
- description:
|
||||
Input PLL to the AudioSS block, parent of mout_audss. "fout_epll" is
|
||||
used if not specified.
|
||||
- description:
|
||||
Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if not
|
||||
specified.
|
||||
- description:
|
||||
PCM clock, parent of sclk_pcm. "sclk_pcm0" is used if not specified.
|
||||
- description:
|
||||
External i2s clock, parent of mout_i2s. "cdclk0" is used if not
|
||||
specified.
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
items:
|
||||
- const: pll_ref
|
||||
- const: pll_in
|
||||
- const: sclk_audio
|
||||
- const: sclk_pcm_in
|
||||
- const: cdclk
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- "#clock-cells"
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@3810000 {
|
||||
compatible = "samsung,exynos5250-audss-clock";
|
||||
reg = <0x03810000 0x0c>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>, <&ext_i2s_clk>;
|
||||
clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";
|
||||
};
|
||||
@ -0,0 +1,59 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/samsung,exynos-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos SoC clock controller
|
||||
|
||||
maintainers:
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
- Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
- Tomasz Figa <tomasz.figa@gmail.com>
|
||||
|
||||
description: |
|
||||
All available clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/ headers.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- samsung,exynos3250-cmu
|
||||
- samsung,exynos3250-cmu-dmc
|
||||
- samsung,exynos3250-cmu-isp
|
||||
- samsung,exynos4210-clock
|
||||
- samsung,exynos4412-clock
|
||||
- samsung,exynos5250-clock
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos5420-clock
|
||||
- samsung,exynos5800-clock
|
||||
- const: syscon
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/exynos5250.h>
|
||||
clock: clock-controller@10010000 {
|
||||
compatible = "samsung,exynos5250-clock";
|
||||
reg = <0x10010000 0x30000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@ -0,0 +1,46 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/samsung,exynos-ext-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung SoC external/osc/XXTI/XusbXTI clock
|
||||
|
||||
maintainers:
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
- Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
- Tomasz Figa <tomasz.figa@gmail.com>
|
||||
|
||||
description: |
|
||||
Samsung SoCs require an external clock supplied through XXTI or XusbXTI pins.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,clock-xxti
|
||||
- samsung,clock-xusbxti
|
||||
- samsung,exynos5420-oscclk
|
||||
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
clock-frequency: true
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clock-frequency
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
fixed-rate-clocks {
|
||||
clock {
|
||||
compatible = "samsung,clock-xxti";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,64 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/samsung,exynos4412-isp-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos4412 SoC ISP clock controller
|
||||
|
||||
maintainers:
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
- Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
- Tomasz Figa <tomasz.figa@gmail.com>
|
||||
|
||||
description: |
|
||||
Clock controller for Samsung Exynos4412 SoC FIMC-ISP (Camera ISP)
|
||||
All available clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/ headers.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: samsung,exynos4412-isp-clock
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: CLK_ACLK200 from the main clock controller
|
||||
- description: CLK_ACLK400_MCUISP from the main clock controller
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: aclk200
|
||||
- const: aclk400_mcuisp
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
- clocks
|
||||
- clock-names
|
||||
- power-domains
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/exynos4.h>
|
||||
clock-controller@10048000 {
|
||||
compatible = "samsung,exynos4412-isp-clock";
|
||||
reg = <0x10048000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
power-domains = <&pd_isp>;
|
||||
clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>;
|
||||
clock-names = "aclk200", "aclk400_mcuisp";
|
||||
};
|
||||
|
||||
@ -0,0 +1,78 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/samsung,s5pv210-audss-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung S5Pv210 SoC Audio SubSystem clock controller
|
||||
|
||||
maintainers:
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
- Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
- Tomasz Figa <tomasz.figa@gmail.com>
|
||||
|
||||
description: |
|
||||
All available clocks are defined as preprocessor macros in
|
||||
include/dt-bindings/clock/s5pv210-audss.h header.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: samsung,s5pv210-audss-clock
|
||||
|
||||
clocks:
|
||||
minItems: 4
|
||||
items:
|
||||
- description:
|
||||
AHB bus clock of the Audio Subsystem.
|
||||
- description:
|
||||
Optional fixed rate PLL reference clock, parent of mout_audss. If not
|
||||
specified (i.e. xusbxti is used for PLL reference), it is fixed to a
|
||||
clock named "xxti".
|
||||
- description:
|
||||
Input PLL to the AudioSS block, parent of mout_audss.
|
||||
- description:
|
||||
Audio bus clock, parent of mout_i2s.
|
||||
- description:
|
||||
Optional external i2s clock, parent of mout_i2s. If not specified, it
|
||||
is fixed to a clock named "iiscdclk0".
|
||||
|
||||
clock-names:
|
||||
minItems: 4
|
||||
items:
|
||||
- const: hclk
|
||||
- const: xxti
|
||||
- const: fout_epll
|
||||
- const: sclk_audio0
|
||||
- const: iiscdclk0
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- "#clock-cells"
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/s5pv210.h>
|
||||
|
||||
clock-controller@c0900000 {
|
||||
compatible = "samsung,s5pv210-audss-clock";
|
||||
reg = <0xc0900000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
clock-names = "hclk", "xxti", "fout_epll", "sclk_audio0";
|
||||
clocks = <&clocks DOUT_HCLKP>, <&xxti>, <&clocks FOUT_EPLL>,
|
||||
<&clocks SCLK_AUDIO0>;
|
||||
};
|
||||
@ -111,6 +111,10 @@ properties:
|
||||
- 1.5A
|
||||
- 3.0A
|
||||
|
||||
pd-disable:
|
||||
description: Set this property if the Type-C connector has no power delivery support.
|
||||
type: boolean
|
||||
|
||||
# The following are optional properties for "usb-c-connector" with power
|
||||
# delivery support.
|
||||
source-pdos:
|
||||
|
||||
@ -11,7 +11,7 @@ Required properties:
|
||||
- None
|
||||
|
||||
Optional properties:
|
||||
- operating-points: Refer to Documentation/devicetree/bindings/opp/opp.txt for
|
||||
- operating-points: Refer to Documentation/devicetree/bindings/opp/opp-v1.yaml for
|
||||
details. OPPs *must* be supplied either via DT, i.e. this property, or
|
||||
populated at runtime.
|
||||
- clock-latency: Specify the possible maximum transition latency for clock,
|
||||
|
||||
@ -0,0 +1,70 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/cpufreq/cpufreq-mediatek-hw.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek's CPUFREQ Bindings
|
||||
|
||||
maintainers:
|
||||
- Hector Yuan <hector.yuan@mediatek.com>
|
||||
|
||||
description:
|
||||
CPUFREQ HW is a hardware engine used by MediaTek SoCs to
|
||||
manage frequency in hardware. It is capable of controlling
|
||||
frequency for multiple clusters.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: mediatek,cpufreq-hw
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
description:
|
||||
Addresses and sizes for the memory of the HW bases in
|
||||
each frequency domain. Each entry corresponds to
|
||||
a register bank for each frequency domain present.
|
||||
|
||||
"#performance-domain-cells":
|
||||
description:
|
||||
Number of cells in a performance domain specifier.
|
||||
Set const to 1 here for nodes providing multiple
|
||||
performance domains.
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#performance-domain-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
enable-method = "psci";
|
||||
performance-domains = <&performance 0>;
|
||||
reg = <0x000>;
|
||||
};
|
||||
};
|
||||
|
||||
/* ... */
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
performance: performance-controller@11bc00 {
|
||||
compatible = "mediatek,cpufreq-hw";
|
||||
reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
|
||||
|
||||
#performance-domain-cells = <1>;
|
||||
};
|
||||
};
|
||||
@ -10,7 +10,7 @@ Required properties:
|
||||
transition and not stable yet.
|
||||
Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for
|
||||
generic clock consumer properties.
|
||||
- operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp.txt
|
||||
- operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp-v2.yaml
|
||||
for detail.
|
||||
- proc-supply: Regulator for Vproc of CPU cluster.
|
||||
|
||||
|
||||
@ -6,8 +6,6 @@ from the SoC, then supplies the OPP framework with 'prop' and 'supported
|
||||
hardware' information respectively. The framework is then able to read
|
||||
the DT and operate in the usual way.
|
||||
|
||||
For more information about the expected DT format [See: ../opp/opp.txt].
|
||||
|
||||
Frequency Scaling only
|
||||
----------------------
|
||||
|
||||
@ -15,7 +13,7 @@ No vendor specific driver required for this.
|
||||
|
||||
Located in CPU's node:
|
||||
|
||||
- operating-points : [See: ../power/opp.txt]
|
||||
- operating-points : [See: ../power/opp-v1.yaml]
|
||||
|
||||
Example [safe]
|
||||
--------------
|
||||
@ -37,7 +35,7 @@ This requires the ST CPUFreq driver to supply 'process' and 'version' info.
|
||||
|
||||
Located in CPU's node:
|
||||
|
||||
- operating-points-v2 : [See ../power/opp.txt]
|
||||
- operating-points-v2 : [See ../power/opp-v2.yaml]
|
||||
|
||||
Example [unsafe]
|
||||
----------------
|
||||
|
||||
@ -4,7 +4,7 @@ Binding for NVIDIA Tegra20 CPUFreq
|
||||
Required properties:
|
||||
- clocks: Must contain an entry for the CPU clock.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- operating-points-v2: See ../bindings/opp/opp.txt for details.
|
||||
- operating-points-v2: See ../bindings/opp/opp-v2.yaml for details.
|
||||
- #cooling-cells: Should be 2. See ../thermal/thermal-cooling-devices.yaml for details.
|
||||
|
||||
For each opp entry in 'operating-points-v2' table:
|
||||
|
||||
@ -0,0 +1,48 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/devfreq/event/samsung,exynos-nocp.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos NoC (Network on Chip) Probe
|
||||
|
||||
maintainers:
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
|
||||
description: |
|
||||
The Samsung Exynos542x SoC has a NoC (Network on Chip) Probe for NoC bus.
|
||||
NoC provides the primitive values to get the performance data. The packets
|
||||
that the Network on Chip (NoC) probes detects are transported over the
|
||||
network infrastructure to observer units. You can configure probes to capture
|
||||
packets with header or data on the data request response network, or as
|
||||
traffic debug or statistic collectors. Exynos542x bus has multiple NoC probes
|
||||
to provide bandwidth information about behavior of the SoC that you can use
|
||||
while analyzing system performance.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: samsung,exynos5420-nocp
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: nocp
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
nocp_mem0_0: nocp@10ca1000 {
|
||||
compatible = "samsung,exynos5420-nocp";
|
||||
reg = <0x10ca1000 0x200>;
|
||||
};
|
||||
@ -0,0 +1,169 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/devfreq/event/samsung,exynos-ppmu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos SoC PPMU (Platform Performance Monitoring Unit)
|
||||
|
||||
maintainers:
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
|
||||
description: |
|
||||
The Samsung Exynos SoC has PPMU (Platform Performance Monitoring Unit) for
|
||||
each IP. PPMU provides the primitive values to get performance data. These
|
||||
PPMU events provide information of the SoC's behaviors so that you may use to
|
||||
analyze system performance, to make behaviors visible and to count usages of
|
||||
each IP (DMC, CPU, RIGHTBUS, LEFTBUS, CAM interface, LCD, G3D, MFC). The
|
||||
Exynos PPMU driver uses the devfreq-event class to provide event data to
|
||||
various devfreq devices. The devfreq devices would use the event data when
|
||||
derterming the current state of each IP.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynos-ppmu
|
||||
- samsung,exynos-ppmu-v2
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: ppmu
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
events:
|
||||
type: object
|
||||
|
||||
patternProperties:
|
||||
'^ppmu-event[0-9]+(-[a-z0-9]+){,2}$':
|
||||
type: object
|
||||
properties:
|
||||
event-name:
|
||||
description: |
|
||||
The unique event name among PPMU device
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
|
||||
event-data-type:
|
||||
description: |
|
||||
Define the type of data which shell be counted by the counter.
|
||||
You can check include/dt-bindings/pmu/exynos_ppmu.h for all
|
||||
possible type, i.e. count read requests, count write data in
|
||||
bytes, etc. This field is optional and when it is missing, the
|
||||
driver code will use default data type.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
required:
|
||||
- event-name
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
// PPMUv1 nodes for Exynos3250 (although the board DTS defines events)
|
||||
#include <dt-bindings/clock/exynos3250.h>
|
||||
|
||||
ppmu_dmc0: ppmu@106a0000 {
|
||||
compatible = "samsung,exynos-ppmu";
|
||||
reg = <0x106a0000 0x2000>;
|
||||
|
||||
events {
|
||||
ppmu_dmc0_3: ppmu-event3-dmc0 {
|
||||
event-name = "ppmu-event3-dmc0";
|
||||
};
|
||||
|
||||
ppmu_dmc0_2: ppmu-event2-dmc0 {
|
||||
event-name = "ppmu-event2-dmc0";
|
||||
};
|
||||
|
||||
ppmu_dmc0_1: ppmu-event1-dmc0 {
|
||||
event-name = "ppmu-event1-dmc0";
|
||||
};
|
||||
|
||||
ppmu_dmc0_0: ppmu-event0-dmc0 {
|
||||
event-name = "ppmu-event0-dmc0";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ppmu_rightbus: ppmu@112a0000 {
|
||||
compatible = "samsung,exynos-ppmu";
|
||||
reg = <0x112a0000 0x2000>;
|
||||
clocks = <&cmu CLK_PPMURIGHT>;
|
||||
clock-names = "ppmu";
|
||||
|
||||
events {
|
||||
ppmu_rightbus_3: ppmu-event3-rightbus {
|
||||
event-name = "ppmu-event3-rightbus";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
// PPMUv2 nodes in Exynos5433
|
||||
ppmu_d0_cpu: ppmu@10480000 {
|
||||
compatible = "samsung,exynos-ppmu-v2";
|
||||
reg = <0x10480000 0x2000>;
|
||||
};
|
||||
|
||||
ppmu_d0_general: ppmu@10490000 {
|
||||
compatible = "samsung,exynos-ppmu-v2";
|
||||
reg = <0x10490000 0x2000>;
|
||||
|
||||
events {
|
||||
ppmu_event0_d0_general: ppmu-event0-d0-general {
|
||||
event-name = "ppmu-event0-d0-general";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ppmu_d0_rt: ppmu@104a0000 {
|
||||
compatible = "samsung,exynos-ppmu-v2";
|
||||
reg = <0x104a0000 0x2000>;
|
||||
};
|
||||
|
||||
ppmu_d1_cpu: ppmu@104b0000 {
|
||||
compatible = "samsung,exynos-ppmu-v2";
|
||||
reg = <0x104b0000 0x2000>;
|
||||
};
|
||||
|
||||
ppmu_d1_general: ppmu@104c0000 {
|
||||
compatible = "samsung,exynos-ppmu-v2";
|
||||
reg = <0x104c0000 0x2000>;
|
||||
};
|
||||
|
||||
ppmu_d1_rt: ppmu@104d0000 {
|
||||
compatible = "samsung,exynos-ppmu-v2";
|
||||
reg = <0x104d0000 0x2000>;
|
||||
};
|
||||
|
||||
- |
|
||||
// PPMUv1 nodes with event-data-type for Exynos4412
|
||||
#include <dt-bindings/pmu/exynos_ppmu.h>
|
||||
|
||||
ppmu@106a0000 {
|
||||
compatible = "samsung,exynos-ppmu";
|
||||
reg = <0x106a0000 0x2000>;
|
||||
clocks = <&clock 400>;
|
||||
clock-names = "ppmu";
|
||||
|
||||
events {
|
||||
ppmu-event3-dmc0 {
|
||||
event-name = "ppmu-event3-dmc0";
|
||||
event-data-type = <(PPMU_RO_DATA_CNT |
|
||||
PPMU_WO_DATA_CNT)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -8,7 +8,7 @@ Required properties:
|
||||
- clocks: Phandles for clock specified in "clock-names" property
|
||||
- clock-names : The name of clock used by the DFI, must be
|
||||
"pclk_ddr_mon";
|
||||
- operating-points-v2: Refer to Documentation/devicetree/bindings/opp/opp.txt
|
||||
- operating-points-v2: Refer to Documentation/devicetree/bindings/opp/opp-v2.yaml
|
||||
for details.
|
||||
- center-supply: DMC supply node.
|
||||
- status: Marks the node enabled/disabled.
|
||||
|
||||
@ -174,7 +174,6 @@ examples:
|
||||
phy-names = "phy";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmi_pins>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
@ -233,7 +232,6 @@ examples:
|
||||
phy-names = "phy";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmi_pins>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
|
||||
@ -22,6 +22,9 @@ properties:
|
||||
- ti,ths8134a
|
||||
- ti,ths8134b
|
||||
- const: ti,ths8134
|
||||
- items:
|
||||
- const: corpro,gm7123
|
||||
- const: adi,adv7123
|
||||
- enum:
|
||||
- adi,adv7123
|
||||
- dumb-vga-dac
|
||||
|
||||
@ -37,7 +37,8 @@ properties:
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
$ref: /schemas/graph.yaml#/$defs/port-base
|
||||
unevaluatedProperties: false
|
||||
description: Video port for MIPI DSI Channel-A input
|
||||
|
||||
properties:
|
||||
@ -49,7 +50,6 @@ properties:
|
||||
data-lanes:
|
||||
description: array of physical DSI data lane indexes.
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
items:
|
||||
- const: 1
|
||||
- const: 2
|
||||
@ -57,7 +57,8 @@ properties:
|
||||
- const: 4
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
$ref: /schemas/graph.yaml#/$defs/port-base
|
||||
unevaluatedProperties: false
|
||||
description: Video port for MIPI DSI Channel-B input
|
||||
|
||||
properties:
|
||||
@ -69,7 +70,6 @@ properties:
|
||||
data-lanes:
|
||||
description: array of physical DSI data lane indexes.
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
items:
|
||||
- const: 1
|
||||
- const: 2
|
||||
|
||||
@ -18,7 +18,7 @@ properties:
|
||||
const: ti,sn65dsi86
|
||||
|
||||
reg:
|
||||
const: 0x2d
|
||||
enum: [ 0x2c, 0x2d ]
|
||||
|
||||
enable-gpios:
|
||||
maxItems: 1
|
||||
@ -70,6 +70,9 @@ properties:
|
||||
const: 1
|
||||
description: See ../../pwm/pwm.yaml for description of the cell formats.
|
||||
|
||||
aux-bus:
|
||||
$ref: /schemas/display/dp-aux-bus.yaml#
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
@ -150,7 +153,6 @@ properties:
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- enable-gpios
|
||||
- vccio-supply
|
||||
- vpll-supply
|
||||
- vcca-supply
|
||||
@ -201,11 +203,26 @@ examples:
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
endpoint {
|
||||
sn65dsi86_out: endpoint {
|
||||
remote-endpoint = <&panel_in_edp>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
aux-bus {
|
||||
panel {
|
||||
compatible = "boe,nv133fhm-n62";
|
||||
power-supply = <&pp3300_dx_edp>;
|
||||
backlight = <&backlight>;
|
||||
hpd-gpios = <&sn65dsi86_bridge 2 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
port {
|
||||
panel_in_edp: endpoint {
|
||||
remote-endpoint = <&sn65dsi86_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
- |
|
||||
|
||||
37
sys/contrib/device-tree/Bindings/display/dp-aux-bus.yaml
Normal file
37
sys/contrib/device-tree/Bindings/display/dp-aux-bus.yaml
Normal file
@ -0,0 +1,37 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/dp-aux-bus.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: DisplayPort AUX bus
|
||||
|
||||
maintainers:
|
||||
- Douglas Anderson <dianders@chromium.org>
|
||||
|
||||
description:
|
||||
DisplayPort controllers provide a control channel to the sinks that
|
||||
are hooked up to them. This is the DP AUX bus. Over the DP AUX bus
|
||||
we can query properties about a sink and also configure it. In
|
||||
particular, DP sinks support DDC over DP AUX which allows tunneling
|
||||
a standard I2C DDC connection over the AUX channel.
|
||||
|
||||
To model this relationship, DP sinks should be placed as children
|
||||
of the DP controller under the "aux-bus" node.
|
||||
|
||||
At the moment, this binding only handles the eDP case. It is
|
||||
possible it will be extended in the future to handle the DP case.
|
||||
For DP, presumably a connector would be listed under the DP AUX
|
||||
bus instead of a panel.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: "aux-bus"
|
||||
|
||||
panel:
|
||||
$ref: panel/panel-common.yaml#
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- panel
|
||||
@ -27,6 +27,7 @@ properties:
|
||||
- fsl,imx6ul-lcdif
|
||||
- fsl,imx7d-lcdif
|
||||
- fsl,imx8mm-lcdif
|
||||
- fsl,imx8mn-lcdif
|
||||
- fsl,imx8mq-lcdif
|
||||
- const: fsl,imx6sx-lcdif
|
||||
|
||||
|
||||
@ -9,7 +9,7 @@ function block.
|
||||
|
||||
All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node.
|
||||
For a description of the MMSYS_CONFIG binding, see
|
||||
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt.
|
||||
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml.
|
||||
|
||||
DISP function blocks
|
||||
====================
|
||||
|
||||
@ -7,7 +7,7 @@ channel output.
|
||||
|
||||
Required properties:
|
||||
- compatible: "mediatek,<chip>-dsi"
|
||||
- the supported chips are mt2701, mt7623, mt8173 and mt8183.
|
||||
- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183.
|
||||
- reg: Physical base address and length of the controller's registers
|
||||
- interrupts: The interrupt signal from the function block.
|
||||
- clocks: device clocks
|
||||
|
||||
@ -64,6 +64,18 @@ properties:
|
||||
Indicates if the DSI controller is driving a panel which needs
|
||||
2 DSI links.
|
||||
|
||||
assigned-clocks:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
description: |
|
||||
Parents of "byte" and "pixel" for the given platform.
|
||||
|
||||
assigned-clock-parents:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
description: |
|
||||
The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block.
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
@ -77,7 +89,8 @@ properties:
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: "/schemas/graph.yaml#/properties/port"
|
||||
$ref: "/schemas/graph.yaml#/$defs/port-base"
|
||||
unevaluatedProperties: false
|
||||
description: |
|
||||
Input endpoints of the controller.
|
||||
properties:
|
||||
@ -92,7 +105,8 @@ properties:
|
||||
enum: [ 0, 1, 2, 3 ]
|
||||
|
||||
port@1:
|
||||
$ref: "/schemas/graph.yaml#/properties/port"
|
||||
$ref: "/schemas/graph.yaml#/$defs/port-base"
|
||||
unevaluatedProperties: false
|
||||
description: |
|
||||
Output endpoints of the controller.
|
||||
properties:
|
||||
@ -119,6 +133,8 @@ required:
|
||||
- clock-names
|
||||
- phys
|
||||
- phy-names
|
||||
- assigned-clocks
|
||||
- assigned-clock-parents
|
||||
- power-domains
|
||||
- operating-points-v2
|
||||
- ports
|
||||
@ -159,6 +175,9 @@ examples:
|
||||
phys = <&dsi0_phy>;
|
||||
phy-names = "dsi";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
|
||||
assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
|
||||
|
||||
power-domains = <&rpmhpd SC7180_CX>;
|
||||
operating-points-v2 = <&dsi_opp_table>;
|
||||
|
||||
|
||||
@ -14,9 +14,9 @@ allOf:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: qcom,dsi-phy-10nm
|
||||
- const: qcom,dsi-phy-10nm-8998
|
||||
enum:
|
||||
- qcom,dsi-phy-10nm
|
||||
- qcom,dsi-phy-10nm-8998
|
||||
|
||||
reg:
|
||||
items:
|
||||
|
||||
@ -14,9 +14,9 @@ allOf:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: qcom,dsi-phy-14nm
|
||||
- const: qcom,dsi-phy-14nm-660
|
||||
enum:
|
||||
- qcom,dsi-phy-14nm
|
||||
- qcom,dsi-phy-14nm-660
|
||||
|
||||
reg:
|
||||
items:
|
||||
|
||||
@ -14,8 +14,7 @@ allOf:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: qcom,dsi-phy-20nm
|
||||
const: qcom,dsi-phy-20nm
|
||||
|
||||
reg:
|
||||
items:
|
||||
|
||||
@ -14,10 +14,10 @@ allOf:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: qcom,dsi-phy-28nm-hpm
|
||||
- const: qcom,dsi-phy-28nm-lp
|
||||
- const: qcom,dsi-phy-28nm-8960
|
||||
enum:
|
||||
- qcom,dsi-phy-28nm-hpm
|
||||
- qcom,dsi-phy-28nm-lp
|
||||
- qcom,dsi-phy-28nm-8960
|
||||
|
||||
reg:
|
||||
items:
|
||||
|
||||
@ -0,0 +1,72 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dsi-phy-7nm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DSI 7nm PHY
|
||||
|
||||
maintainers:
|
||||
- Jonathan Marek <jonathan@marek.ca>
|
||||
|
||||
allOf:
|
||||
- $ref: dsi-phy-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,dsi-phy-7nm
|
||||
- qcom,dsi-phy-7nm-8150
|
||||
- qcom,sc7280-dsi-phy-7nm
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: dsi phy register set
|
||||
- description: dsi phy lane register set
|
||||
- description: dsi pll register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: dsi_phy
|
||||
- const: dsi_phy_lane
|
||||
- const: dsi_pll
|
||||
|
||||
vdds-supply:
|
||||
description: |
|
||||
Connected to VDD_A_DSI_PLL_0P9 pin (or VDDA_DSI{0,1}_PLL_0P9 for sm8150)
|
||||
|
||||
phy-type:
|
||||
description: D-PHY (default) or C-PHY mode
|
||||
enum: [ 10, 11 ]
|
||||
default: 10
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- vdds-supply
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sm8250.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
|
||||
dsi-phy@ae94400 {
|
||||
compatible = "qcom,dsi-phy-7nm";
|
||||
reg = <0x0ae94400 0x200>,
|
||||
<0x0ae94600 0x280>,
|
||||
<0x0ae94900 0x260>;
|
||||
reg-names = "dsi_phy",
|
||||
"dsi_phy_lane",
|
||||
"dsi_pll";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
vdds-supply = <&vreg_l5a_0p88>;
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
};
|
||||
@ -70,7 +70,6 @@ examples:
|
||||
avee-supply = <&ppvarp_lcd>;
|
||||
pp1800-supply = <&pp1800_lcd>;
|
||||
backlight = <&backlight_lcd0>;
|
||||
status = "okay";
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&dsi_out>;
|
||||
|
||||
@ -0,0 +1,78 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/panel/ilitek,ili9341.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Ilitek-9341 Display Panel
|
||||
|
||||
maintainers:
|
||||
- Dillon Min <dillon.minfei@gmail.com>
|
||||
|
||||
description: |
|
||||
Ilitek ILI9341 TFT panel driver with SPI control bus
|
||||
This is a driver for 320x240 TFT panels, accepting a rgb input
|
||||
streams with 16 bits or 18 bits.
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
# ili9341 240*320 Color on stm32f429-disco board
|
||||
- st,sf-tc240t-9370-t
|
||||
- const: ilitek,ili9341
|
||||
|
||||
reg: true
|
||||
|
||||
dc-gpios:
|
||||
maxItems: 1
|
||||
description: Display data/command selection (D/CX) of this DBI panel
|
||||
|
||||
spi-3wire: true
|
||||
|
||||
spi-max-frequency:
|
||||
const: 10000000
|
||||
|
||||
port: true
|
||||
|
||||
vci-supply:
|
||||
description: Analog voltage supply (2.5 .. 3.3V)
|
||||
|
||||
vddi-supply:
|
||||
description: Voltage supply for interface logic (1.65 .. 3.3 V)
|
||||
|
||||
vddi-led-supply:
|
||||
description: Voltage supply for the LED driver (1.65 .. 3.3 V)
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- dc-gpios
|
||||
- port
|
||||
|
||||
examples:
|
||||
- |+
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
panel: display@0 {
|
||||
compatible = "st,sf-tc240t-9370-t",
|
||||
"ilitek,ili9341";
|
||||
reg = <0>;
|
||||
spi-3wire;
|
||||
spi-max-frequency = <10000000>;
|
||||
dc-gpios = <&gpiod 13 0>;
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&display_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
|
||||
@ -0,0 +1,62 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/panel/innolux,ej030na.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Innolux EJ030NA 3.0" (320x480 pixels) 24-bit TFT LCD panel
|
||||
|
||||
description: |
|
||||
The panel must obey the rules for a SPI slave device as specified in
|
||||
spi/spi-controller.yaml
|
||||
|
||||
maintainers:
|
||||
- Paul Cercueil <paul@crapouillou.net>
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: innolux,ej030na
|
||||
|
||||
backlight: true
|
||||
port: true
|
||||
power-supply: true
|
||||
reg: true
|
||||
reset-gpios: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- power-supply
|
||||
- reset-gpios
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
panel@0 {
|
||||
compatible = "innolux,ej030na";
|
||||
reg = <0>;
|
||||
|
||||
spi-max-frequency = <10000000>;
|
||||
|
||||
reset-gpios = <&gpe 4 GPIO_ACTIVE_LOW>;
|
||||
power-supply = <&lcd_power>;
|
||||
|
||||
backlight = <&backlight>;
|
||||
|
||||
port {
|
||||
panel_input: endpoint {
|
||||
remote-endpoint = <&panel_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -46,9 +46,13 @@ properties:
|
||||
# AU Optronics Corporation 11.6" HD (1366x768) color TFT-LCD panel
|
||||
- auo,b116xw03
|
||||
# AU Optronics Corporation 13.3" FHD (1920x1080) color TFT-LCD panel
|
||||
- auo,b133han05
|
||||
# AU Optronics Corporation 13.3" FHD (1920x1080) color TFT-LCD panel
|
||||
- auo,b133htn01
|
||||
# AU Optronics Corporation 13.3" WXGA (1366x768) TFT LCD panel
|
||||
- auo,b133xtn01
|
||||
# AU Optronics Corporation 14.0" FHD (1920x1080) color TFT-LCD panel
|
||||
- auo,b140han06
|
||||
# AU Optronics Corporation 7.0" FHD (800 x 480) TFT LCD panel
|
||||
- auo,g070vvn01
|
||||
# AU Optronics Corporation 10.1" (1280x800) color TFT LCD panel
|
||||
@ -110,6 +114,9 @@ properties:
|
||||
# Emerging Display Technology Corp. 5.7" VGA TFT LCD panel
|
||||
- edt,et057090dhu
|
||||
- edt,et070080dh6
|
||||
# Emerging Display Technology Corp. 3.5" WVGA TFT LCD panel with
|
||||
# capacitive multitouch
|
||||
- edt,etm0350g0dh6
|
||||
# Emerging Display Technology Corp. 480x272 TFT Display with capacitive touch
|
||||
- edt,etm043080dh6gp
|
||||
# Emerging Display Technology Corp. 480x272 TFT Display
|
||||
@ -128,6 +135,11 @@ properties:
|
||||
# Emerging Display Technology Corp. WVGA TFT Display with capacitive touch
|
||||
- edt,etm0700g0dh6
|
||||
- edt,etm0700g0edh6
|
||||
# Emerging Display Technology Corp. 5.7" VGA TFT LCD panel with
|
||||
# capacitive touch
|
||||
- edt,etmv570g2dhu
|
||||
# E Ink VB3300-KCA
|
||||
- eink,vb3300-kca
|
||||
# Evervision Electronics Co. Ltd. VGG804821 5.0" WVGA TFT LCD Panel
|
||||
- evervision,vgg804821
|
||||
# Foxlink Group 5" WVGA TFT LCD panel
|
||||
@ -202,8 +214,14 @@ properties:
|
||||
- logictechno,lt161010-2nhr
|
||||
# Logic Technologies LT170410-2WHC 10.1" 1280x800 IPS TFT Cap Touch Mod.
|
||||
- logictechno,lt170410-2whc
|
||||
# Logic Technologies LTTD800x480 L2RT 7" 800x480 TFT Resistive Touch Module
|
||||
- logictechno,lttd800480070-l2rt
|
||||
# Logic Technologies LTTD800480070-L6WH-RT 7” 800x480 TFT Resistive Touch Module
|
||||
- logictechno,lttd800480070-l6wh-rt
|
||||
# Mitsubishi "AA070MC01 7.0" WVGA TFT LCD panel
|
||||
- mitsubishi,aa070mc01-ca1
|
||||
# Multi-Inno Technology Co.,Ltd MI1010AIT-1CP 10.1" 1280x800 LVDS IPS Cap Touch Mod.
|
||||
- multi-inno,mi1010ait-1cp
|
||||
# NEC LCD Technologies, Ltd. 12.1" WXGA (1280x800) LVDS TFT LCD panel
|
||||
- nec,nl12880bc20-05
|
||||
# NEC LCD Technologies,Ltd. WQVGA TFT LCD panel
|
||||
@ -238,10 +256,14 @@ properties:
|
||||
- powertip,ph800480t013-idf02
|
||||
# QiaoDian XianShi Corporation 4"3 TFT LCD panel
|
||||
- qiaodian,qd43003c0-40
|
||||
# Shenzhen QiShenglong Industrialist Co., Ltd. Gopher 2b 4.3" 480(RGB)x272 TFT LCD panel
|
||||
- qishenglong,gopher2b-lcd
|
||||
# Rocktech Displays Ltd. RK101II01D-CT 10.1" TFT 1280x800
|
||||
- rocktech,rk101ii01d-ct
|
||||
# Rocktech Display Ltd. RK070ER9427 800(RGB)x480 TFT LCD panel
|
||||
- rocktech,rk070er9427
|
||||
# Samsung 13.3" FHD (1920x1080 pixels) eDP AMOLED panel
|
||||
- samsung,atna33xc20
|
||||
# Samsung 12.2" (2560x1600 pixels) TFT LCD panel
|
||||
- samsung,lsn122dl01-c01
|
||||
# Samsung Electronics 10.1" WSVGA TFT LCD panel
|
||||
@ -298,6 +320,8 @@ properties:
|
||||
enable-gpios: true
|
||||
port: true
|
||||
power-supply: true
|
||||
no-hpd: true
|
||||
hpd-gpios: true
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
|
||||
@ -0,0 +1,99 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/panel/samsung,lms380kf01.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung LMS380KF01 display panel
|
||||
|
||||
description: The LMS380KF01 is a 480x800 DPI display panel from Samsung Mobile
|
||||
Displays (SMD) utilizing the WideChips WS2401 display controller. It can be
|
||||
used with internal or external backlight control.
|
||||
The panel must obey the rules for a SPI slave device as specified in
|
||||
spi/spi-controller.yaml
|
||||
|
||||
maintainers:
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: samsung,lms380kf01
|
||||
|
||||
reg: true
|
||||
|
||||
interrupts:
|
||||
description: provides an optional ESD (electrostatic discharge)
|
||||
interrupt that signals abnormalities in the display hardware.
|
||||
This can also be raised for other reasons like erroneous
|
||||
configuration.
|
||||
maxItems: 1
|
||||
|
||||
reset-gpios: true
|
||||
|
||||
vci-supply:
|
||||
description: regulator that supplies the VCI analog voltage
|
||||
usually around 3.0 V
|
||||
|
||||
vccio-supply:
|
||||
description: regulator that supplies the VCCIO voltage usually
|
||||
around 1.8 V
|
||||
|
||||
backlight: true
|
||||
|
||||
spi-cpha: true
|
||||
|
||||
spi-cpol: true
|
||||
|
||||
spi-max-frequency:
|
||||
maximum: 1200000
|
||||
|
||||
port: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- spi-cpha
|
||||
- spi-cpol
|
||||
- port
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
spi {
|
||||
compatible = "spi-gpio";
|
||||
sck-gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
|
||||
miso-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
|
||||
mosi-gpios = <&gpio 2 GPIO_ACTIVE_HIGH>;
|
||||
cs-gpios = <&gpio 3 GPIO_ACTIVE_HIGH>;
|
||||
num-chipselects = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
panel@0 {
|
||||
compatible = "samsung,lms380kf01";
|
||||
spi-max-frequency = <1200000>;
|
||||
spi-cpha;
|
||||
spi-cpol;
|
||||
reg = <0>;
|
||||
vci-supply = <&lcd_3v0_reg>;
|
||||
vccio-supply = <&lcd_1v8_reg>;
|
||||
reset-gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <5 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&display_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@ -33,8 +33,11 @@ properties:
|
||||
|
||||
backlight: true
|
||||
|
||||
spi-cpha: true
|
||||
|
||||
spi-cpol: true
|
||||
|
||||
spi-max-frequency:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: inherited as a SPI client node, the datasheet specifies
|
||||
maximum 300 ns minimum cycle which gives around 3 MHz max frequency
|
||||
maximum: 3000000
|
||||
@ -44,6 +47,9 @@ properties:
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- spi-cpha
|
||||
- spi-cpol
|
||||
- port
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
@ -52,15 +58,23 @@ examples:
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
spi {
|
||||
compatible = "spi-gpio";
|
||||
sck-gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
|
||||
miso-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
|
||||
mosi-gpios = <&gpio 2 GPIO_ACTIVE_HIGH>;
|
||||
cs-gpios = <&gpio 3 GPIO_ACTIVE_HIGH>;
|
||||
num-chipselects = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
panel@0 {
|
||||
compatible = "samsung,lms397kf04";
|
||||
spi-max-frequency = <3000000>;
|
||||
spi-cpha;
|
||||
spi-cpol;
|
||||
reg = <0>;
|
||||
vci-supply = <&lcd_3v0_reg>;
|
||||
vccio-supply = <&lcd_1v8_reg>;
|
||||
reset-gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
|
||||
reset-gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
|
||||
backlight = <&ktd259>;
|
||||
|
||||
port {
|
||||
|
||||
@ -23,6 +23,7 @@ Required properties:
|
||||
Optional properties:
|
||||
- phys: from general PHY binding: the phandle for the PHY device.
|
||||
- phy-names: Should be "dphy" if phys references an external phy.
|
||||
- #phy-cells: Defined when used as ISP phy, should be 0.
|
||||
- power-domains: a phandle to mipi dsi power domain node.
|
||||
- resets: list of phandle + reset specifier pairs, as described in [3].
|
||||
- reset-names: string reset name, must be "apb".
|
||||
|
||||
208
sys/contrib/device-tree/Bindings/display/solomon,ssd1307fb.yaml
Normal file
208
sys/contrib/device-tree/Bindings/display/solomon,ssd1307fb.yaml
Normal file
@ -0,0 +1,208 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/solomon,ssd1307fb.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Solomon SSD1307 OLED Controller Framebuffer
|
||||
|
||||
maintainers:
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- solomon,ssd1305fb-i2c
|
||||
- solomon,ssd1306fb-i2c
|
||||
- solomon,ssd1307fb-i2c
|
||||
- solomon,ssd1309fb-i2c
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
pwms:
|
||||
maxItems: 1
|
||||
|
||||
reset-gpios:
|
||||
maxItems: 1
|
||||
|
||||
vbat-supply:
|
||||
description: The supply for VBAT
|
||||
|
||||
solomon,height:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
default: 16
|
||||
description:
|
||||
Height in pixel of the screen driven by the controller
|
||||
|
||||
solomon,width:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
default: 96
|
||||
description:
|
||||
Width in pixel of the screen driven by the controller
|
||||
|
||||
solomon,page-offset:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
default: 1
|
||||
description:
|
||||
Offset of pages (band of 8 pixels) that the screen is mapped to
|
||||
|
||||
solomon,segment-no-remap:
|
||||
type: boolean
|
||||
description:
|
||||
Display needs normal (non-inverted) data column to segment mapping
|
||||
|
||||
solomon,col-offset:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
default: 0
|
||||
description:
|
||||
Offset of columns (COL/SEG) that the screen is mapped to
|
||||
|
||||
solomon,com-seq:
|
||||
type: boolean
|
||||
description:
|
||||
Display uses sequential COM pin configuration
|
||||
|
||||
solomon,com-lrremap:
|
||||
type: boolean
|
||||
description:
|
||||
Display uses left-right COM pin remap
|
||||
|
||||
solomon,com-invdir:
|
||||
type: boolean
|
||||
description:
|
||||
Display uses inverted COM pin scan direction
|
||||
|
||||
solomon,com-offset:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
default: 0
|
||||
description:
|
||||
Number of the COM pin wired to the first display line
|
||||
|
||||
solomon,prechargep1:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
default: 2
|
||||
description:
|
||||
Length of deselect period (phase 1) in clock cycles
|
||||
|
||||
solomon,prechargep2:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
default: 2
|
||||
description:
|
||||
Length of precharge period (phase 2) in clock cycles. This needs to be
|
||||
the higher, the higher the capacitance of the OLED's pixels is.
|
||||
|
||||
solomon,dclk-div:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 1
|
||||
maximum: 16
|
||||
description:
|
||||
Clock divisor. The default value is controller-dependent.
|
||||
|
||||
solomon,dclk-frq:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 15
|
||||
description:
|
||||
Clock frequency, higher value means higher frequency.
|
||||
The default value is controller-dependent.
|
||||
|
||||
solomon,lookup-table:
|
||||
$ref: /schemas/types.yaml#/definitions/uint8-array
|
||||
maxItems: 4
|
||||
description:
|
||||
8 bit value array of current drive pulse widths for BANK0, and colors A,
|
||||
B, and C. Each value in range of 31 to 63 for pulse widths of 32 to 64.
|
||||
Color D is always width 64.
|
||||
|
||||
solomon,area-color-enable:
|
||||
type: boolean
|
||||
description:
|
||||
Display uses color mode
|
||||
|
||||
solomon,low-power:
|
||||
type: boolean
|
||||
description:
|
||||
Display runs in low power mode
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: solomon,ssd1305fb-i2c
|
||||
then:
|
||||
properties:
|
||||
solomon,dclk-div:
|
||||
default: 1
|
||||
solomon,dclk-frq:
|
||||
default: 7
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: solomon,ssd1306fb-i2c
|
||||
then:
|
||||
properties:
|
||||
solomon,dclk-div:
|
||||
default: 1
|
||||
solomon,dclk-frq:
|
||||
default: 8
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: solomon,ssd1307fb-i2c
|
||||
then:
|
||||
properties:
|
||||
solomon,dclk-div:
|
||||
default: 2
|
||||
solomon,dclk-frq:
|
||||
default: 12
|
||||
required:
|
||||
- pwms
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: solomon,ssd1309fb-i2c
|
||||
then:
|
||||
properties:
|
||||
solomon,dclk-div:
|
||||
default: 1
|
||||
solomon,dclk-frq:
|
||||
default: 10
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
i2c1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ssd1307: oled@3c {
|
||||
compatible = "solomon,ssd1307fb-i2c";
|
||||
reg = <0x3c>;
|
||||
pwms = <&pwm 4 3000>;
|
||||
reset-gpios = <&gpio2 7>;
|
||||
};
|
||||
|
||||
ssd1306: oled@3d {
|
||||
compatible = "solomon,ssd1306fb-i2c";
|
||||
reg = <0x3c>;
|
||||
pwms = <&pwm 4 3000>;
|
||||
reset-gpios = <&gpio2 7>;
|
||||
solomon,com-lrremap;
|
||||
solomon,com-invdir;
|
||||
solomon,com-offset = <32>;
|
||||
solomon,lookup-table = /bits/ 8 <0x3f 0x3f 0x3f 0x3f>;
|
||||
};
|
||||
};
|
||||
@ -19,12 +19,12 @@ properties:
|
||||
description: The cell is the request line number.
|
||||
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: allwinner,sun6i-a31-dma
|
||||
- const: allwinner,sun8i-a23-dma
|
||||
- const: allwinner,sun8i-a83t-dma
|
||||
- const: allwinner,sun8i-h3-dma
|
||||
- const: allwinner,sun8i-v3s-dma
|
||||
enum:
|
||||
- allwinner,sun6i-a31-dma
|
||||
- allwinner,sun8i-a23-dma
|
||||
- allwinner,sun8i-a83t-dma
|
||||
- allwinner,sun8i-h3-dma
|
||||
- allwinner,sun8i-v3s-dma
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@ -24,13 +24,15 @@ properties:
|
||||
items:
|
||||
- description: Control and Status Register Slave Port
|
||||
- description: Descriptor Slave Port
|
||||
- description: Response Slave Port
|
||||
- description: Response Slave Port (Optional)
|
||||
minItems: 2
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: csr
|
||||
- const: desc
|
||||
- const: resp
|
||||
minItems: 2
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
@ -9,6 +9,7 @@ Required properties:
|
||||
"fsl,imx53-sdma"
|
||||
"fsl,imx6q-sdma"
|
||||
"fsl,imx7d-sdma"
|
||||
"fsl,imx6ul-sdma"
|
||||
"fsl,imx8mq-sdma"
|
||||
"fsl,imx8mm-sdma"
|
||||
"fsl,imx8mn-sdma"
|
||||
|
||||
130
sys/contrib/device-tree/Bindings/dma/renesas,rz-dmac.yaml
Normal file
130
sys/contrib/device-tree/Bindings/dma/renesas,rz-dmac.yaml
Normal file
@ -0,0 +1,130 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas RZ/G2L DMA Controller
|
||||
|
||||
maintainers:
|
||||
- Biju Das <biju.das.jz@bp.renesas.com>
|
||||
|
||||
allOf:
|
||||
- $ref: "dma-controller.yaml#"
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- renesas,r9a07g044-dmac # RZ/G2{L,LC}
|
||||
- const: renesas,rz-dmac
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Control and channel register block
|
||||
- description: DMA extended resource selector block
|
||||
|
||||
interrupts:
|
||||
maxItems: 17
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: error
|
||||
- const: ch0
|
||||
- const: ch1
|
||||
- const: ch2
|
||||
- const: ch3
|
||||
- const: ch4
|
||||
- const: ch5
|
||||
- const: ch6
|
||||
- const: ch7
|
||||
- const: ch8
|
||||
- const: ch9
|
||||
- const: ch10
|
||||
- const: ch11
|
||||
- const: ch12
|
||||
- const: ch13
|
||||
- const: ch14
|
||||
- const: ch15
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: DMA main clock
|
||||
- description: DMA register access clock
|
||||
|
||||
'#dma-cells':
|
||||
const: 1
|
||||
description:
|
||||
The cell specifies the encoded MID/RID values of the DMAC port
|
||||
connected to the DMA client and the slave channel configuration
|
||||
parameters.
|
||||
bits[0:9] - Specifies MID/RID value
|
||||
bit[10] - Specifies DMA request high enable (HIEN)
|
||||
bit[11] - Specifies DMA request detection type (LVL)
|
||||
bits[12:14] - Specifies DMAACK output mode (AM)
|
||||
bit[15] - Specifies Transfer Mode (TM)
|
||||
|
||||
dma-channels:
|
||||
const: 16
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
items:
|
||||
- description: Reset for DMA ARESETN reset terminal
|
||||
- description: Reset for DMA RST_ASYNC reset terminal
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
- clocks
|
||||
- '#dma-cells'
|
||||
- dma-channels
|
||||
- power-domains
|
||||
- resets
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/r9a07g044-cpg.h>
|
||||
|
||||
dmac: dma-controller@11820000 {
|
||||
compatible = "renesas,r9a07g044-dmac",
|
||||
"renesas,rz-dmac";
|
||||
reg = <0x11820000 0x10000>,
|
||||
<0x11830000 0x10000>;
|
||||
interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7",
|
||||
"ch8", "ch9", "ch10", "ch11",
|
||||
"ch12", "ch13", "ch14", "ch15";
|
||||
clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
|
||||
<&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
|
||||
power-domains = <&cpg>;
|
||||
resets = <&cpg R9A07G044_DMAC_ARESETN>,
|
||||
<&cpg R9A07G044_DMAC_RST_ASYNC>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <16>;
|
||||
};
|
||||
@ -40,6 +40,13 @@ description: |
|
||||
0x0: FIFO mode with threshold selectable with bit 0-1
|
||||
0x1: Direct mode: each DMA request immediately initiates a transfer
|
||||
from/to the memory, FIFO is bypassed.
|
||||
-bit 4: alternative DMA request/acknowledge protocol
|
||||
0x0: Use standard DMA ACK management, where ACK signal is maintained
|
||||
up to the removal of request and transfer completion
|
||||
0x1: Use alternative DMA ACK management, where ACK de-assertion does
|
||||
not wait for the de-assertion of the REQuest, ACK is only managed
|
||||
by transfer completion. This must only be used on channels
|
||||
managing transfers for STM32 USART/UART.
|
||||
|
||||
|
||||
maintainers:
|
||||
|
||||
@ -34,6 +34,10 @@ properties:
|
||||
- description: SCMI compliant firmware with ARM SMC/HVC transport
|
||||
items:
|
||||
- const: arm,scmi-smc
|
||||
- description: SCMI compliant firmware with SCMI Virtio transport.
|
||||
The virtio transport only supports a single device.
|
||||
items:
|
||||
- const: arm,scmi-virtio
|
||||
|
||||
interrupts:
|
||||
description:
|
||||
@ -172,6 +176,7 @@ patternProperties:
|
||||
Each sub-node represents a protocol supported. If the platform
|
||||
supports a dedicated communication channel for a particular protocol,
|
||||
then the corresponding transport properties must be present.
|
||||
The virtio transport does not support a dedicated communication channel.
|
||||
|
||||
properties:
|
||||
reg:
|
||||
@ -195,7 +200,6 @@ patternProperties:
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- shmem
|
||||
|
||||
if:
|
||||
properties:
|
||||
@ -209,6 +213,7 @@ then:
|
||||
|
||||
required:
|
||||
- mboxes
|
||||
- shmem
|
||||
|
||||
else:
|
||||
if:
|
||||
@ -219,6 +224,7 @@ else:
|
||||
then:
|
||||
required:
|
||||
- arm,smc-id
|
||||
- shmem
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -131,9 +131,9 @@ properties:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: arm,scpi-dvfs-clocks
|
||||
- const: arm,scpi-variable-clocks
|
||||
enum:
|
||||
- arm,scpi-dvfs-clocks
|
||||
- arm,scpi-variable-clocks
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
@ -0,0 +1,89 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Xilinx firmware driver
|
||||
|
||||
maintainers:
|
||||
- Nava kishore Manne <nava.manne@xilinx.com>
|
||||
|
||||
description: The zynqmp-firmware node describes the interface to platform
|
||||
firmware. ZynqMP has an interface to communicate with secure firmware.
|
||||
Firmware driver provides an interface to firmware APIs. Interface APIs
|
||||
can be used by any driver to communicate to PMUFW(Platform Management Unit).
|
||||
These requests include clock management, pin control, device control,
|
||||
power management service, FPGA service and other platform management
|
||||
services.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: For implementations complying for Zynq Ultrascale+ MPSoC.
|
||||
const: xlnx,zynqmp-firmware
|
||||
|
||||
- description: For implementations complying for Versal.
|
||||
const: xlnx,versal-firmware
|
||||
|
||||
method:
|
||||
description: |
|
||||
The method of calling the PM-API firmware layer.
|
||||
Permitted values are.
|
||||
- "smc" : SMC #0, following the SMCCC
|
||||
- "hvc" : HVC #0, following the SMCCC
|
||||
|
||||
$ref: /schemas/types.yaml#/definitions/string-array
|
||||
enum:
|
||||
- smc
|
||||
- hvc
|
||||
|
||||
versal_fpga:
|
||||
$ref: /schemas/fpga/xlnx,versal-fpga.yaml#
|
||||
description: Compatible of the FPGA device.
|
||||
type: object
|
||||
|
||||
zynqmp-aes:
|
||||
$ref: /schemas/crypto/xlnx,zynqmp-aes.yaml#
|
||||
description: The ZynqMP AES-GCM hardened cryptographic accelerator is
|
||||
used to encrypt or decrypt the data with provided key and initialization
|
||||
vector.
|
||||
type: object
|
||||
|
||||
clock-controller:
|
||||
$ref: /schemas/clock/xlnx,versal-clk.yaml#
|
||||
description: The clock controller is a hardware block of Xilinx versal
|
||||
clock tree. It reads required input clock frequencies from the devicetree
|
||||
and acts as clock provider for all clock consumers of PS clocks.list of
|
||||
clock specifiers which are external input clocks to the given clock
|
||||
controller.
|
||||
type: object
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
versal-firmware {
|
||||
compatible = "xlnx,versal-firmware";
|
||||
method = "smc";
|
||||
|
||||
versal_fpga: versal_fpga {
|
||||
compatible = "xlnx,versal-fpga";
|
||||
};
|
||||
|
||||
xlnx_aes: zynqmp-aes {
|
||||
compatible = "xlnx,zynqmp-aes";
|
||||
};
|
||||
|
||||
versal_clk: clock-controller {
|
||||
#clock-cells = <1>;
|
||||
compatible = "xlnx,versal-clk";
|
||||
clocks = <&ref>, <&alt_ref>, <&pl_alt_ref>;
|
||||
clock-names = "ref", "alt_ref", "pl_alt_ref";
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
33
sys/contrib/device-tree/Bindings/fpga/xlnx,versal-fpga.yaml
Normal file
33
sys/contrib/device-tree/Bindings/fpga/xlnx,versal-fpga.yaml
Normal file
@ -0,0 +1,33 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/fpga/xlnx,versal-fpga.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Xilinx Versal FPGA driver.
|
||||
|
||||
maintainers:
|
||||
- Nava kishore Manne <nava.manne@xilinx.com>
|
||||
|
||||
description: |
|
||||
Device Tree Versal FPGA bindings for the Versal SoC, controlled
|
||||
using firmware interface.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- xlnx,versal-fpga
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
versal_fpga: versal_fpga {
|
||||
compatible = "xlnx,versal-fpga";
|
||||
};
|
||||
|
||||
...
|
||||
@ -0,0 +1,36 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Xilinx Zynq Ultrascale MPSoC FPGA Manager Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Nava kishore Manne <navam@xilinx.com>
|
||||
|
||||
description: |
|
||||
Device Tree Bindings for Zynq Ultrascale MPSoC FPGA Manager.
|
||||
The ZynqMP SoC uses the PCAP (Processor Configuration Port) to
|
||||
configure the Programmable Logic (PL). The configuration uses the
|
||||
firmware interface.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: xlnx,zynqmp-pcap-fpga
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
firmware {
|
||||
zynqmp_firmware: zynqmp-firmware {
|
||||
zynqmp_pcap: pcap {
|
||||
compatible = "xlnx,zynqmp-pcap-fpga";
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -19,7 +19,6 @@ properties:
|
||||
compatible:
|
||||
enum:
|
||||
- ibm,fsi2spi
|
||||
- ibm,fsi2spi-restricted
|
||||
|
||||
reg:
|
||||
items:
|
||||
|
||||
77
sys/contrib/device-tree/Bindings/gpio/aspeed,sgpio.yaml
Normal file
77
sys/contrib/device-tree/Bindings/gpio/aspeed,sgpio.yaml
Normal file
@ -0,0 +1,77 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/gpio/aspeed,sgpio.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Aspeed SGPIO controller
|
||||
|
||||
maintainers:
|
||||
- Andrew Jeffery <andrew@aj.id.au>
|
||||
|
||||
description:
|
||||
This SGPIO controller is for ASPEED AST2400, AST2500 and AST2600 SoC,
|
||||
AST2600 have two sgpio master one with 128 pins another one with 80 pins,
|
||||
AST2500/AST2400 have one sgpio master with 80 pins. Each of the Serial
|
||||
GPIO pins can be programmed to support the following options
|
||||
- Support interrupt option for each input port and various interrupt
|
||||
sensitivity option (level-high, level-low, edge-high, edge-low)
|
||||
- Support reset tolerance option for each output port
|
||||
- Directly connected to APB bus and its shift clock is from APB bus clock
|
||||
divided by a programmable value.
|
||||
- Co-work with external signal-chained TTL components (74LV165/74LV595)
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- aspeed,ast2400-sgpio
|
||||
- aspeed,ast2500-sgpio
|
||||
- aspeed,ast2600-sgpiom
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
gpio-controller: true
|
||||
|
||||
'#gpio-cells':
|
||||
const: 2
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
ngpios: true
|
||||
|
||||
bus-frequency: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- gpio-controller
|
||||
- '#gpio-cells'
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- ngpios
|
||||
- clocks
|
||||
- bus-frequency
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/aspeed-clock.h>
|
||||
sgpio: sgpio@1e780200 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "aspeed,ast2500-sgpio";
|
||||
gpio-controller;
|
||||
interrupts = <40>;
|
||||
reg = <0x1e780200 0x0100>;
|
||||
clocks = <&syscon ASPEED_CLK_APB>;
|
||||
interrupt-controller;
|
||||
ngpios = <80>;
|
||||
bus-frequency = <12000000>;
|
||||
};
|
||||
59
sys/contrib/device-tree/Bindings/gpio/gpio-virtio.yaml
Normal file
59
sys/contrib/device-tree/Bindings/gpio/gpio-virtio.yaml
Normal file
@ -0,0 +1,59 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/gpio/gpio-virtio.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Virtio GPIO controller
|
||||
|
||||
maintainers:
|
||||
- Viresh Kumar <viresh.kumar@linaro.org>
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/virtio/virtio-device.yaml#
|
||||
|
||||
description:
|
||||
Virtio GPIO controller, see /schemas/virtio/virtio-device.yaml for more
|
||||
details.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: gpio
|
||||
|
||||
compatible:
|
||||
const: virtio,device29
|
||||
|
||||
gpio-controller: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
"#interrupt-cells":
|
||||
const: 2
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- gpio-controller
|
||||
- "#gpio-cells"
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
virtio@3000 {
|
||||
compatible = "virtio,mmio";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <41>;
|
||||
|
||||
gpio {
|
||||
compatible = "virtio,device29";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@ -22,7 +22,10 @@ properties:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
minItems: 1
|
||||
items:
|
||||
- description: APB interface clock source
|
||||
- description: GPIO debounce reference clock source
|
||||
|
||||
gpio-controller: true
|
||||
|
||||
|
||||
@ -20,6 +20,7 @@ properties:
|
||||
- mediatek,mt8183-mali
|
||||
- realtek,rtd1619-mali
|
||||
- rockchip,px30-mali
|
||||
- rockchip,rk3568-mali
|
||||
- const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable
|
||||
|
||||
reg:
|
||||
@ -136,7 +137,7 @@ examples:
|
||||
resets = <&reset 0>, <&reset 1>;
|
||||
};
|
||||
|
||||
gpu_opp_table: opp_table0 {
|
||||
gpu_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-533000000 {
|
||||
|
||||
@ -160,7 +160,7 @@ examples:
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
gpu_opp_table: opp_table0 {
|
||||
gpu_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-533000000 {
|
||||
|
||||
53
sys/contrib/device-tree/Bindings/hwmon/amd,sbrmi.yaml
Normal file
53
sys/contrib/device-tree/Bindings/hwmon/amd,sbrmi.yaml
Normal file
@ -0,0 +1,53 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/hwmon/amd,sbrmi.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: >
|
||||
Sideband Remote Management Interface (SB-RMI) compliant
|
||||
AMD SoC power device.
|
||||
|
||||
maintainers:
|
||||
- Akshay Gupta <Akshay.Gupta@amd.com>
|
||||
|
||||
description: |
|
||||
SB Remote Management Interface (SB-RMI) is an SMBus compatible
|
||||
interface that reports AMD SoC's Power (normalized Power) using,
|
||||
Mailbox Service Request and resembles a typical 8-pin remote power
|
||||
sensor's I2C interface to BMC. The power attributes in hwmon
|
||||
reports power in microwatts.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- amd,sbrmi
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
description: |
|
||||
I2C bus address of the device as specified in Section SBI SMBus Address
|
||||
of the SoC register reference. The SB-RMI address is normally 78h for
|
||||
socket 0 and 70h for socket 1, but it could vary based on hardware
|
||||
address select pins.
|
||||
\[open source SoC register reference\]
|
||||
https://www.amd.com/en/support/tech-docs?keyword=55898
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
i2c0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
sbrmi@3c {
|
||||
compatible = "amd,sbrmi";
|
||||
reg = <0x3c>;
|
||||
};
|
||||
};
|
||||
...
|
||||
41
sys/contrib/device-tree/Bindings/hwmon/winbond,w83781d.yaml
Normal file
41
sys/contrib/device-tree/Bindings/hwmon/winbond,w83781d.yaml
Normal file
@ -0,0 +1,41 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
|
||||
$id: http://devicetree.org/schemas/hwmon/winbond,w83781d.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Winbond W83781 and compatible hardware monitor IC
|
||||
|
||||
maintainers:
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- winbond,w83781d
|
||||
- winbond,w83781g
|
||||
- winbond,w83782d
|
||||
- winbond,w83783s
|
||||
- asus,as99127f
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
temperature-sensor@28 {
|
||||
compatible = "winbond,w83781d";
|
||||
reg = <0x28>;
|
||||
};
|
||||
};
|
||||
71
sys/contrib/device-tree/Bindings/i2c/brcm,iproc-i2c.yaml
Normal file
71
sys/contrib/device-tree/Bindings/i2c/brcm,iproc-i2c.yaml
Normal file
@ -0,0 +1,71 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/i2c/brcm,iproc-i2c.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom iProc I2C controller
|
||||
|
||||
maintainers:
|
||||
- Rafał Miłecki <rafal@milecki.pl>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- brcm,iproc-i2c
|
||||
- brcm,iproc-nic-i2c
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clock-frequency:
|
||||
enum: [ 100000, 400000 ]
|
||||
|
||||
interrupts:
|
||||
description: |
|
||||
Should contain the I2C interrupt. For certain revisions of the I2C
|
||||
controller, I2C interrupt is unwired to the interrupt controller. In such
|
||||
case, this property should be left unspecified, and driver will fall back
|
||||
to polling mode
|
||||
maxItems: 1
|
||||
|
||||
brcm,ape-hsls-addr-mask:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Host view of address mask into the 'APE' co-processor
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/i2c/i2c-controller.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: brcm,iproc-nic-i2c
|
||||
then:
|
||||
required:
|
||||
- brcm,ape-hsls-addr-mask
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- reg
|
||||
- clock-frequency
|
||||
- '#address-cells'
|
||||
- '#size-cells'
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
i2c@18008000 {
|
||||
compatible = "brcm,iproc-i2c";
|
||||
reg = <0x18008000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
|
||||
clock-frequency = <100000>;
|
||||
|
||||
wm8750@1a {
|
||||
compatible = "wlf,wm8750";
|
||||
reg = <0x1a>;
|
||||
};
|
||||
};
|
||||
51
sys/contrib/device-tree/Bindings/i2c/i2c-virtio.yaml
Normal file
51
sys/contrib/device-tree/Bindings/i2c/i2c-virtio.yaml
Normal file
@ -0,0 +1,51 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/i2c/i2c-virtio.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Virtio I2C Adapter
|
||||
|
||||
maintainers:
|
||||
- Viresh Kumar <viresh.kumar@linaro.org>
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/i2c/i2c-controller.yaml#
|
||||
- $ref: /schemas/virtio/virtio-device.yaml#
|
||||
|
||||
description:
|
||||
Virtio I2C device, see /schemas/virtio/virtio-device.yaml for more details.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: i2c
|
||||
|
||||
compatible:
|
||||
const: virtio,device22
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
virtio@3000 {
|
||||
compatible = "virtio,mmio";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <41>;
|
||||
|
||||
i2c {
|
||||
compatible = "virtio,device22";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
light-sensor@20 {
|
||||
compatible = "dynaimage,al3320a";
|
||||
reg = <0x20>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@ -27,14 +27,25 @@ properties:
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: Transmit End Interrupt (TEI)
|
||||
- description: Receive Data Full Interrupt (RI)
|
||||
- description: Transmit Data Empty Interrupt (TI)
|
||||
- description: Stop Condition Detection Interrupt (SPI)
|
||||
- description: Start Condition Detection Interrupt (STI)
|
||||
- description: NACK Reception Interrupt (NAKI)
|
||||
- description: Arbitration-Lost Interrupt (ALI)
|
||||
- description: Timeout Interrupt (TMOI)
|
||||
- description: Transmit End Interrupt
|
||||
- description: Receive Data Full Interrupt
|
||||
- description: Transmit Data Empty Interrupt
|
||||
- description: Stop Condition Detection Interrupt
|
||||
- description: Start Condition Detection Interrupt
|
||||
- description: NACK Reception Interrupt
|
||||
- description: Arbitration-Lost Interrupt
|
||||
- description: Timeout Interrupt
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: tei
|
||||
- const: ri
|
||||
- const: ti
|
||||
- const: spi
|
||||
- const: sti
|
||||
- const: naki
|
||||
- const: ali
|
||||
- const: tmoi
|
||||
|
||||
clock-frequency:
|
||||
description:
|
||||
@ -51,6 +62,7 @@ required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
- clocks
|
||||
- clock-frequency
|
||||
- power-domains
|
||||
@ -85,6 +97,8 @@ examples:
|
||||
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tei", "ri", "ti", "spi", "sti", "naki", "ali",
|
||||
"tmoi";
|
||||
clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
|
||||
clock-frequency = <100000>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
|
||||
@ -72,11 +72,11 @@ additionalProperties: false
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: ti,omap2420-i2c
|
||||
- const: ti,omap2430-i2c
|
||||
- const: ti,omap3-i2c
|
||||
- const: ti,omap4-i2c
|
||||
enum:
|
||||
- ti,omap2420-i2c
|
||||
- ti,omap2430-i2c
|
||||
- ti,omap3-i2c
|
||||
- ti,omap4-i2c
|
||||
|
||||
then:
|
||||
properties:
|
||||
|
||||
@ -8,6 +8,7 @@ title: Bosch BMA255 and Similar Accelerometers
|
||||
|
||||
maintainers:
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
- Stephan Gerhold <stephan@gerhold.net>
|
||||
|
||||
description:
|
||||
3 axis accelerometers with varying range and I2C or SPI
|
||||
@ -16,15 +17,24 @@ description:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- bosch,bmc150_accel
|
||||
- bosch,bmi055_accel
|
||||
# bmc150-accel driver in Linux
|
||||
- bosch,bma222
|
||||
- bosch,bma222e
|
||||
- bosch,bma250e
|
||||
- bosch,bma253
|
||||
- bosch,bma254
|
||||
- bosch,bma255
|
||||
- bosch,bma250e
|
||||
- bosch,bma222
|
||||
- bosch,bma222e
|
||||
- bosch,bma280
|
||||
- bosch,bmc150_accel
|
||||
- bosch,bmc156_accel
|
||||
- bosch,bmi055_accel
|
||||
|
||||
# bma180 driver in Linux
|
||||
- bosch,bma023
|
||||
- bosch,bma150
|
||||
- bosch,bma180
|
||||
- bosch,bma250
|
||||
- bosch,smb380
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@ -36,9 +46,21 @@ properties:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
description: |
|
||||
The first interrupt listed must be the one connected to the INT1 pin,
|
||||
the second (optional) interrupt listed must be the one connected to the
|
||||
INT2 pin (if available).
|
||||
Without interrupt-names, the first interrupt listed must be the one
|
||||
connected to the INT1 pin, the second (optional) interrupt listed must be
|
||||
the one connected to the INT2 pin (if available). The type should be
|
||||
IRQ_TYPE_EDGE_RISING.
|
||||
|
||||
BMC156 does not have an INT1 pin, therefore the first interrupt pin is
|
||||
always treated as INT2.
|
||||
|
||||
interrupt-names:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
items:
|
||||
enum:
|
||||
- INT1
|
||||
- INT2
|
||||
|
||||
mount-matrix:
|
||||
description: an optional 3x3 mounting rotation matrix.
|
||||
@ -63,7 +85,22 @@ examples:
|
||||
reg = <0x08>;
|
||||
vddio-supply = <&vddio>;
|
||||
vdd-supply = <&vdd>;
|
||||
interrupts = <57 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupts = <57 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "INT1";
|
||||
};
|
||||
};
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
accelerometer@10 {
|
||||
compatible = "bosch,bmc156_accel";
|
||||
reg = <0x10>;
|
||||
vddio-supply = <&vddio>;
|
||||
vdd-supply = <&vdd>;
|
||||
interrupts = <116 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "INT2";
|
||||
};
|
||||
};
|
||||
- |
|
||||
|
||||
@ -23,6 +23,8 @@ properties:
|
||||
enum:
|
||||
- ingenic,jz4725b-adc
|
||||
- ingenic,jz4740-adc
|
||||
- ingenic,jz4760-adc
|
||||
- ingenic,jz4760b-adc
|
||||
- ingenic,jz4770-adc
|
||||
|
||||
'#io-channel-cells':
|
||||
@ -43,6 +45,23 @@ properties:
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
ingenic,use-internal-divider:
|
||||
description:
|
||||
If present, battery voltage is read from the VBAT_IR pin, which has an
|
||||
internal 1/4 divider. If absent, it is read through the VBAT_ER pin,
|
||||
which does not have such a divider.
|
||||
type: boolean
|
||||
|
||||
if:
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: ingenic,jz4760b-adc
|
||||
then:
|
||||
properties:
|
||||
ingenic,use-internal-divider: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#io-channel-cells'
|
||||
|
||||
134
sys/contrib/device-tree/Bindings/iio/adc/renesas,rzg2l-adc.yaml
Normal file
134
sys/contrib/device-tree/Bindings/iio/adc/renesas,rzg2l-adc.yaml
Normal file
@ -0,0 +1,134 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/iio/adc/renesas,rzg2l-adc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas RZ/G2L ADC
|
||||
|
||||
maintainers:
|
||||
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
|
||||
|
||||
description: |
|
||||
A/D Converter block is a successive approximation analog-to-digital converter
|
||||
with a 12-bit accuracy. Up to eight analog input channels can be selected.
|
||||
Conversions can be performed in single or repeat mode. Result of the ADC is
|
||||
stored in a 32-bit data register corresponding to each channel.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- renesas,r9a07g044-adc # RZ/G2{L,LC}
|
||||
- const: renesas,rzg2l-adc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: converter clock
|
||||
- description: peripheral clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: adclk
|
||||
- const: pclk
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 2
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: presetn
|
||||
- const: adrst-n
|
||||
|
||||
'#address-cells':
|
||||
const: 1
|
||||
|
||||
'#size-cells':
|
||||
const: 0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- power-domains
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
patternProperties:
|
||||
"^channel@[0-7]$":
|
||||
$ref: "adc.yaml"
|
||||
type: object
|
||||
description: |
|
||||
Represents the external channels which are connected to the ADC.
|
||||
|
||||
properties:
|
||||
reg:
|
||||
description: |
|
||||
The channel number. It can have up to 8 channels numbered from 0 to 7.
|
||||
items:
|
||||
- minimum: 0
|
||||
maximum: 7
|
||||
|
||||
required:
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/r9a07g044-cpg.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
adc: adc@10059000 {
|
||||
compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc";
|
||||
reg = <0x10059000 0x400>;
|
||||
interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,
|
||||
<&cpg CPG_MOD R9A07G044_ADC_PCLK>;
|
||||
clock-names = "adclk", "pclk";
|
||||
power-domains = <&cpg>;
|
||||
resets = <&cpg R9A07G044_ADC_PRESETN>,
|
||||
<&cpg R9A07G044_ADC_ADRST_N>;
|
||||
reset-names = "presetn", "adrst-n";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
channel@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
channel@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
channel@2 {
|
||||
reg = <2>;
|
||||
};
|
||||
channel@3 {
|
||||
reg = <3>;
|
||||
};
|
||||
channel@4 {
|
||||
reg = <4>;
|
||||
};
|
||||
channel@5 {
|
||||
reg = <5>;
|
||||
};
|
||||
channel@6 {
|
||||
reg = <6>;
|
||||
};
|
||||
channel@7 {
|
||||
reg = <7>;
|
||||
};
|
||||
};
|
||||
@ -20,6 +20,7 @@ properties:
|
||||
- rockchip,px30-saradc
|
||||
- rockchip,rk3308-saradc
|
||||
- rockchip,rk3328-saradc
|
||||
- rockchip,rk3568-saradc
|
||||
- rockchip,rv1108-saradc
|
||||
- const: rockchip,rk3399-saradc
|
||||
|
||||
|
||||
268
sys/contrib/device-tree/Bindings/iio/dac/adi,ad5064.yaml
Normal file
268
sys/contrib/device-tree/Bindings/iio/dac/adi,ad5064.yaml
Normal file
@ -0,0 +1,268 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/iio/dac/adi,ad5064.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Analog Devices AD5064 and similar DACs
|
||||
|
||||
maintainers:
|
||||
- Lars-Peter Clausen <lars@metafoo.de>
|
||||
- Jonathan Cameron <jic23@kernel.org>
|
||||
|
||||
description: |
|
||||
A range of similar DAC devices with between 1 and 12 channels. Some parts
|
||||
have internal references, others require a single shared external reference
|
||||
and the remainder have a separate reference pin for each DAC.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: I2C devics
|
||||
enum:
|
||||
- adi,ad5024
|
||||
- adi,ad5025
|
||||
- adi,ad5044
|
||||
- adi,ad5045
|
||||
- adi,ad5064
|
||||
- adi,ad5064-1
|
||||
- adi,ad5065
|
||||
- adi,ad5628-1
|
||||
- adi,ad5628-2
|
||||
- adi,ad5648-1
|
||||
- adi,ad5648-2
|
||||
- adi,ad5666-1
|
||||
- adi,ad5666-2
|
||||
- adi,ad5668-1
|
||||
- adi,ad5668-2
|
||||
- adi,ad5668-3
|
||||
- description: SPI devices
|
||||
enum:
|
||||
- adi,ad5625
|
||||
- adi,ad5625r-1v25
|
||||
- adi,ad5625r-2v5
|
||||
- adi,ad5627
|
||||
- adi,ad5627r-1v25
|
||||
- adi,ad5627r-2v5
|
||||
- adi,ad5629-1
|
||||
- adi,ad5629-2
|
||||
- adi,ad5629-3
|
||||
- adi,ad5645r-1v25
|
||||
- adi,ad5645r-2v5
|
||||
- adi,ad5665
|
||||
- adi,ad5665r-1v25
|
||||
- adi,ad5665r-2v5
|
||||
- adi,ad5667
|
||||
- adi,ad5667r-1v25
|
||||
- adi,ad5667r-2v5
|
||||
- adi,ad5669-1
|
||||
- adi,ad5669-2
|
||||
- adi,ad5669-3
|
||||
- lltc,ltc2606
|
||||
- lltc,ltc2607
|
||||
- lltc,ltc2609
|
||||
- lltc,ltc2616
|
||||
- lltc,ltc2617
|
||||
- lltc,ltc2619
|
||||
- lltc,ltc2626
|
||||
- lltc,ltc2627
|
||||
- lltc,ltc2629
|
||||
- lltc,ltc2631-l12
|
||||
- lltc,ltc2631-h12
|
||||
- lltc,ltc2631-l10
|
||||
- lltc,ltc2631-h10
|
||||
- lltc,ltc2631-l8
|
||||
- lltc,ltc2631-h8
|
||||
- lltc,ltc2633-l12
|
||||
- lltc,ltc2633-h12
|
||||
- lltc,ltc2633-l10
|
||||
- lltc,ltc2633-h10
|
||||
- lltc,ltc2633-l8
|
||||
- lltc,ltc2633-h8
|
||||
- lltc,ltc2635-l12
|
||||
- lltc,ltc2635-h12
|
||||
- lltc,ltc2635-l10
|
||||
- lltc,ltc2635-h10
|
||||
- lltc,ltc2635-l8
|
||||
- lltc,ltc2635-h8
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
vrefA-supply: true
|
||||
vrefB-supply: true
|
||||
vrefC-supply: true
|
||||
vrefD-supply: true
|
||||
vref-supply: true
|
||||
|
||||
spi-max-frequency: true
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
allOf:
|
||||
- # Shared external vref, no internal reference
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- adi,ad5064-1
|
||||
- adi,ad5625
|
||||
- adi,ad5627
|
||||
- adi,ad5665
|
||||
- adi,ad5667
|
||||
- lltc,ltc2606
|
||||
- lltc,ltc2607
|
||||
- lltc,ltc2616
|
||||
- lltc,ltc2617
|
||||
- lltc,ltc2626
|
||||
- lltc,ltc2627
|
||||
then:
|
||||
properties:
|
||||
vref-supply: true
|
||||
vrefA-supply: false
|
||||
vrefB-supply: false
|
||||
vrefC-supply: false
|
||||
vrefD-supply: false
|
||||
required:
|
||||
- vref-supply
|
||||
- # Shared external vref, internal reference available
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- adi,ad5625r-1v25
|
||||
- adi,ad5625r-2v5
|
||||
- adi,ad5627r-1v25
|
||||
- adi,ad5627r-2v5
|
||||
- adi,ad5628-1
|
||||
- adi,ad5628-2
|
||||
- adi,ad5629-1
|
||||
- adi,ad5629-2
|
||||
- adi,ad5629-3
|
||||
- adi,ad5645r-1v25
|
||||
- adi,ad5645r-2v5
|
||||
- adi,ad5647r-1v25
|
||||
- adi,ad5647r-2v5
|
||||
- adi,ad5648-1
|
||||
- adi,ad5648-2
|
||||
- adi,ad5665r-1v25
|
||||
- adi,ad5665r-2v5
|
||||
- adi,ad5666-1
|
||||
- adi,ad5666-2
|
||||
- adi,ad5667r-1v25
|
||||
- adi,ad5667r-2v5
|
||||
- adi,ad5668-1
|
||||
- adi,ad5668-2
|
||||
- adi,ad5668-3
|
||||
- adi,ad5669-1
|
||||
- adi,ad5669-2
|
||||
- adi,ad5669-3
|
||||
- lltc,ltc2631-l12
|
||||
- lltc,ltc2631-h12
|
||||
- lltc,ltc2631-l10
|
||||
- lltc,ltc2631-h10
|
||||
- lltc,ltc2631-l8
|
||||
- lltc,ltc2631-h8
|
||||
- lltc,ltc2633-l12
|
||||
- lltc,ltc2633-h12
|
||||
- lltc,ltc2633-l10
|
||||
- lltc,ltc2633-h10
|
||||
- lltc,ltc2633-l8
|
||||
- lltc,ltc2633-h8
|
||||
- lltc,ltc2635-l12
|
||||
- lltc,ltc2635-h12
|
||||
- lltc,ltc2635-l10
|
||||
- lltc,ltc2635-h10
|
||||
- lltc,ltc2635-l8
|
||||
- lltc,ltc2635-h8
|
||||
then:
|
||||
properties:
|
||||
vref-supply: true
|
||||
vrefA-supply: false
|
||||
vrefB-supply: false
|
||||
vrefC-supply: false
|
||||
vrefD-supply: false
|
||||
- # 4 input devices, separate vrefs, no internal reference
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- adi,ad5024
|
||||
- adi,ad5044
|
||||
- adi,ad5064
|
||||
- lltc,ltc2609
|
||||
- lltc,ltc2619
|
||||
- lltc,ltc2629
|
||||
then:
|
||||
properties:
|
||||
vrefA-supply: true
|
||||
vrefB-supply: true
|
||||
vrefC-supply: true
|
||||
vrefD-supply: true
|
||||
vref-supply: false
|
||||
required:
|
||||
- vrefA-supply
|
||||
- vrefB-supply
|
||||
- vrefC-supply
|
||||
- vrefD-supply
|
||||
- # 2 input devices, separate vrefs, no internal reference
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- adi,ad5025
|
||||
- adi,ad5045
|
||||
- adi,ad5065
|
||||
then:
|
||||
properties:
|
||||
vrefA-supply: true
|
||||
vrefB-supply: true
|
||||
vrefC-supply: false
|
||||
vrefD-supply: false
|
||||
vref-supply: false
|
||||
required:
|
||||
- vrefA-supply
|
||||
- vrefB-supply
|
||||
|
||||
examples:
|
||||
- |
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
dac@0 {
|
||||
reg = <0>;
|
||||
compatible = "adi,ad5625";
|
||||
vref-supply = <&dac_vref>;
|
||||
};
|
||||
};
|
||||
- |
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
dac@0 {
|
||||
reg = <0>;
|
||||
compatible = "adi,ad5625r-1v25";
|
||||
};
|
||||
};
|
||||
- |
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
dac@42 {
|
||||
reg = <0x42>;
|
||||
compatible = "adi,ad5024";
|
||||
vrefA-supply = <&dac_vref>;
|
||||
vrefB-supply = <&dac_vref>;
|
||||
vrefC-supply = <&dac_vref2>;
|
||||
vrefD-supply = <&dac_vref2>;
|
||||
};
|
||||
};
|
||||
...
|
||||
79
sys/contrib/device-tree/Bindings/iio/dac/adi,ad5360.yaml
Normal file
79
sys/contrib/device-tree/Bindings/iio/dac/adi,ad5360.yaml
Normal file
@ -0,0 +1,79 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/iio/dac/adi,ad5360.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Analog Devices AD5360 and similar DACs
|
||||
|
||||
maintainers:
|
||||
- Lars-Peter Clausen <lars@metafoo.de>
|
||||
- Jonathan Cameron <jic23@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- adi,ad5360
|
||||
- adi,ad5361
|
||||
- adi,ad5363
|
||||
- adi,ad5370
|
||||
- adi,ad5371
|
||||
- adi,ad5372
|
||||
- adi,ad5373
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
vref0-supply: true
|
||||
vref1-supply: true
|
||||
vref2-supply: true
|
||||
|
||||
spi-max-frequency: true
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- vref0-supply
|
||||
- vref1-supply
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- adi,ad5360
|
||||
- adi,ad5361
|
||||
- adi,ad5363
|
||||
- adi,ad5370
|
||||
- adi,ad5372
|
||||
- adi,ad5373
|
||||
then:
|
||||
properties:
|
||||
vref2-supply: false
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- adi,ad5371
|
||||
then:
|
||||
required:
|
||||
- vref2-supply
|
||||
|
||||
examples:
|
||||
- |
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
dac@0 {
|
||||
reg = <0>;
|
||||
compatible = "adi,ad5371";
|
||||
vref0-supply = <&dac_vref0>;
|
||||
vref1-supply = <&dac_vref1>;
|
||||
vref2-supply = <&dac_vref2>;
|
||||
};
|
||||
};
|
||||
...
|
||||
70
sys/contrib/device-tree/Bindings/iio/dac/adi,ad5380.yaml
Normal file
70
sys/contrib/device-tree/Bindings/iio/dac/adi,ad5380.yaml
Normal file
@ -0,0 +1,70 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/iio/dac/adi,ad5380.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Analog Devices AD5380 and similar DACs
|
||||
|
||||
maintainers:
|
||||
- Lars-Peter Clausen <lars@metafoo.de>
|
||||
- Jonathan Cameron <jic23@kernel.org>
|
||||
|
||||
description: |
|
||||
DAC devices supporting both SPI and I2C interfaces.
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- adi,ad5380-3
|
||||
- adi,ad5380-5
|
||||
- adi,ad5381-3
|
||||
- adi,ad5381-5
|
||||
- adi,ad5382-3
|
||||
- adi,ad5382-5
|
||||
- adi,ad5383-3
|
||||
- adi,ad5383-5
|
||||
- adi,ad5384-3
|
||||
- adi,ad5384-5
|
||||
- adi,ad5390-3
|
||||
- adi,ad5390-5
|
||||
- adi,ad5391-3
|
||||
- adi,ad5391-5
|
||||
- adi,ad5392-3
|
||||
- adi,ad5392-5
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
vref-supply:
|
||||
description:
|
||||
If not supplied devices will use internal regulators.
|
||||
|
||||
spi-max-frequency: true
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
examples:
|
||||
- |
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
dac@0 {
|
||||
reg = <0>;
|
||||
compatible = "adi,ad5390-5";
|
||||
vref-supply = <&dacvref>;
|
||||
};
|
||||
};
|
||||
- |
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
dac@42 {
|
||||
reg = <0x42>;
|
||||
compatible = "adi,ad5380-3";
|
||||
};
|
||||
};
|
||||
...
|
||||
51
sys/contrib/device-tree/Bindings/iio/dac/adi,ad5421.yaml
Normal file
51
sys/contrib/device-tree/Bindings/iio/dac/adi,ad5421.yaml
Normal file
@ -0,0 +1,51 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/iio/dac/adi,ad5421.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Analog Devices AD5421 DAC
|
||||
|
||||
maintainers:
|
||||
- Lars-Peter Clausen <lars@metafoo.de>
|
||||
- Jonathan Cameron <jic23@kernel.org>
|
||||
|
||||
description: |
|
||||
AD5421 is designed for us in loop-powered, 4 mA to 20 mA smart transmitter
|
||||
applications. It provides a 16-bit DAC, current amplifier, voltage regulator
|
||||
to drive the loop and a voltage reference.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: adi,ad5421
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
description: Fault signal.
|
||||
|
||||
spi-max-frequency: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
dac@0 {
|
||||
compatible = "adi,ad5421";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <30000000>;
|
||||
interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
...
|
||||
97
sys/contrib/device-tree/Bindings/iio/dac/adi,ad5449.yaml
Normal file
97
sys/contrib/device-tree/Bindings/iio/dac/adi,ad5449.yaml
Normal file
@ -0,0 +1,97 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/iio/dac/adi,ad5449.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Analog Devices AD5449 and similar DACs
|
||||
|
||||
maintainers:
|
||||
- Lars-Peter Clausen <lars@metafoo.de>
|
||||
- Jonathan Cameron <jic23@kernel.org>
|
||||
|
||||
description:
|
||||
Family of multiplying DACs from Analog Devices
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- adi,ad5415
|
||||
- adi,ad5426
|
||||
- adi,ad5429
|
||||
- adi,ad5432
|
||||
- adi,ad5439
|
||||
- adi,ad5443
|
||||
- adi,ad5449
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
spi-max-frequency: true
|
||||
|
||||
VREF-supply: true
|
||||
VREFA-supply: true
|
||||
VREFB-supply: true
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- adi,ad5415
|
||||
- adi,ad5426
|
||||
- adi,ad5432
|
||||
then:
|
||||
properties:
|
||||
VREF-supply: true
|
||||
VREFA-supply: false
|
||||
VREFB-supply: false
|
||||
required:
|
||||
- VREF-supply
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- adi,ad5429
|
||||
- adi,ad5439
|
||||
- adi,ad5449
|
||||
then:
|
||||
properties:
|
||||
VREF-supply: false
|
||||
VREFA-supply: true
|
||||
VREFB-supply: true
|
||||
required:
|
||||
- VREFA-supply
|
||||
- VREFB-supply
|
||||
|
||||
examples:
|
||||
- |
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
dac@0 {
|
||||
reg = <0>;
|
||||
compatible = "adi,ad5415";
|
||||
VREF-supply = <&dac_ref>;
|
||||
};
|
||||
};
|
||||
- |
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
dac@0 {
|
||||
reg = <0>;
|
||||
compatible = "adi,ad5429";
|
||||
VREFA-supply = <&dac_refA>;
|
||||
VREFB-supply = <&dac_refB>;
|
||||
};
|
||||
};
|
||||
...
|
||||
50
sys/contrib/device-tree/Bindings/iio/dac/adi,ad5504.yaml
Normal file
50
sys/contrib/device-tree/Bindings/iio/dac/adi,ad5504.yaml
Normal file
@ -0,0 +1,50 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/iio/dac/adi,ad5504.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Analog Devices AD5501 and AD5504 DACs
|
||||
|
||||
maintainers:
|
||||
- Lars-Peter Clausen <lars@metafoo.de>
|
||||
- Jonathan Cameron <jic23@kernel.org>
|
||||
|
||||
description:
|
||||
High voltage (up to 60V) DACs with temperature sensor alarm function
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- adi,ad5501
|
||||
- adi,ad5504
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
description: Used for temperature alarm.
|
||||
maxItems: 1
|
||||
|
||||
vcc-supply: true
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
dac@0 {
|
||||
reg = <0>;
|
||||
compatible = "adi,ad5504";
|
||||
vcc-supply = <&dac_vcc>;
|
||||
interrupts = <55 IRQ_TYPE_EDGE_FALLING>;
|
||||
};
|
||||
};
|
||||
...
|
||||
47
sys/contrib/device-tree/Bindings/iio/dac/adi,ad5624r.yaml
Normal file
47
sys/contrib/device-tree/Bindings/iio/dac/adi,ad5624r.yaml
Normal file
@ -0,0 +1,47 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/iio/dac/adi,ad5624r.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Analog Devices AD5624r and similar DACs
|
||||
|
||||
maintainers:
|
||||
- Jonathan Cameron <jic23@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- adi,ad5624r3
|
||||
- adi,ad5644r3
|
||||
- adi,ad5664r3
|
||||
- adi,ad5624r5
|
||||
- adi,ad5644r5
|
||||
- adi,ad5664r5
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
spi-max-frequency: true
|
||||
|
||||
vref-supply:
|
||||
description: If not present, internal reference will be used.
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
examples:
|
||||
- |
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
dac@0 {
|
||||
reg = <0>;
|
||||
compatible = "adi,ad5624r3";
|
||||
vref-supply = <&vref>;
|
||||
};
|
||||
};
|
||||
...
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user