AR9287 tidyups:
* Add an OS_A_REG_WRITE() routine - analog writes require a 100usec delay on AR9280 and later, so create a method to do it. * Use it for the AR9287 analog writes. * Re-indent and style(9) the code.
This commit is contained in:
Adrian Chadd
parent
1b86b1d21a
commit
3acbfe72fc
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=237184
@ -484,6 +484,8 @@ isBigEndian(void)
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/* Analog register writes may require a delay between each one (eg Merlin?) */
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#define OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \
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do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) ; OS_DELAY(100); } while (0)
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#define OS_A_REG_WRITE(_a, _r, _v) \
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do { OS_REG_WRITE(_a, _r, _v); OS_DELAY(100); } while (0)
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/* wait for the register contents to have the specified value */
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extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg,
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@ -45,70 +45,70 @@ static void
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ar9287SetPowerCalTable(struct ath_hal *ah,
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const struct ieee80211_channel *chan, int16_t *pTxPowerIndexOffset)
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{
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struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop;
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uint8_t *pCalBChans = NULL;
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uint16_t pdGainOverlap_t2;
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uint16_t numPiers = 0, i;
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uint16_t numXpdGain, xpdMask;
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uint16_t xpdGainValues[AR5416_NUM_PD_GAINS] = {0, 0, 0, 0};
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uint32_t regChainOffset;
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struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop;
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uint8_t *pCalBChans = NULL;
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uint16_t pdGainOverlap_t2;
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uint16_t numPiers = 0, i;
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uint16_t numXpdGain, xpdMask;
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uint16_t xpdGainValues[AR5416_NUM_PD_GAINS] = {0, 0, 0, 0};
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uint32_t regChainOffset;
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HAL_EEPROM_9287 *ee = AH_PRIVATE(ah)->ah_eeprom;
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struct ar9287_eeprom *pEepData = &ee->ee_base;
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struct ar9287_eeprom *pEepData = &ee->ee_base;
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xpdMask = pEepData->modalHeader.xpdGain;
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xpdMask = pEepData->modalHeader.xpdGain;
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if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >=
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AR9287_EEP_MINOR_VER_2)
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pdGainOverlap_t2 = pEepData->modalHeader.pdGainOverlap;
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else
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pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5),
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AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
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if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >=
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AR9287_EEP_MINOR_VER_2)
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pdGainOverlap_t2 = pEepData->modalHeader.pdGainOverlap;
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else
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pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5),
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AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
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/* Note: Kiwi should only be 2ghz.. */
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if (IEEE80211_IS_CHAN_2GHZ(chan)) {
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pCalBChans = pEepData->calFreqPier2G;
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numPiers = AR9287_NUM_2G_CAL_PIERS;
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pRawDatasetOpenLoop = (struct cal_data_op_loop_ar9287 *)pEepData->calPierData2G[0];
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AH5416(ah)->initPDADC = pRawDatasetOpenLoop->vpdPdg[0][0];
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}
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numXpdGain = 0;
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if (IEEE80211_IS_CHAN_2GHZ(chan)) {
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pCalBChans = pEepData->calFreqPier2G;
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numPiers = AR9287_NUM_2G_CAL_PIERS;
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pRawDatasetOpenLoop = (struct cal_data_op_loop_ar9287 *)pEepData->calPierData2G[0];
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AH5416(ah)->initPDADC = pRawDatasetOpenLoop->vpdPdg[0][0];
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}
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numXpdGain = 0;
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/* Calculate the value of xpdgains from the xpdGain Mask */
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for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
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if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
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if (numXpdGain >= AR5416_NUM_PD_GAINS)
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break;
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xpdGainValues[numXpdGain] =
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(uint16_t)(AR5416_PD_GAINS_IN_MASK-i);
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numXpdGain++;
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}
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}
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/* Calculate the value of xpdgains from the xpdGain Mask */
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for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
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if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
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if (numXpdGain >= AR5416_NUM_PD_GAINS)
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break;
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xpdGainValues[numXpdGain] =
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(uint16_t)(AR5416_PD_GAINS_IN_MASK-i);
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numXpdGain++;
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}
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}
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OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
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(numXpdGain - 1) & 0x3);
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OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
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xpdGainValues[0]);
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OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
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xpdGainValues[1]);
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OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
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xpdGainValues[2]);
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OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
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(numXpdGain - 1) & 0x3);
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OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
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xpdGainValues[0]);
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OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
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xpdGainValues[1]);
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OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
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xpdGainValues[2]);
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for (i = 0; i < AR9287_MAX_CHAINS; i++) {
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regChainOffset = i * 0x1000;
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for (i = 0; i < AR9287_MAX_CHAINS; i++) {
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regChainOffset = i * 0x1000;
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if (pEepData->baseEepHeader.txMask & (1 << i)) {
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int8_t txPower;
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pRawDatasetOpenLoop =
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(struct cal_data_op_loop_ar9287 *)pEepData->calPierData2G[i];
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ar9287olcGetTxGainIndex(ah, chan,
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pRawDatasetOpenLoop,
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pCalBChans, numPiers,
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&txPower);
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ar9287olcSetPDADCs(ah, txPower, i);
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}
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}
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if (pEepData->baseEepHeader.txMask & (1 << i)) {
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int8_t txPower;
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pRawDatasetOpenLoop =
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(struct cal_data_op_loop_ar9287 *)pEepData->calPierData2G[i];
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ar9287olcGetTxGainIndex(ah, chan,
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pRawDatasetOpenLoop,
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pCalBChans, numPiers,
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&txPower);
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ar9287olcSetPDADCs(ah, txPower, i);
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}
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}
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*pTxPowerIndexOffset = 0;
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*pTxPowerIndexOffset = 0;
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}
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@ -329,20 +329,20 @@ ar9287SetTransmitPower(struct ath_hal *ah,
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const struct ieee80211_channel *chan, uint16_t *rfXpdGain)
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{
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#define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
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#define N(a) (sizeof (a) / sizeof (a[0]))
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#define N(a) (sizeof (a) / sizeof (a[0]))
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const struct modal_eep_ar9287_header *pModal;
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struct ath_hal_5212 *ahp = AH5212(ah);
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int16_t ratesArray[Ar5416RateSize];
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int16_t txPowerIndexOffset = 0;
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uint8_t ht40PowerIncForPdadc = 2;
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int i;
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int16_t ratesArray[Ar5416RateSize];
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int16_t txPowerIndexOffset = 0;
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uint8_t ht40PowerIncForPdadc = 2;
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int i;
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uint16_t cfgCtl;
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uint16_t powerLimit;
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uint16_t twiceAntennaReduction;
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uint16_t twiceMaxRegulatoryPower;
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int16_t maxPower;
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uint16_t cfgCtl;
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uint16_t powerLimit;
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uint16_t twiceAntennaReduction;
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uint16_t twiceMaxRegulatoryPower;
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int16_t maxPower;
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HAL_EEPROM_9287 *ee = AH_PRIVATE(ah)->ah_eeprom;
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struct ar9287_eeprom *pEepData = &ee->ee_base;
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@ -351,7 +351,8 @@ ar9287SetTransmitPower(struct ath_hal *ah,
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cfgCtl = ath_hal_getctl(ah, chan);
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powerLimit = chan->ic_maxregpower * 2;
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twiceAntennaReduction = chan->ic_maxantgain;
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twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit);
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twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER,
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AH_PRIVATE(ah)->ah_powerLimit);
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pModal = &pEepData->modalHeader;
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HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n",
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__func__,chan->ic_freq, cfgCtl );
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@ -361,9 +362,9 @@ ar9287SetTransmitPower(struct ath_hal *ah,
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/* Fetch per-rate power table for the given channel */
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if (! ar9287SetPowerPerRateTable(ah, pEepData, chan,
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&ratesArray[0],cfgCtl,
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twiceAntennaReduction,
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twiceMaxRegulatoryPower, powerLimit)) {
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&ratesArray[0],cfgCtl,
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twiceAntennaReduction,
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twiceMaxRegulatoryPower, powerLimit)) {
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HALDEBUG(ah, HAL_DEBUG_ANY,
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"%s: unable to set tx power per rate table\n", __func__);
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return AH_FALSE;
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@ -476,7 +477,8 @@ ar9287SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
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pModal->antCtrlChain[i]);
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OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0) + regChainOffset,
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(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0) + regChainOffset)
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(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)
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+ regChainOffset)
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& ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
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AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
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SM(pModal->iqCalICh[i],
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@ -500,7 +502,6 @@ ar9287SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
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pModal->rxTxMarginCh[i]);
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}
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if (IEEE80211_IS_CHAN_HT40(chan))
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OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING,
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AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40);
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@ -539,8 +540,8 @@ ar9287SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
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SM(pModal->ob_qam, AR9287_AN_RF2G3_OB_QAM) |
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SM(pModal->ob_pal_off, AR9287_AN_RF2G3_OB_PAL_OFF));
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OS_REG_WRITE(ah, AR9287_AN_RF2G3_CH0, regval);
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OS_DELAY(100); /* analog write */
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/* Analog write - requires a 100usec delay */
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OS_A_REG_WRITE(ah, AR9287_AN_RF2G3_CH0, regval);
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regval = OS_REG_READ(ah, AR9287_AN_RF2G3_CH1);
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regval &= ~(AR9287_AN_RF2G3_DB1 |
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@ -556,8 +557,7 @@ ar9287SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
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SM(pModal->ob_qam, AR9287_AN_RF2G3_OB_QAM) |
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SM(pModal->ob_pal_off, AR9287_AN_RF2G3_OB_PAL_OFF));
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OS_REG_WRITE(ah, AR9287_AN_RF2G3_CH1, regval);
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OS_DELAY(100); /* analog write */
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OS_A_REG_WRITE(ah, AR9287_AN_RF2G3_CH1, regval);
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OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
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AR_PHY_TX_FRAME_TO_DATA_START, pModal->txFrameToDataStart);
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