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AR9287 tidyups:

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* Add an OS_A_REG_WRITE() routine - analog writes require a 100usec delay
  on AR9280 and later, so create a method to do it.

* Use it for the AR9287 analog writes.

* Re-indent and style(9) the code.
This commit is contained in:
Adrian Chadd 2012-06-17 05:56:27 +00:00
parent 1b86b1d21a
commit 3acbfe72fc
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=237184
2 changed files with 76 additions and 74 deletions
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2
sys/dev/ath/ath_hal/ah_internal.h
View File

@ -484,6 +484,8 @@ isBigEndian(void)
/* Analog register writes may require a delay between each one (eg Merlin?) */
#define OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \
do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) ; OS_DELAY(100); } while (0)
#define OS_A_REG_WRITE(_a, _r, _v) \
do { OS_REG_WRITE(_a, _r, _v); OS_DELAY(100); } while (0)
/* wait for the register contents to have the specified value */
extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg,

14
sys/dev/ath/ath_hal/ar9002/ar9287_reset.c
View File

@ -351,7 +351,8 @@ ar9287SetTransmitPower(struct ath_hal *ah,
cfgCtl = ath_hal_getctl(ah, chan);
powerLimit = chan->ic_maxregpower * 2;
twiceAntennaReduction = chan->ic_maxantgain;
twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit);
twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER,
AH_PRIVATE(ah)->ah_powerLimit);
pModal = &pEepData->modalHeader;
HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n",
__func__,chan->ic_freq, cfgCtl );
@ -476,7 +477,8 @@ ar9287SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
pModal->antCtrlChain[i]);
OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0) + regChainOffset,
(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0) + regChainOffset)
(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)
+ regChainOffset)
& ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
SM(pModal->iqCalICh[i],
@ -500,7 +502,6 @@ ar9287SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
pModal->rxTxMarginCh[i]);
}
if (IEEE80211_IS_CHAN_HT40(chan))
OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING,
AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40);
@ -539,8 +540,8 @@ ar9287SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
SM(pModal->ob_qam, AR9287_AN_RF2G3_OB_QAM) |
SM(pModal->ob_pal_off, AR9287_AN_RF2G3_OB_PAL_OFF));
OS_REG_WRITE(ah, AR9287_AN_RF2G3_CH0, regval);
OS_DELAY(100); /* analog write */
/* Analog write - requires a 100usec delay */
OS_A_REG_WRITE(ah, AR9287_AN_RF2G3_CH0, regval);
regval = OS_REG_READ(ah, AR9287_AN_RF2G3_CH1);
regval &= ~(AR9287_AN_RF2G3_DB1 |
@ -556,8 +557,7 @@ ar9287SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
SM(pModal->ob_qam, AR9287_AN_RF2G3_OB_QAM) |
SM(pModal->ob_pal_off, AR9287_AN_RF2G3_OB_PAL_OFF));
OS_REG_WRITE(ah, AR9287_AN_RF2G3_CH1, regval);
OS_DELAY(100); /* analog write */
OS_A_REG_WRITE(ah, AR9287_AN_RF2G3_CH1, regval);
OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
AR_PHY_TX_FRAME_TO_DATA_START, pModal->txFrameToDataStart);