a10_ehci: Remove the passby code
It doesn't seems to be needed anymore and this make ehci working again on the Pine64. Thanks to jmcneill@ for the help. Tested on: Pine64 (A64), OrangePi One (H3), BananapiM2 (A31s)
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8d94da2899
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449ed68efb
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=324563
@ -65,17 +65,10 @@ __FBSDID("$FreeBSD$");
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#define EHCI_HC_DEVSTR "Allwinner Integrated USB 2.0 controller"
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#define SW_USB_PMU_IRQ_ENABLE 0x800
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#define SW_SDRAM_REG_HPCR_USB1 (0x250 + ((1 << 2) * 4))
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#define SW_SDRAM_REG_HPCR_USB2 (0x250 + ((1 << 2) * 5))
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#define SW_SDRAM_BP_HPCR_ACCESS (1 << 0)
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#define SW_ULPI_BYPASS (1 << 0)
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#define SW_AHB_INCRX_ALIGN (1 << 8)
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#define SW_AHB_INCR4 (1 << 9)
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#define SW_AHB_INCR8 (1 << 10)
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#define USB_CONF(d) \
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(void *)ofw_bus_search_compatible((d), compat_data)->ocd_data
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@ -124,7 +117,7 @@ static struct ofw_compat_data compat_data[] = {
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{ "allwinner,sun7i-a20-ehci", (uintptr_t)&a10_ehci_conf },
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{ "allwinner,sun8i-a83t-ehci", (uintptr_t)&a31_ehci_conf },
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{ "allwinner,sun8i-h3-ehci", (uintptr_t)&a31_ehci_conf },
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/* { "allwinner,sun50i-a64-ehci", (uintptr_t)&a31_ehci_conf }, */
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{ "allwinner,sun50i-a64-ehci", (uintptr_t)&a31_ehci_conf },
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{ NULL, (uintptr_t)NULL }
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};
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@ -254,14 +247,6 @@ a10_ehci_attach(device_t self)
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}
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}
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/* Enable passby */
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reg_value = A10_READ_4(sc, SW_USB_PMU_IRQ_ENABLE);
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reg_value |= SW_AHB_INCR8; /* AHB INCR8 enable */
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reg_value |= SW_AHB_INCR4; /* AHB burst type INCR4 enable */
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reg_value |= SW_AHB_INCRX_ALIGN; /* AHB INCRX align enable */
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reg_value |= SW_ULPI_BYPASS; /* ULPI bypass enable */
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A10_WRITE_4(sc, SW_USB_PMU_IRQ_ENABLE, reg_value);
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/* Configure port */
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if (conf->sdram_init) {
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reg_value = A10_READ_4(sc, SW_SDRAM_REG_HPCR_USB2);
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@ -333,14 +318,6 @@ a10_ehci_detach(device_t self)
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A10_WRITE_4(sc, SW_SDRAM_REG_HPCR_USB2, reg_value);
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}
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/* Disable passby */
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reg_value = A10_READ_4(sc, SW_USB_PMU_IRQ_ENABLE);
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reg_value &= ~SW_AHB_INCR8; /* AHB INCR8 disable */
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reg_value &= ~SW_AHB_INCR4; /* AHB burst type INCR4 disable */
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reg_value &= ~SW_AHB_INCRX_ALIGN; /* AHB INCRX align disable */
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reg_value &= ~SW_ULPI_BYPASS; /* ULPI bypass disable */
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A10_WRITE_4(sc, SW_USB_PMU_IRQ_ENABLE, reg_value);
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/* Disable clock */
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TAILQ_FOREACH_SAFE(clk, &aw_sc->clk_list, next, clk_tmp) {
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err = clk_disable(clk->clk);
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