449ed68efb
It doesn't seems to be needed anymore and this make ehci working again on the Pine64. Thanks to jmcneill@ for the help. Tested on: Pine64 (A64), OrangePi One (H3), BananapiM2 (A31s)
368 lines
9.8 KiB
C
368 lines
9.8 KiB
C
/*-
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* Copyright (c) 2012 Ganbold Tsagaankhuu <ganbold@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Allwinner A10 attachment driver for the USB Enhanced Host Controller.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_bus.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/condvar.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <machine/bus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/usb/usb.h>
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#include <dev/usb/usbdi.h>
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#include <dev/usb/usb_core.h>
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#include <dev/usb/usb_busdma.h>
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#include <dev/usb/usb_process.h>
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#include <dev/usb/usb_util.h>
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#include <dev/usb/usb_controller.h>
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#include <dev/usb/usb_bus.h>
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#include <dev/usb/controller/ehci.h>
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#include <dev/usb/controller/ehcireg.h>
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#include <arm/allwinner/aw_machdep.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include <dev/extres/phy/phy.h>
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#define EHCI_HC_DEVSTR "Allwinner Integrated USB 2.0 controller"
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#define SW_SDRAM_REG_HPCR_USB1 (0x250 + ((1 << 2) * 4))
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#define SW_SDRAM_REG_HPCR_USB2 (0x250 + ((1 << 2) * 5))
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#define SW_SDRAM_BP_HPCR_ACCESS (1 << 0)
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#define USB_CONF(d) \
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(void *)ofw_bus_search_compatible((d), compat_data)->ocd_data
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#define A10_READ_4(sc, reg) \
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bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg)
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#define A10_WRITE_4(sc, reg, data) \
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bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data)
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static device_attach_t a10_ehci_attach;
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static device_detach_t a10_ehci_detach;
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struct clk_list {
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TAILQ_ENTRY(clk_list) next;
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clk_t clk;
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};
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struct hwrst_list {
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TAILQ_ENTRY(hwrst_list) next;
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hwreset_t rst;
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};
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struct aw_ehci_softc {
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ehci_softc_t sc;
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TAILQ_HEAD(, clk_list) clk_list;
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TAILQ_HEAD(, hwrst_list) rst_list;
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phy_t phy;
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};
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struct aw_ehci_conf {
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bool sdram_init;
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};
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static const struct aw_ehci_conf a10_ehci_conf = {
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.sdram_init = true,
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};
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static const struct aw_ehci_conf a31_ehci_conf = {
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.sdram_init = false,
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};
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static struct ofw_compat_data compat_data[] = {
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{ "allwinner,sun4i-a10-ehci", (uintptr_t)&a10_ehci_conf },
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{ "allwinner,sun5i-a13-ehci", (uintptr_t)&a10_ehci_conf },
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{ "allwinner,sun6i-a31-ehci", (uintptr_t)&a31_ehci_conf },
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{ "allwinner,sun7i-a20-ehci", (uintptr_t)&a10_ehci_conf },
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{ "allwinner,sun8i-a83t-ehci", (uintptr_t)&a31_ehci_conf },
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{ "allwinner,sun8i-h3-ehci", (uintptr_t)&a31_ehci_conf },
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{ "allwinner,sun50i-a64-ehci", (uintptr_t)&a31_ehci_conf },
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{ NULL, (uintptr_t)NULL }
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};
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static int
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a10_ehci_probe(device_t self)
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{
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if (!ofw_bus_status_okay(self))
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return (ENXIO);
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if (ofw_bus_search_compatible(self, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(self, EHCI_HC_DEVSTR);
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return (BUS_PROBE_DEFAULT);
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}
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static int
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a10_ehci_attach(device_t self)
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{
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struct aw_ehci_softc *aw_sc = device_get_softc(self);
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ehci_softc_t *sc = &aw_sc->sc;
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const struct aw_ehci_conf *conf;
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bus_space_handle_t bsh;
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int err, rid, off;
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struct clk_list *clkp;
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clk_t clk;
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struct hwrst_list *rstp;
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hwreset_t rst;
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uint32_t reg_value = 0;
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conf = USB_CONF(self);
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/* initialise some bus fields */
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sc->sc_bus.parent = self;
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sc->sc_bus.devices = sc->sc_devices;
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sc->sc_bus.devices_max = EHCI_MAX_DEVICES;
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sc->sc_bus.dma_bits = 32;
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/* get all DMA memory */
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if (usb_bus_mem_alloc_all(&sc->sc_bus,
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USB_GET_DMA_TAG(self), &ehci_iterate_hw_softc)) {
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return (ENOMEM);
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}
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sc->sc_bus.usbrev = USB_REV_2_0;
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rid = 0;
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sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
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if (!sc->sc_io_res) {
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device_printf(self, "Could not map memory\n");
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goto error;
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}
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sc->sc_io_tag = rman_get_bustag(sc->sc_io_res);
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sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
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bsh = rman_get_bushandle(sc->sc_io_res);
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sc->sc_io_size = rman_get_size(sc->sc_io_res);
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if (bus_space_subregion(sc->sc_io_tag, bsh, 0x00,
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sc->sc_io_size, &sc->sc_io_hdl) != 0)
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panic("%s: unable to subregion USB host registers",
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device_get_name(self));
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rid = 0;
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sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
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RF_SHAREABLE | RF_ACTIVE);
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if (sc->sc_irq_res == NULL) {
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device_printf(self, "Could not allocate irq\n");
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goto error;
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}
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sc->sc_bus.bdev = device_add_child(self, "usbus", -1);
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if (!sc->sc_bus.bdev) {
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device_printf(self, "Could not add USB device\n");
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goto error;
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}
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device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
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device_set_desc(sc->sc_bus.bdev, EHCI_HC_DEVSTR);
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sprintf(sc->sc_vendor, "Allwinner");
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err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
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NULL, (driver_intr_t *)ehci_interrupt, sc, &sc->sc_intr_hdl);
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if (err) {
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device_printf(self, "Could not setup irq, %d\n", err);
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sc->sc_intr_hdl = NULL;
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goto error;
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}
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sc->sc_flags |= EHCI_SCFLG_DONTRESET;
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/* Enable clock for USB */
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TAILQ_INIT(&aw_sc->clk_list);
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for (off = 0; clk_get_by_ofw_index(self, 0, off, &clk) == 0; off++) {
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err = clk_enable(clk);
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if (err != 0) {
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device_printf(self, "Could not enable clock %s\n",
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clk_get_name(clk));
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goto error;
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}
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clkp = malloc(sizeof(*clkp), M_DEVBUF, M_WAITOK | M_ZERO);
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clkp->clk = clk;
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TAILQ_INSERT_TAIL(&aw_sc->clk_list, clkp, next);
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}
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/* De-assert reset */
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TAILQ_INIT(&aw_sc->rst_list);
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for (off = 0; hwreset_get_by_ofw_idx(self, 0, off, &rst) == 0; off++) {
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err = hwreset_deassert(rst);
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if (err != 0) {
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device_printf(self, "Could not de-assert reset\n");
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goto error;
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}
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rstp = malloc(sizeof(*rstp), M_DEVBUF, M_WAITOK | M_ZERO);
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rstp->rst = rst;
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TAILQ_INSERT_TAIL(&aw_sc->rst_list, rstp, next);
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}
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/* Enable USB PHY */
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if (phy_get_by_ofw_name(self, 0, "usb", &aw_sc->phy) == 0) {
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err = phy_enable(self, aw_sc->phy);
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if (err != 0) {
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device_printf(self, "Could not enable phy\n");
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goto error;
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}
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}
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/* Configure port */
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if (conf->sdram_init) {
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reg_value = A10_READ_4(sc, SW_SDRAM_REG_HPCR_USB2);
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reg_value |= SW_SDRAM_BP_HPCR_ACCESS;
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A10_WRITE_4(sc, SW_SDRAM_REG_HPCR_USB2, reg_value);
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}
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err = ehci_init(sc);
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if (!err) {
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err = device_probe_and_attach(sc->sc_bus.bdev);
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}
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if (err) {
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device_printf(self, "USB init failed err=%d\n", err);
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goto error;
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}
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return (0);
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error:
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a10_ehci_detach(self);
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return (ENXIO);
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}
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static int
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a10_ehci_detach(device_t self)
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{
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struct aw_ehci_softc *aw_sc = device_get_softc(self);
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ehci_softc_t *sc = &aw_sc->sc;
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const struct aw_ehci_conf *conf;
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int err;
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uint32_t reg_value = 0;
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struct clk_list *clk, *clk_tmp;
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struct hwrst_list *rst, *rst_tmp;
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conf = USB_CONF(self);
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/* during module unload there are lots of children leftover */
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device_delete_children(self);
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if (sc->sc_irq_res && sc->sc_intr_hdl) {
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/*
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* only call ehci_detach() after ehci_init()
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*/
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ehci_detach(sc);
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err = bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl);
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if (err)
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/* XXX or should we panic? */
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device_printf(self, "Could not tear down irq, %d\n",
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err);
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sc->sc_intr_hdl = NULL;
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}
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if (sc->sc_irq_res) {
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bus_release_resource(self, SYS_RES_IRQ, 0, sc->sc_irq_res);
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sc->sc_irq_res = NULL;
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}
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if (sc->sc_io_res) {
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bus_release_resource(self, SYS_RES_MEMORY, 0,
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sc->sc_io_res);
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sc->sc_io_res = NULL;
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}
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usb_bus_mem_free_all(&sc->sc_bus, &ehci_iterate_hw_softc);
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/* Disable configure port */
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if (conf->sdram_init) {
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reg_value = A10_READ_4(sc, SW_SDRAM_REG_HPCR_USB2);
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reg_value &= ~SW_SDRAM_BP_HPCR_ACCESS;
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A10_WRITE_4(sc, SW_SDRAM_REG_HPCR_USB2, reg_value);
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}
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/* Disable clock */
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TAILQ_FOREACH_SAFE(clk, &aw_sc->clk_list, next, clk_tmp) {
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err = clk_disable(clk->clk);
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if (err != 0)
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device_printf(self, "Could not disable clock %s\n",
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clk_get_name(clk->clk));
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err = clk_release(clk->clk);
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if (err != 0)
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device_printf(self, "Could not release clock %s\n",
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clk_get_name(clk->clk));
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TAILQ_REMOVE(&aw_sc->clk_list, clk, next);
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free(clk, M_DEVBUF);
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}
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/* Assert reset */
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TAILQ_FOREACH_SAFE(rst, &aw_sc->rst_list, next, rst_tmp) {
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hwreset_assert(rst->rst);
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hwreset_release(rst->rst);
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TAILQ_REMOVE(&aw_sc->rst_list, rst, next);
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free(rst, M_DEVBUF);
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}
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return (0);
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}
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static device_method_t ehci_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, a10_ehci_probe),
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DEVMETHOD(device_attach, a10_ehci_attach),
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DEVMETHOD(device_detach, a10_ehci_detach),
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DEVMETHOD(device_suspend, bus_generic_suspend),
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DEVMETHOD(device_resume, bus_generic_resume),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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DEVMETHOD_END
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};
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static driver_t ehci_driver = {
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.name = "ehci",
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.methods = ehci_methods,
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.size = sizeof(struct aw_ehci_softc),
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};
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static devclass_t ehci_devclass;
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DRIVER_MODULE(ehci, simplebus, ehci_driver, ehci_devclass, 0, 0);
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MODULE_DEPEND(ehci, usb, 1, 1, 1);
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