Update our copies of the Device Tree Source to Linux 4.14
This commit is contained in:
parent
d5464ff117
commit
550370858c
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/vendor/device-tree/dist/; revision=325773 svn path=/vendor/device-tree/4.14/; revision=325774; tag=vendor/device-tree/4.14
7
Bindings/arc/hsdk.txt
Normal file
7
Bindings/arc/hsdk.txt
Normal file
@ -0,0 +1,7 @@
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Synopsys DesignWare ARC HS Development Kit Device Tree Bindings
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---------------------------------------------------------------------------
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ARC HSDK Board with quad-core ARC HS38x4 in silicon.
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Required root node properties:
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- compatible = "snps,hsdk";
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@ -1,6 +1,18 @@
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Amlogic MesonX device tree bindings
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-------------------------------------------
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Work in progress statement:
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Device tree files and bindings applying to Amlogic SoCs and boards are
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considered "unstable". Any Amlogic device tree binding may change at
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any time. Be sure to use a device tree binary and a kernel image
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generated from the same source tree.
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Please refer to Documentation/devicetree/bindings/ABI.txt for a definition of a
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stable binding/ABI.
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---------------------------------------------------------------
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Boards with the Amlogic Meson6 SoC shall have the following properties:
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Required root node property:
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compatible: "amlogic,meson6"
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@ -61,3 +73,32 @@ Board compatible values (alphabetically, grouped by SoC):
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- "amlogic,q201" (Meson gxm s912)
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- "kingnovel,r-box-pro" (Meson gxm S912)
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- "nexbox,a1" (Meson gxm s912)
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Amlogic Meson Firmware registers Interface
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------------------------------------------
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The Meson SoCs have a register bank with status and data shared with the
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secure firmware.
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Required properties:
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- compatible: For Meson GX SoCs, must be "amlogic,meson-gx-ao-secure", "syscon"
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Properties should indentify components of this register interface :
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Meson GX SoC Information
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------------------------
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A firmware register encodes the SoC type, package and revision information on
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the Meson GX SoCs.
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If present, the following property should be added :
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Optional properties:
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- amlogic,has-chip-id: If present, the interface gives the current SoC version.
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Example
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-------
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ao-secure@140 {
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compatible = "amlogic,meson-gx-ao-secure", "syscon";
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reg = <0x0 0x140 0x0 0x140>;
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amlogic,has-chip-id;
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};
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@ -108,6 +108,5 @@ Example:
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frame-number = <1>
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interrupts = <0 15 0x8>;
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reg = <0xf0003000 0x1000>;
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status = "disabled";
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};
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};
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@ -42,6 +42,10 @@ Raspberry Pi Zero
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Required root node properties:
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compatible = "raspberrypi,model-zero", "brcm,bcm2835";
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Raspberry Pi Zero W
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Required root node properties:
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compatible = "raspberrypi,model-zero-w", "brcm,bcm2835";
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Generic BCM2835 board
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Required root node properties:
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compatible = "brcm,bcm2835";
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6
Bindings/arm/bhf.txt
Normal file
6
Bindings/arm/bhf.txt
Normal file
@ -0,0 +1,6 @@
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Beckhoff Automation Platforms Device Tree Bindings
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--------------------------------------------------
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CX9020 Embedded PC
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Required root node properties:
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- compatible = "bhf,cx9020", "fsl,imx53";
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@ -34,8 +34,8 @@ its hardware characteristcs.
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- Embedded Trace Macrocell (version 4.x):
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"arm,coresight-etm4x", "arm,primecell";
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- Qualcomm Configurable Replicator (version 1.x):
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"qcom,coresight-replicator1x", "arm,primecell";
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- Coresight programmable Replicator :
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"arm,coresight-dynamic-replicator", "arm,primecell";
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- System Trace Macrocell:
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"arm,coresight-stm", "arm,primecell"; [1]
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@ -200,6 +200,7 @@ described below.
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"arm,realview-smp"
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"brcm,bcm11351-cpu-method"
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"brcm,bcm23550"
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"brcm,bcm2836-smp"
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"brcm,bcm-nsp-smp"
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"brcm,brahma-b15"
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"marvell,armada-375-smp"
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15
Bindings/arm/marvell/armada-8kp.txt
Normal file
15
Bindings/arm/marvell/armada-8kp.txt
Normal file
@ -0,0 +1,15 @@
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Marvell Armada 8KPlus Platforms Device Tree Bindings
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----------------------------------------------------
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Boards using a SoC of the Marvell Armada 8KP families must carry
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the following root node property:
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- compatible, with one of the following values:
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- "marvell,armada-8080", "marvell,armada-ap810-octa", "marvell,armada-ap810"
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when the SoC being used is the Armada 8080
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Example:
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compatible = "marvell,armada-8080-db", "marvell,armada-8080",
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"marvell,armada-ap810-octa", "marvell,armada-ap810"
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@ -183,7 +183,6 @@ cpm_syscon0: system-controller@440000 {
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&cpm_pinctrl 0 0 32>;
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status = "disabled";
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};
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};
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@ -1,12 +1,12 @@
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MediaTek mt65xx, mt67xx & mt81xx Platforms Device Tree Bindings
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MediaTek SoC based Platforms Device Tree Bindings
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Boards with a MediaTek mt65xx/mt67xx/mt81xx SoC shall have the
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following property:
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Boards with a MediaTek SoC shall have the following property:
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Required root node property:
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compatible: Must contain one of
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"mediatek,mt2701"
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"mediatek,mt2712"
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"mediatek,mt6580"
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"mediatek,mt6589"
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"mediatek,mt6592"
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@ -14,7 +14,8 @@ compatible: Must contain one of
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"mediatek,mt6795"
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"mediatek,mt6797"
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"mediatek,mt7622"
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"mediatek,mt7623"
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"mediatek,mt7623" which is referred to MT7623N SoC
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"mediatek,mt7623a"
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"mediatek,mt8127"
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"mediatek,mt8135"
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"mediatek,mt8173"
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@ -25,6 +26,9 @@ Supported boards:
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- Evaluation board for MT2701:
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Required root node properties:
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- compatible = "mediatek,mt2701-evb", "mediatek,mt2701";
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- Evaluation board for MT2712:
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Required root node properties:
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- compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
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- Evaluation board for MT6580:
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Required root node properties:
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- compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580";
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@ -46,9 +50,11 @@ Supported boards:
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- Reference board variant 1 for MT7622:
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Required root node properties:
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- compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
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- Evaluation board for MT7623:
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- Reference board for MT7623n with NAND:
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Required root node properties:
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- compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
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- compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";
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- Bananapi BPI-R2 board:
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- compatible = "bananapi,bpi-r2", "mediatek,mt7623";
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- MTK mt8127 tablet moose EVB:
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Required root node properties:
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- compatible = "mediatek,mt8127-moose", "mediatek,mt8127";
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@ -80,6 +80,9 @@ SoCs:
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- OMAP5432
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compatible = "ti,omap5432", "ti,omap5"
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- DRA762
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compatible = "ti,dra762", "ti,dra7"
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- DRA742
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compatible = "ti,dra742", "ti,dra74", "ti,dra7"
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@ -154,6 +157,9 @@ Boards:
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- AM335X phyCORE-AM335x: Development kit
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compatible = "phytec,am335x-pcm-953", "phytec,am335x-phycore-som", "ti,am33xx"
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- AM335X UC-8100-ME-T: Communication-centric industrial computing platform
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compatible = "moxa,uc-8100-me-t", "ti,am33xx";
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- OMAP5 EVM : Evaluation Module
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compatible = "ti,omap5-evm", "ti,omap5"
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@ -184,6 +190,9 @@ Boards:
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- AM5718 IDK
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compatible = "ti,am5718-idk", "ti,am5718", "ti,dra7"
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- DRA762 EVM: Software Development Board for DRA762
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compatible = "ti,dra76-evm", "ti,dra762", "ti,dra7"
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- DRA742 EVM: Software Development Board for DRA742
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compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"
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@ -9,9 +9,11 @@ Required properties:
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- compatible : should be one of
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"apm,potenza-pmu"
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"arm,armv8-pmuv3"
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"arm,cortex-a73-pmu"
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"arm,cortex-a72-pmu"
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"arm,cortex-a57-pmu"
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"arm,cortex-a53-pmu"
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"arm,cortex-a35-pmu"
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"arm,cortex-a17-pmu"
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"arm,cortex-a15-pmu"
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"arm,cortex-a12-pmu"
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@ -25,6 +25,7 @@ The 'SoC' element must be one of the following strings:
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msm8994
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msm8996
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mdm9615
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ipq8074
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The 'board' element must be one of the following strings:
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@ -33,6 +34,7 @@ The 'board' element must be one of the following strings:
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dragonboard
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mtp
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sbc
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hk01
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The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor>
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where the minor number may be omitted when it's zero, i.e. v1.0 is the same
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@ -134,6 +134,10 @@ Rockchip platforms device tree bindings
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Required root node properties:
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- compatible = "phytec,rk3288-pcm-947", "phytec,rk3288-phycore-som", "rockchip,rk3288";
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- Pine64 Rock64 board:
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Required root node properties:
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- compatible = "pine64,rock64", "rockchip,rk3328";
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- Rockchip PX3 Evaluation board:
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Required root node properties:
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- compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188";
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@ -173,6 +177,14 @@ Rockchip platforms device tree bindings
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Required root node properties:
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- compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
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- Rockchip RK3399 Sapphire Excavator board:
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Required root node properties:
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- compatible = "rockchip,rk3399-sapphire-excavator", "rockchip,rk3399";
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- Theobroma Systems RK3399-Q7 Haikou Baseboard:
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Required root node properties:
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- compatible = "tsd,rk3399-q7-haikou", "rockchip,rk3399";
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- Tronsmart Orion R68 Meta
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Required root node properties:
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- compatible = "tronsmart,orion-r68-meta", "rockchip,rk3368";
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@ -39,6 +39,8 @@ SoCs:
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compatible = "renesas,r8a7795"
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- R-Car M3-W (R8A77960)
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compatible = "renesas,r8a7796"
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- R-Car D3 (R8A77995)
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compatible = "renesas,r8a77995"
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Boards:
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@ -53,6 +55,8 @@ Boards:
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compatible = "renesas,blanche", "renesas,r8a7792"
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- BOCK-W
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compatible = "renesas,bockw", "renesas,r8a7778"
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- Draak (RTP0RC77995SEB0010S)
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compatible = "renesas,draak", "renesas,r8a77995"
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- Genmai (RTK772100BC00000BR)
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compatible = "renesas,genmai", "renesas,r7s72100"
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- GR-Peach (X28A-M01-E/F)
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@ -64,6 +68,10 @@ Boards:
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compatible = "renesas,h3ulcb", "renesas,r8a7795";
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- Henninger
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compatible = "renesas,henninger", "renesas,r8a7791"
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- iWave Systems RZ/G1E SODIMM SOM Development Platform (iW-RainboW-G22D)
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compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745"
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- iWave Systems RZ/G1E SODIMM System On Module (iW-RainboW-G22M-SM)
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compatible = "iwave,g22m", "renesas,r8a7745"
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- iWave Systems RZ/G1M Qseven Development Platform (iW-RainboW-G20D-Qseven)
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compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743"
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- iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven)
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|
51
Bindings/ata/ahci-mtk.txt
Normal file
51
Bindings/ata/ahci-mtk.txt
Normal file
@ -0,0 +1,51 @@
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MediaTek Serial ATA controller
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Required properties:
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- compatible : Must be "mediatek,<chip>-ahci", "mediatek,mtk-ahci".
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When using "mediatek,mtk-ahci" compatible strings, you
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need SoC specific ones in addition, one of:
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- "mediatek,mt7622-ahci"
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- reg : Physical base addresses and length of register sets.
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- interrupts : Interrupt associated with the SATA device.
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- interrupt-names : Associated name must be: "hostc".
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- clocks : A list of phandle and clock specifier pairs, one for each
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entry in clock-names.
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- clock-names : Associated names must be: "ahb", "axi", "asic", "rbc", "pm".
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- phys : A phandle and PHY specifier pair for the PHY port.
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- phy-names : Associated name must be: "sata-phy".
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- ports-implemented : See ./ahci-platform.txt for details.
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Optional properties:
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- power-domains : A phandle and power domain specifier pair to the power
|
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domain which is responsible for collapsing and restoring
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power to the peripheral.
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- resets : Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names : Associated names must be: "axi", "sw", "reg".
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- mediatek,phy-mode : A phandle to the system controller, used to enable
|
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SATA function.
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Example:
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sata: sata@1a200000 {
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compatible = "mediatek,mt7622-ahci",
|
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"mediatek,mtk-ahci";
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reg = <0 0x1a200000 0 0x1100>;
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interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
|
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interrupt-names = "hostc";
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clocks = <&pciesys CLK_SATA_AHB_EN>,
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<&pciesys CLK_SATA_AXI_EN>,
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<&pciesys CLK_SATA_ASIC_EN>,
|
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<&pciesys CLK_SATA_RBC_EN>,
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<&pciesys CLK_SATA_PM_EN>;
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clock-names = "ahb", "axi", "asic", "rbc", "pm";
|
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phys = <&u3port1 PHY_TYPE_SATA>;
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phy-names = "sata-phy";
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ports-implemented = <0x1>;
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power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
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resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
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<&pciesys MT7622_SATA_PHY_SW_RST>,
|
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<&pciesys MT7622_SATA_PHY_REG_RST>;
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reset-names = "axi", "sw", "reg";
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mediatek,phy-mode = <&pciesys>;
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};
|
@ -57,7 +57,6 @@ Example:
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<0x0 0x1f227000 0x0 0x1000>;
|
||||
interrupts = <0x0 0x87 0x4>;
|
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dma-coherent;
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status = "ok";
|
||||
clocks = <&sataclk 0>;
|
||||
phys = <&phy2 0>;
|
||||
phy-names = "sata-phy";
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||||
@ -72,7 +71,6 @@ Example:
|
||||
<0x0 0x1f237000 0x0 0x1000>;
|
||||
interrupts = <0x0 0x88 0x4>;
|
||||
dma-coherent;
|
||||
status = "ok";
|
||||
clocks = <&sataclk 0>;
|
||||
phys = <&phy3 0>;
|
||||
phy-names = "sata-phy";
|
||||
|
@ -13,5 +13,4 @@ Example:
|
||||
reg = <0x83fe0000 0x4000>;
|
||||
interrupts = <70>;
|
||||
clocks = <&clks 161>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -227,7 +227,6 @@ See the example below, where a more complete device tree is shown:
|
||||
};
|
||||
|
||||
devbus-bootcs {
|
||||
status = "okay";
|
||||
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0x8000000>;
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||||
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||||
/* NOR */
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||||
@ -240,7 +239,6 @@ See the example below, where a more complete device tree is shown:
|
||||
|
||||
pcie-controller {
|
||||
compatible = "marvell,armada-xp-pcie";
|
||||
status = "okay";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
@ -258,7 +256,6 @@ See the example below, where a more complete device tree is shown:
|
||||
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -84,7 +84,6 @@ gmi@70090000 {
|
||||
reset-names = "gmi";
|
||||
ranges = <4 0 0xd0000000 0xfffffff>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
bus@4,0 {
|
||||
compatible = "simple-bus";
|
||||
@ -121,7 +120,6 @@ gmi@70090000 {
|
||||
reset-names = "gmi";
|
||||
ranges = <4 0 0xd0000000 0xfffffff>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
can@4,0 {
|
||||
reg = <4 0 0x100>;
|
||||
|
@ -33,7 +33,6 @@ Example:
|
||||
#size-cells = <1>;
|
||||
ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
child1 {
|
||||
...
|
||||
|
@ -5,9 +5,31 @@ The chosen node does not represent a real device, but serves as a place
|
||||
for passing data between firmware and the operating system, like boot
|
||||
arguments. Data in the chosen node does not represent the hardware.
|
||||
|
||||
The following properties are recognized:
|
||||
|
||||
stdout-path property
|
||||
--------------------
|
||||
|
||||
kaslr-seed
|
||||
-----------
|
||||
|
||||
This property is used when booting with CONFIG_RANDOMIZE_BASE as the
|
||||
entropy used to randomize the kernel image base address location. Since
|
||||
it is used directly, this value is intended only for KASLR, and should
|
||||
not be used for other purposes (as it may leak information about KASLR
|
||||
offsets). It is parsed as a u64 value, e.g.
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
kaslr-seed = <0xfeedbeef 0xc0def00d>;
|
||||
};
|
||||
};
|
||||
|
||||
Note that if this property is set from UEFI (or a bootloader in EFI
|
||||
mode) when EFI_RNG_PROTOCOL is supported, it will be overwritten by
|
||||
the Linux EFI stub (which will populate the property itself, using
|
||||
EFI_RNG_PROTOCOL).
|
||||
|
||||
stdout-path
|
||||
-----------
|
||||
|
||||
Device trees may specify the device to be used for boot console output
|
||||
with a stdout-path property under /chosen, as described in the Devicetree
|
||||
|
@ -102,7 +102,6 @@ uart4: serial@80010000 {
|
||||
reg = <0x80010000 0x4000>;
|
||||
clocks = <&acc CLKID_SYS_UART4>, <&acc CLKID_AHB_UART4>;
|
||||
interrupts = <19>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
Clock consumer with only one, _AHB_ sink.
|
||||
|
@ -5,9 +5,11 @@ controllers within the Always-On part of the SoC.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "amlogic,gxbb-aoclkc"
|
||||
- reg: physical base address of the clock controller and length of memory
|
||||
mapped region.
|
||||
- compatible: value should be different for each SoC family as :
|
||||
- GXBB (S905) : "amlogic,meson-gxbb-aoclkc"
|
||||
- GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
|
||||
- GXM (S912) : "amlogic,meson-gxm-aoclkc"
|
||||
followed by the common "amlogic,meson-gx-aoclkc"
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
@ -23,14 +25,22 @@ to specify the reset which they consume. All available resets are defined as
|
||||
preprocessor macros in the dt-bindings/reset/gxbb-aoclkc.h header and can be
|
||||
used in device tree sources.
|
||||
|
||||
Parent node should have the following properties :
|
||||
- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"
|
||||
- reg: base address and size of the AO system control register space.
|
||||
|
||||
Example: AO Clock controller node:
|
||||
|
||||
clkc_AO: clock-controller@040 {
|
||||
compatible = "amlogic,gxbb-aoclkc";
|
||||
reg = <0x0 0x040 0x0 0x4>;
|
||||
ao_sysctrl: sys-ctrl@0 {
|
||||
compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
|
||||
reg = <0x0 0x0 0x0 0x100>;
|
||||
|
||||
clkc_AO: clock-controller {
|
||||
compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock and reset generated
|
||||
by the clock controller:
|
||||
@ -41,5 +51,4 @@ Example: UART controller node that consumes the clock and reset generated
|
||||
interrupts = <0 90 1>;
|
||||
clocks = <&clkc_AO CLKID_AO_UART1>;
|
||||
resets = <&clkc_AO RESET_AO_UART1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -33,5 +33,4 @@ Example: UART controller node that consumes the clock generated by the clock
|
||||
reg = <0xc81004c0 0x14>;
|
||||
interrupts = <0 90 1>;
|
||||
clocks = <&clkc CLKID_CLK81>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -16,18 +16,25 @@ Required Properties:
|
||||
mapped region.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can be
|
||||
used in device tree sources.
|
||||
|
||||
Similarly a preprocessor macro for each reset line is defined in
|
||||
dt-bindings/reset/amlogic,meson8b-clkc-reset.h (which can be used from the
|
||||
device tree sources).
|
||||
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
clkc: clock-controller@c1104000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "amlogic,meson8b-clkc";
|
||||
reg = <0xc1108000 0x4>, <0xc1104000 0x460>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
|
||||
@ -39,5 +46,4 @@ Example: UART controller node that consumes the clock generated by the clock
|
||||
reg = <0xc81004c0 0x14>;
|
||||
interrupts = <0 90 1>;
|
||||
clocks = <&clkc CLKID_CLK81>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -81,6 +81,16 @@ Required properties:
|
||||
"atmel,sama5d2-clk-generated":
|
||||
at91 generated clock
|
||||
|
||||
"atmel,sama5d2-clk-audio-pll-frac":
|
||||
at91 audio fractional pll
|
||||
|
||||
"atmel,sama5d2-clk-audio-pll-pad":
|
||||
at91 audio pll CLK_AUDIO output pin
|
||||
|
||||
"atmel,sama5d2-clk-audio-pll-pmc"
|
||||
at91 audio pll output on AUDIOPLLCLK that feeds the PMC
|
||||
and can be used by peripheral clock or generic clock
|
||||
|
||||
Required properties for SCKC node:
|
||||
- reg : defines the IO memory reserved for the SCKC.
|
||||
- #size-cells : shall be 0 (reg is used to encode clk id).
|
||||
|
@ -46,7 +46,6 @@ Device tree example:
|
||||
|
||||
uart@3e002000 {
|
||||
compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
|
||||
status = "disabled";
|
||||
reg = <0x3e002000 0x1000>;
|
||||
clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>;
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
@ -465,5 +465,4 @@ Example 3: UART controller node that consumes the clock generated by the clock
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_bus>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -38,5 +38,4 @@ Examples:
|
||||
clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
|
||||
<&crg_ctrl HI3660_PCLK>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -27,5 +27,4 @@ Examples:
|
||||
interrupts = <0 49 4>;
|
||||
clocks = <&clock HIX5HD2_FIXED_83M>;
|
||||
clock-names = "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -1,24 +1,32 @@
|
||||
Binding for IDT VersaClock5 programmable i2c clock generator.
|
||||
Binding for IDT VersaClock 5,6 programmable i2c clock generators.
|
||||
|
||||
The IDT VersaClock5 are programmable i2c clock generators providing
|
||||
from 3 to 12 output clocks.
|
||||
The IDT VersaClock 5 and VersaClock 6 are programmable i2c clock
|
||||
generators providing from 3 to 12 output clocks.
|
||||
|
||||
==I2C device node==
|
||||
|
||||
Required properties:
|
||||
- compatible: shall be one of "idt,5p49v5923" , "idt,5p49v5933" ,
|
||||
"idt,5p49v5935".
|
||||
- compatible: shall be one of
|
||||
"idt,5p49v5923"
|
||||
"idt,5p49v5925"
|
||||
"idt,5p49v5933"
|
||||
"idt,5p49v5935"
|
||||
"idt,5p49v6901"
|
||||
- reg: i2c device address, shall be 0x68 or 0x6a.
|
||||
- #clock-cells: from common clock binding; shall be set to 1.
|
||||
- clocks: from common clock binding; list of parent clock handles,
|
||||
- 5p49v5923: (required) either or both of XTAL or CLKIN
|
||||
- 5p49v5923 and
|
||||
5p49v5925 and
|
||||
5p49v6901: (required) either or both of XTAL or CLKIN
|
||||
reference clock.
|
||||
- 5p49v5933 and
|
||||
- 5p49v5935: (optional) property not present (internal
|
||||
Xtal used) or CLKIN reference
|
||||
clock.
|
||||
- clock-names: from common clock binding; clock input names, can be
|
||||
- 5p49v5923: (required) either or both of "xin", "clkin".
|
||||
- 5p49v5923 and
|
||||
5p49v5925 and
|
||||
5p49v6901: (required) either or both of "xin", "clkin".
|
||||
- 5p49v5933 and
|
||||
- 5p49v5935: (optional) property not present or "clkin".
|
||||
|
||||
@ -37,6 +45,7 @@ clock specifier, the following mapping applies:
|
||||
1 -- OUT1
|
||||
2 -- OUT4
|
||||
|
||||
5P49V5925 and
|
||||
5P49V5935:
|
||||
0 -- OUT0_SEL_I2CB
|
||||
1 -- OUT1
|
||||
@ -44,6 +53,13 @@ clock specifier, the following mapping applies:
|
||||
3 -- OUT3
|
||||
4 -- OUT4
|
||||
|
||||
5P49V6901:
|
||||
0 -- OUT0_SEL_I2CB
|
||||
1 -- OUT1
|
||||
2 -- OUT2
|
||||
3 -- OUT3
|
||||
4 -- OUT4
|
||||
|
||||
==Example==
|
||||
|
||||
/* 25MHz reference crystal */
|
||||
|
@ -24,5 +24,4 @@ Examples:
|
||||
clocks = <&clks IMX21_CLK_UART1_IPG_GATE>,
|
||||
<&clks IMX21_CLK_PER1>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -67,5 +67,4 @@ auart0: serial@8006c000 {
|
||||
reg = <0x8006c000 0x2000>;
|
||||
interrupts = <24 25 23>;
|
||||
clocks = <&clks 32>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -157,5 +157,4 @@ uart1: serial@43f90000 {
|
||||
interrupts = <45>;
|
||||
clocks = <&clks 79>, <&clks 50>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -24,5 +24,4 @@ Examples:
|
||||
clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
|
||||
<&clks IMX27_CLK_PER1_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -90,5 +90,4 @@ auart0: serial@8006a000 {
|
||||
reg = <0x8006a000 0x2000>;
|
||||
interrupts = <112 70 71>;
|
||||
clocks = <&clks 45>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -87,5 +87,4 @@ uart1: serial@43f90000 {
|
||||
interrupts = <45>;
|
||||
clocks = <&clks 10>, <&clks 30>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -25,5 +25,4 @@ can1: can@53fc8000 {
|
||||
interrupts = <82>;
|
||||
clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -27,5 +27,4 @@ uart1: serial@02020000 {
|
||||
interrupts = <0 26 0x04>;
|
||||
clocks = <&clks IMX6QDL_CLK_UART_IPG>, <&clks IMX6QDL_CLK_UART_SERIAL>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -1,83 +0,0 @@
|
||||
Device Tree Clock bindins for CPU DVFS of Mediatek MT8173 SoC
|
||||
|
||||
Required properties:
|
||||
- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
|
||||
- clock-names: Should contain the following:
|
||||
"cpu" - The multiplexer for clock input of CPU cluster.
|
||||
"intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
|
||||
source (usually MAINPLL) when the original CPU PLL is under
|
||||
transition and not stable yet.
|
||||
Please refer to Documentation/devicetree/bindings/clk/clock-bindings.txt for
|
||||
generic clock consumer properties.
|
||||
- proc-supply: Regulator for Vproc of CPU cluster.
|
||||
|
||||
Optional properties:
|
||||
- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
|
||||
needs to do "voltage tracking" to step by step scale up/down Vproc and
|
||||
Vsram to fit SoC specific needs. When absent, the voltage scaling
|
||||
flow is handled by hardware, hence no software "voltage tracking" is
|
||||
needed.
|
||||
|
||||
Example:
|
||||
--------
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x000>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
clocks = <&infracfg CLK_INFRA_CA53SEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x001>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
clocks = <&infracfg CLK_INFRA_CA53SEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
};
|
||||
|
||||
cpu2: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x100>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
clocks = <&infracfg CLK_INFRA_CA57SEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
};
|
||||
|
||||
cpu3: cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x101>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
clocks = <&infracfg CLK_INFRA_CA57SEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
proc-supply = <&mt6397_vpca15_reg>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
proc-supply = <&mt6397_vpca15_reg>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
proc-supply = <&da9211_vcpu_reg>;
|
||||
sram-supply = <&mt6397_vsramca7_reg>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
proc-supply = <&da9211_vcpu_reg>;
|
||||
sram-supply = <&mt6397_vsramca7_reg>;
|
||||
};
|
@ -66,7 +66,6 @@ clock@70110000 {
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "dfllCPU_out";
|
||||
vdd-cpu-supply = <&vdd_cpu>;
|
||||
status = "okay";
|
||||
|
||||
nvidia,sample-rate = <12500>;
|
||||
nvidia,droop-ctrl = <0x00000f00>;
|
||||
|
@ -12,5 +12,4 @@ Examples:
|
||||
pxa2xx_clks: pxa2xx_clks@41300004 {
|
||||
compatible = "marvell,pxa-clocks";
|
||||
#clock-cells = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
@ -22,6 +22,7 @@ Required Properties:
|
||||
- "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
|
||||
- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
|
||||
- "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
|
||||
- "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
|
||||
|
||||
- reg: Base address and length of the memory resource used by the CPG/MSSR
|
||||
block
|
||||
@ -30,7 +31,7 @@ Required Properties:
|
||||
clock-names
|
||||
- clock-names: List of external parent clock names. Valid names are:
|
||||
- "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
|
||||
r8a7795, r8a7796)
|
||||
r8a7795, r8a7796, r8a77995)
|
||||
- "extalr" (r8a7795, r8a7796)
|
||||
- "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)
|
||||
|
||||
@ -81,5 +82,4 @@ Examples
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg>;
|
||||
resets = <&cpg 310>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -44,5 +44,4 @@ Examples
|
||||
interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
55
Bindings/clock/renesas,rcar-usb2-clock-sel.txt
Normal file
55
Bindings/clock/renesas,rcar-usb2-clock-sel.txt
Normal file
@ -0,0 +1,55 @@
|
||||
* Renesas R-Car USB 2.0 clock selector
|
||||
|
||||
This file provides information on what the device node for the R-Car USB 2.0
|
||||
clock selector.
|
||||
|
||||
If you connect an external clock to the USB_EXTAL pin only, you should set
|
||||
the clock rate to "usb_extal" node only.
|
||||
If you connect an oscillator to both the USB_XTAL and USB_EXTAL, this module
|
||||
is not needed because this is default setting. (Of course, you can set the
|
||||
clock rates to both "usb_extal" and "usb_xtal" nodes.
|
||||
|
||||
Case 1: An external clock connects to R-Car SoC
|
||||
+----------+ +--- R-Car ---------------------+
|
||||
|External |---|USB_EXTAL ---> all usb channels|
|
||||
|clock | |USB_XTAL |
|
||||
+----------+ +-------------------------------+
|
||||
In this case, we need this driver with "usb_extal" clock.
|
||||
|
||||
Case 2: An oscillator connects to R-Car SoC
|
||||
+----------+ +--- R-Car ---------------------+
|
||||
|Oscillator|---|USB_EXTAL -+-> all usb channels|
|
||||
| |---|USB_XTAL --+ |
|
||||
+----------+ +-------------------------------+
|
||||
In this case, we don't need this selector.
|
||||
|
||||
Required properties:
|
||||
- compatible: "renesas,r8a7795-rcar-usb2-clock-sel" if the device is a part of
|
||||
an R8A7795 SoC.
|
||||
"renesas,r8a7796-rcar-usb2-clock-sel" if the device if a part of
|
||||
an R8A7796 SoC.
|
||||
"renesas,rcar-gen3-usb2-clock-sel" for a generic R-Car Gen3
|
||||
compatible device.
|
||||
|
||||
When compatible with the generic version, nodes must list the
|
||||
SoC-specific version corresponding to the platform first
|
||||
followed by the generic version.
|
||||
|
||||
- reg: offset and length of the USB 2.0 clock selector register block.
|
||||
- clocks: A list of phandles and specifier pairs.
|
||||
- clock-names: Name of the clocks.
|
||||
- The functional clock must be "ehci_ohci"
|
||||
- The USB_EXTAL clock pin must be "usb_extal"
|
||||
- The USB_XTAL clock pin must be "usb_xtal"
|
||||
- #clock-cells: Must be 0
|
||||
|
||||
Example (R-Car H3):
|
||||
|
||||
usb2_clksel: clock-controller@e6590630 {
|
||||
compatible = "renesas,r8a77950-rcar-usb2-clock-sel",
|
||||
"renesas,rcar-gen3-usb2-clock-sel";
|
||||
reg = <0 0xe6590630 0 0x02>;
|
||||
clocks = <&cpg CPG_MOD 703>, <&usb_extal>, <&usb_xtal>;
|
||||
clock-names = "ehci_ohci", "usb_extal", "usb_xtal";
|
||||
#clock-cells = <0>;
|
||||
};
|
@ -50,5 +50,4 @@ Examples
|
||||
clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -1,12 +1,14 @@
|
||||
* Rockchip RK3128 Clock and Reset Unit
|
||||
* Rockchip RK3126/RK3128 Clock and Reset Unit
|
||||
|
||||
The RK3128 clock controller generates and supplies clock to various
|
||||
The RK3126/RK3128 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "rockchip,rk3128-cru"
|
||||
- compatible: should be "rockchip,rk3126-cru" or "rockchip,rk3128-cru"
|
||||
"rockchip,rk3126-cru" - controller compatible with RK3126 SoC.
|
||||
"rockchip,rk3128-cru" - controller compatible with RK3128 SoC.
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
|
@ -46,5 +46,4 @@ Example: UART controller node that consumes the clock generated by the clock
|
||||
interrupts = <1 23 3 4>, <1 23 4 4>;
|
||||
clock-names = "uart", "clk_uart_baud2";
|
||||
clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -46,5 +46,4 @@ Example: UART controller node that consumes the clock generated by the clock
|
||||
clock-names = "uart", "clk_uart_baud2", "clk_uart_baud3";
|
||||
clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
|
||||
<&clocks SCLK_UART>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -52,5 +52,4 @@ Example: UART controller node that consumes the clock generated by the clock
|
||||
"clk_uart_baud3";
|
||||
clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
|
||||
<&clocks SCLK_UART>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -73,5 +73,4 @@ Example: UART controller node that consumes the clock generated by the clock
|
||||
"clk_uart_baud3";
|
||||
clocks = <&clock PCLK_UART0>, <&clocks PCLK_UART0>,
|
||||
<&clock SCLK_UART>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -74,5 +74,4 @@ Example: UART controller node that consumes the clock generated by the clock
|
||||
"clk_uart_baud1";
|
||||
clocks = <&clocks UART0>, <&clocks UART0>,
|
||||
<&clocks SCLK_UART0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -12,7 +12,11 @@ generators can be found in [1].
|
||||
==I2C device node==
|
||||
|
||||
Required properties:
|
||||
- compatible: shall be one of "silabs,si5351{a,a-msop,b,c}".
|
||||
- compatible: shall be one of the following:
|
||||
"silabs,si5351a" - Si5351a, QFN20 package
|
||||
"silabs,si5351a-msop" - Si5351a, MSOP10 package
|
||||
"silabs,si5351b" - Si5351b, QFN20 package
|
||||
"silabs,si5351c" - Si5351c, QFN20 package
|
||||
- reg: i2c device address, shall be 0x60 or 0x61.
|
||||
- #clock-cells: from common clock binding; shall be set to 1.
|
||||
- clocks: from common clock binding; list of parent clock
|
||||
|
28
Bindings/clock/snps,hsdk-pll-clock.txt
Normal file
28
Bindings/clock/snps,hsdk-pll-clock.txt
Normal file
@ -0,0 +1,28 @@
|
||||
Binding for the HSDK Generic PLL clock
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "snps,hsdk-<name>-pll-clock"
|
||||
"snps,hsdk-core-pll-clock"
|
||||
"snps,hsdk-gp-pll-clock"
|
||||
"snps,hsdk-hdmi-pll-clock"
|
||||
- reg : should contain base register location and length.
|
||||
- clocks: shall be the input parent clock phandle for the PLL.
|
||||
- #clock-cells: from common clock binding; Should always be set to 0.
|
||||
|
||||
Example:
|
||||
input_clk: input-clk {
|
||||
clock-frequency = <33333333>;
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
cpu_clk: cpu-clk@0 {
|
||||
compatible = "snps,hsdk-core-pll-clock";
|
||||
reg = <0x00 0x10>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&input_clk>;
|
||||
};
|
28
Bindings/clock/snps,pll-clock.txt
Normal file
28
Bindings/clock/snps,pll-clock.txt
Normal file
@ -0,0 +1,28 @@
|
||||
Binding for the AXS10X Generic PLL clock
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "snps,axs10x-<name>-pll-clock"
|
||||
"snps,axs10x-arc-pll-clock"
|
||||
"snps,axs10x-pgu-pll-clock"
|
||||
- reg: should always contain 2 pairs address - length: first for PLL config
|
||||
registers and second for corresponding LOCK CGU register.
|
||||
- clocks: shall be the input parent clock phandle for the PLL.
|
||||
- #clock-cells: from common clock binding; Should always be set to 0.
|
||||
|
||||
Example:
|
||||
input-clk: input-clk {
|
||||
clock-frequency = <33333333>;
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
core-clk: core-clk@80 {
|
||||
compatible = "snps,axs10x-arc-pll-clock";
|
||||
reg = <0x80 0x10>, <0x100 0x10>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&input-clk>;
|
||||
};
|
71
Bindings/clock/st,stm32h7-rcc.txt
Normal file
71
Bindings/clock/st,stm32h7-rcc.txt
Normal file
@ -0,0 +1,71 @@
|
||||
STMicroelectronics STM32H7 Reset and Clock Controller
|
||||
=====================================================
|
||||
|
||||
The RCC IP is both a reset and a clock controller.
|
||||
|
||||
Please refer to clock-bindings.txt for common clock controller binding usage.
|
||||
Please also refer to reset.txt for common reset controller binding usage.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be:
|
||||
"st,stm32h743-rcc"
|
||||
|
||||
- reg: should be register base and length as documented in the
|
||||
datasheet
|
||||
|
||||
- #reset-cells: 1, see below
|
||||
|
||||
- #clock-cells : from common clock binding; shall be set to 1
|
||||
|
||||
- clocks: External oscillator clock phandle
|
||||
- high speed external clock signal (HSE)
|
||||
- low speed external clock signal (LSE)
|
||||
- external I2S clock (I2S_CKIN)
|
||||
|
||||
Optional properties:
|
||||
- st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain
|
||||
write protection (RTC clock).
|
||||
|
||||
Example:
|
||||
|
||||
rcc: reset-clock-controller@58024400 {
|
||||
compatible = "st,stm32h743-rcc", "st,stm32-rcc";
|
||||
reg = <0x58024400 0x400>;
|
||||
#reset-cells = <1>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s_ckin>;
|
||||
|
||||
st,syscfg = <&pwrcfg>;
|
||||
};
|
||||
|
||||
The peripheral clock consumer should specify the desired clock by
|
||||
having the clock ID in its "clocks" phandle cell.
|
||||
|
||||
Example:
|
||||
|
||||
timer5: timer@40000c00 {
|
||||
compatible = "st,stm32-timer";
|
||||
reg = <0x40000c00 0x400>;
|
||||
interrupts = <50>;
|
||||
clocks = <&rcc TIM5_CK>;
|
||||
};
|
||||
|
||||
Specifying softreset control of devices
|
||||
=======================================
|
||||
|
||||
Device nodes should specify the reset channel required in their "resets"
|
||||
property, containing a phandle to the reset device node and an index specifying
|
||||
which channel to use.
|
||||
The index is the bit number within the RCC registers bank, starting from RCC
|
||||
base address.
|
||||
It is calculated as: index = register_offset / 4 * 32 + bit_offset.
|
||||
Where bit_offset is the bit offset within the register.
|
||||
|
||||
For example, for CRC reset:
|
||||
crc = AHB4RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x88 / 4 * 32 + 19 = 1107
|
||||
|
||||
Example:
|
||||
|
||||
timer2 {
|
||||
resets = <&rcc STM32H7_APB1L_RESET(TIM2)>;
|
||||
};
|
@ -3,18 +3,24 @@ Allwinner Clock Control Unit Binding
|
||||
|
||||
Required properties :
|
||||
- compatible: must contain one of the following compatibles:
|
||||
- "allwinner,sun4i-a10-ccu"
|
||||
- "allwinner,sun5i-a10s-ccu"
|
||||
- "allwinner,sun5i-a13-ccu"
|
||||
- "allwinner,sun6i-a31-ccu"
|
||||
- "allwinner,sun7i-a20-ccu"
|
||||
- "allwinner,sun8i-a23-ccu"
|
||||
- "allwinner,sun8i-a33-ccu"
|
||||
- "allwinner,sun8i-a83t-ccu"
|
||||
- "allwinner,sun8i-a83t-r-ccu"
|
||||
- "allwinner,sun8i-h3-ccu"
|
||||
- "allwinner,sun8i-h3-r-ccu"
|
||||
+ - "allwinner,sun8i-r40-ccu"
|
||||
- "allwinner,sun8i-v3s-ccu"
|
||||
- "allwinner,sun9i-a80-ccu"
|
||||
- "allwinner,sun50i-a64-ccu"
|
||||
- "allwinner,sun50i-a64-r-ccu"
|
||||
- "allwinner,sun50i-h5-ccu"
|
||||
- "nextthing,gr8-ccu"
|
||||
|
||||
- reg: Must contain the registers base address and length
|
||||
- clocks: phandle to the oscillators feeding the CCU. Two are needed:
|
||||
|
@ -14,10 +14,9 @@ Required properties:
|
||||
- compatible: Must be "ti,k2g-sci-clk"
|
||||
- #clock-cells: Shall be 2.
|
||||
In clock consumers, this cell represents the device ID and clock ID
|
||||
exposed by the PM firmware. The assignments can be found in the header
|
||||
files <dt-bindings/genpd/<soc>.h> (which covers the device IDs) and
|
||||
<dt-bindings/clock/<soc>.h> (which covers the clock IDs), where <soc>
|
||||
is the SoC involved, for example 'k2g'.
|
||||
exposed by the PM firmware. The list of valid values for the device IDs
|
||||
and clocks IDs for 66AK2G SoC are documented at
|
||||
http://processors.wiki.ti.com/index.php/TISCI#66AK2G02_Data
|
||||
|
||||
Examples:
|
||||
--------
|
||||
|
@ -81,13 +81,11 @@ atl: atl@4843c000 {
|
||||
<&atl_clkin2_ck>, <&atl_clkin3_ck>;
|
||||
clocks = <&atl_gfclk_mux>;
|
||||
clock-names = "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
#include <dt-bindings/clk/ti-dra7-atl.h>
|
||||
|
||||
&atl {
|
||||
status = "okay";
|
||||
|
||||
atl2 {
|
||||
bws = <DRA7_ATL_WS_MCASP2_FSX>;
|
||||
|
@ -6,7 +6,6 @@ System clock
|
||||
|
||||
Required properties:
|
||||
- compatible: should be one of the following:
|
||||
"socionext,uniphier-sld3-clock" - for sLD3 SoC.
|
||||
"socionext,uniphier-ld4-clock" - for LD4 SoC.
|
||||
"socionext,uniphier-pro4-clock" - for Pro4 SoC.
|
||||
"socionext,uniphier-sld8-clock" - for sLD8 SoC.
|
||||
@ -14,6 +13,7 @@ Required properties:
|
||||
"socionext,uniphier-pxs2-clock" - for PXs2/LD6b SoC.
|
||||
"socionext,uniphier-ld11-clock" - for LD11 SoC.
|
||||
"socionext,uniphier-ld20-clock" - for LD20 SoC.
|
||||
"socionext,uniphier-pxs3-clock" - for PXs3 SoC
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
Example:
|
||||
@ -48,7 +48,6 @@ Media I/O (MIO) clock, SD clock
|
||||
|
||||
Required properties:
|
||||
- compatible: should be one of the following:
|
||||
"socionext,uniphier-sld3-mio-clock" - for sLD3 SoC.
|
||||
"socionext,uniphier-ld4-mio-clock" - for LD4 SoC.
|
||||
"socionext,uniphier-pro4-mio-clock" - for Pro4 SoC.
|
||||
"socionext,uniphier-sld8-mio-clock" - for sLD8 SoC.
|
||||
@ -56,6 +55,7 @@ Required properties:
|
||||
"socionext,uniphier-pxs2-sd-clock" - for PXs2/LD6b SoC.
|
||||
"socionext,uniphier-ld11-mio-clock" - for LD11 SoC.
|
||||
"socionext,uniphier-ld20-sd-clock" - for LD20 SoC.
|
||||
"socionext,uniphier-pxs3-sd-clock" - for PXs3 SoC
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
Example:
|
||||
@ -82,11 +82,9 @@ Provided clocks:
|
||||
8: USB2 ch0 host
|
||||
9: USB2 ch1 host
|
||||
10: USB2 ch2 host
|
||||
11: USB2 ch3 host
|
||||
12: USB2 ch0 PHY
|
||||
13: USB2 ch1 PHY
|
||||
14: USB2 ch2 PHY
|
||||
15: USB2 ch3 PHY
|
||||
|
||||
|
||||
Peripheral clock
|
||||
@ -94,7 +92,6 @@ Peripheral clock
|
||||
|
||||
Required properties:
|
||||
- compatible: should be one of the following:
|
||||
"socionext,uniphier-sld3-peri-clock" - for sLD3 SoC.
|
||||
"socionext,uniphier-ld4-peri-clock" - for LD4 SoC.
|
||||
"socionext,uniphier-pro4-peri-clock" - for Pro4 SoC.
|
||||
"socionext,uniphier-sld8-peri-clock" - for sLD8 SoC.
|
||||
@ -102,6 +99,7 @@ Required properties:
|
||||
"socionext,uniphier-pxs2-peri-clock" - for PXs2/LD6b SoC.
|
||||
"socionext,uniphier-ld11-peri-clock" - for LD11 SoC.
|
||||
"socionext,uniphier-ld20-peri-clock" - for LD20 SoC.
|
||||
"socionext,uniphier-pxs3-peri-clock" - for PXs3 SoC
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
Example:
|
||||
|
@ -31,5 +31,4 @@ uart0: serial@0x09405000 {
|
||||
reg = <0x09405000 0x1000>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&lsp1clk ZX296702_UART0_PCLK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -34,5 +34,4 @@ usbphy0:usb-phy0 {
|
||||
#phy-cells = <0>;
|
||||
clocks = <&topclk USB20_PHY_CLK>;
|
||||
clock-names = "phyclk";
|
||||
status = "okay";
|
||||
};
|
||||
|
247
Bindings/cpufreq/cpufreq-mediatek.txt
Normal file
247
Bindings/cpufreq/cpufreq-mediatek.txt
Normal file
@ -0,0 +1,247 @@
|
||||
Binding for MediaTek's CPUFreq driver
|
||||
=====================================
|
||||
|
||||
Required properties:
|
||||
- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
|
||||
- clock-names: Should contain the following:
|
||||
"cpu" - The multiplexer for clock input of CPU cluster.
|
||||
"intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
|
||||
source (usually MAINPLL) when the original CPU PLL is under
|
||||
transition and not stable yet.
|
||||
Please refer to Documentation/devicetree/bindings/clk/clock-bindings.txt for
|
||||
generic clock consumer properties.
|
||||
- operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp.txt
|
||||
for detail.
|
||||
- proc-supply: Regulator for Vproc of CPU cluster.
|
||||
|
||||
Optional properties:
|
||||
- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
|
||||
needs to do "voltage tracking" to step by step scale up/down Vproc and
|
||||
Vsram to fit SoC specific needs. When absent, the voltage scaling
|
||||
flow is handled by hardware, hence no software "voltage tracking" is
|
||||
needed.
|
||||
- #cooling-cells:
|
||||
- cooling-min-level:
|
||||
- cooling-max-level:
|
||||
Please refer to Documentation/devicetree/bindings/thermal/thermal.txt
|
||||
for detail.
|
||||
|
||||
Example 1 (MT7623 SoC):
|
||||
|
||||
cpu_opp_table: opp_table {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp-598000000 {
|
||||
opp-hz = /bits/ 64 <598000000>;
|
||||
opp-microvolt = <1050000>;
|
||||
};
|
||||
|
||||
opp-747500000 {
|
||||
opp-hz = /bits/ 64 <747500000>;
|
||||
opp-microvolt = <1050000>;
|
||||
};
|
||||
|
||||
opp-1040000000 {
|
||||
opp-hz = /bits/ 64 <1040000000>;
|
||||
opp-microvolt = <1150000>;
|
||||
};
|
||||
|
||||
opp-1196000000 {
|
||||
opp-hz = /bits/ 64 <1196000000>;
|
||||
opp-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
opp-1300000000 {
|
||||
opp-hz = /bits/ 64 <1300000000>;
|
||||
opp-microvolt = <1300000>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x0>;
|
||||
clocks = <&infracfg CLK_INFRA_CPUSEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
#cooling-cells = <2>;
|
||||
cooling-min-level = <0>;
|
||||
cooling-max-level = <7>;
|
||||
};
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x1>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
};
|
||||
cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x2>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
};
|
||||
cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x3>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
};
|
||||
|
||||
Example 2 (MT8173 SoC):
|
||||
cpu_opp_table_a: opp_table_a {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp-507000000 {
|
||||
opp-hz = /bits/ 64 <507000000>;
|
||||
opp-microvolt = <859000>;
|
||||
};
|
||||
|
||||
opp-702000000 {
|
||||
opp-hz = /bits/ 64 <702000000>;
|
||||
opp-microvolt = <908000>;
|
||||
};
|
||||
|
||||
opp-1001000000 {
|
||||
opp-hz = /bits/ 64 <1001000000>;
|
||||
opp-microvolt = <983000>;
|
||||
};
|
||||
|
||||
opp-1105000000 {
|
||||
opp-hz = /bits/ 64 <1105000000>;
|
||||
opp-microvolt = <1009000>;
|
||||
};
|
||||
|
||||
opp-1183000000 {
|
||||
opp-hz = /bits/ 64 <1183000000>;
|
||||
opp-microvolt = <1028000>;
|
||||
};
|
||||
|
||||
opp-1404000000 {
|
||||
opp-hz = /bits/ 64 <1404000000>;
|
||||
opp-microvolt = <1083000>;
|
||||
};
|
||||
|
||||
opp-1508000000 {
|
||||
opp-hz = /bits/ 64 <1508000000>;
|
||||
opp-microvolt = <1109000>;
|
||||
};
|
||||
|
||||
opp-1573000000 {
|
||||
opp-hz = /bits/ 64 <1573000000>;
|
||||
opp-microvolt = <1125000>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu_opp_table_b: opp_table_b {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp-507000000 {
|
||||
opp-hz = /bits/ 64 <507000000>;
|
||||
opp-microvolt = <828000>;
|
||||
};
|
||||
|
||||
opp-702000000 {
|
||||
opp-hz = /bits/ 64 <702000000>;
|
||||
opp-microvolt = <867000>;
|
||||
};
|
||||
|
||||
opp-1001000000 {
|
||||
opp-hz = /bits/ 64 <1001000000>;
|
||||
opp-microvolt = <927000>;
|
||||
};
|
||||
|
||||
opp-1209000000 {
|
||||
opp-hz = /bits/ 64 <1209000000>;
|
||||
opp-microvolt = <968000>;
|
||||
};
|
||||
|
||||
opp-1404000000 {
|
||||
opp-hz = /bits/ 64 <1007000000>;
|
||||
opp-microvolt = <1028000>;
|
||||
};
|
||||
|
||||
opp-1612000000 {
|
||||
opp-hz = /bits/ 64 <1612000000>;
|
||||
opp-microvolt = <1049000>;
|
||||
};
|
||||
|
||||
opp-1807000000 {
|
||||
opp-hz = /bits/ 64 <1807000000>;
|
||||
opp-microvolt = <1089000>;
|
||||
};
|
||||
|
||||
opp-1989000000 {
|
||||
opp-hz = /bits/ 64 <1989000000>;
|
||||
opp-microvolt = <1125000>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x000>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
clocks = <&infracfg CLK_INFRA_CA53SEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
operating-points-v2 = <&cpu_opp_table_a>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x001>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
clocks = <&infracfg CLK_INFRA_CA53SEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
operating-points-v2 = <&cpu_opp_table_a>;
|
||||
};
|
||||
|
||||
cpu2: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x100>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
clocks = <&infracfg CLK_INFRA_CA57SEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
operating-points-v2 = <&cpu_opp_table_b>;
|
||||
};
|
||||
|
||||
cpu3: cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x101>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
clocks = <&infracfg CLK_INFRA_CA57SEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
operating-points-v2 = <&cpu_opp_table_b>;
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
proc-supply = <&mt6397_vpca15_reg>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
proc-supply = <&mt6397_vpca15_reg>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
proc-supply = <&da9211_vcpu_reg>;
|
||||
sram-supply = <&mt6397_vsramca7_reg>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
proc-supply = <&da9211_vcpu_reg>;
|
||||
sram-supply = <&mt6397_vsramca7_reg>;
|
||||
};
|
16
Bindings/crypto/artpec6-crypto.txt
Normal file
16
Bindings/crypto/artpec6-crypto.txt
Normal file
@ -0,0 +1,16 @@
|
||||
Axis crypto engine with PDMA interface.
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be one of the following strings:
|
||||
"axis,artpec6-crypto" for the version in the Axis ARTPEC-6 SoC
|
||||
"axis,artpec7-crypto" for the version in the Axis ARTPEC-7 SoC.
|
||||
- reg: Base address and size for the PDMA register area.
|
||||
- interrupts: Interrupt handle for the PDMA interrupt line.
|
||||
|
||||
Example:
|
||||
|
||||
crypto@f4264000 {
|
||||
compatible = "axis,artpec6-crypto";
|
||||
reg = <0xf4264000 0x1000>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
@ -66,3 +66,16 @@ sha@f8034000 {
|
||||
dmas = <&dma1 2 17>;
|
||||
dma-names = "tx";
|
||||
};
|
||||
|
||||
* Eliptic Curve Cryptography (I2C)
|
||||
|
||||
Required properties:
|
||||
- compatible : must be "atmel,atecc508a".
|
||||
- reg: I2C bus address of the device.
|
||||
- clock-frequency: must be present in the i2c controller node.
|
||||
|
||||
Example:
|
||||
atecc508a@C0 {
|
||||
compatible = "atmel,atecc508a";
|
||||
reg = <0xC0>;
|
||||
};
|
||||
|
@ -13,5 +13,4 @@ dcp@80028000 {
|
||||
compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
|
||||
reg = <0x80028000 0x2000>;
|
||||
interrupts = <52 53>;
|
||||
status = "okay";
|
||||
};
|
||||
|
@ -23,5 +23,4 @@ Example:
|
||||
interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3",
|
||||
"eip";
|
||||
clocks = <&cpm_syscon0 1 26>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -41,5 +41,4 @@ Examples:
|
||||
clock-names = "cesa0", "cesa1";
|
||||
marvell,crypto-srams = <&crypto_sram0>, <&crypto_sram1>;
|
||||
marvell,crypto-sram-size = <0x600>;
|
||||
status = "okay";
|
||||
};
|
||||
|
@ -29,5 +29,4 @@ Examples:
|
||||
interrupts = <22>;
|
||||
marvell,crypto-srams = <&crypto_sram>;
|
||||
marvell,crypto-sram-size = <0x600>;
|
||||
status = "okay";
|
||||
};
|
||||
|
@ -25,5 +25,4 @@ Examples:
|
||||
clock-names = "aclk", "hclk", "sclk", "apb_pclk";
|
||||
resets = <&cru SRST_CRYPTO>;
|
||||
reset-names = "crypto-rst";
|
||||
status = "okay";
|
||||
};
|
||||
|
30
Bindings/crypto/st,stm32-hash.txt
Normal file
30
Bindings/crypto/st,stm32-hash.txt
Normal file
@ -0,0 +1,30 @@
|
||||
* STMicroelectronics STM32 HASH
|
||||
|
||||
Required properties:
|
||||
- compatible: Should contain entries for this and backward compatible
|
||||
HASH versions:
|
||||
- "st,stm32f456-hash" for stm32 F456.
|
||||
- "st,stm32f756-hash" for stm32 F756.
|
||||
- reg: The address and length of the peripheral registers space
|
||||
- interrupts: the interrupt specifier for the HASH
|
||||
- clocks: The input clock of the HASH instance
|
||||
|
||||
Optional properties:
|
||||
- resets: The input reset of the HASH instance
|
||||
- dmas: DMA specifiers for the HASH. See the DMA client binding,
|
||||
Documentation/devicetree/bindings/dma/dma.txt
|
||||
- dma-names: DMA request name. Should be "in" if a dma is present.
|
||||
- dma-maxburst: Set number of maximum dma burst supported
|
||||
|
||||
Example:
|
||||
|
||||
hash1: hash@50060400 {
|
||||
compatible = "st,stm32f756-hash";
|
||||
reg = <0x50060400 0x400>;
|
||||
interrupts = <80>;
|
||||
clocks = <&rcc 0 STM32F7_AHB2_CLOCK(HASH)>;
|
||||
resets = <&rcc STM32F7_AHB2_RESET(HASH)>;
|
||||
dmas = <&dma2 7 2 0x400 0x0>;
|
||||
dma-names = "in";
|
||||
dma-maxburst = <0>;
|
||||
};
|
@ -15,5 +15,4 @@ Example:
|
||||
rockchip,pmu = <&pmugrf>;
|
||||
clocks = <&cru PCLK_DDR_MON>;
|
||||
clock-names = "pclk_ddr_mon";
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -205,5 +205,4 @@ Example:
|
||||
rockchip,phy_lpddr4_ck_cs_drv = <PHY_DRV_ODT_80>;
|
||||
rockchip,phy_lpddr4_dq_drv = <PHY_DRV_ODT_80>;
|
||||
rockchip,phy_lpddr4_odt = <PHY_DRV_ODT_60>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -34,7 +34,6 @@ Example:
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fb>;
|
||||
display = <&display0>;
|
||||
status = "okay";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
|
@ -23,7 +23,6 @@ Example:
|
||||
interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
|
||||
clock-names = "periph_clk","sys_clk", "slow_clk";
|
||||
status = "disabled";
|
||||
|
||||
hlcdc-display-controller {
|
||||
compatible = "atmel,hlcdc-display-controller";
|
||||
|
32
Bindings/display/bridge/dw_mipi_dsi.txt
Normal file
32
Bindings/display/bridge/dw_mipi_dsi.txt
Normal file
@ -0,0 +1,32 @@
|
||||
Synopsys DesignWare MIPI DSI host controller
|
||||
============================================
|
||||
|
||||
This document defines device tree properties for the Synopsys DesignWare MIPI
|
||||
DSI host controller. It doesn't constitue a device tree binding specification
|
||||
by itself but is meant to be referenced by platform-specific device tree
|
||||
bindings.
|
||||
|
||||
When referenced from platform device tree bindings the properties defined in
|
||||
this document are defined as follows. The platform device tree bindings are
|
||||
responsible for defining whether each optional property is used or not.
|
||||
|
||||
- reg: Memory mapped base address and length of the DesignWare MIPI DSI
|
||||
host controller registers. (mandatory)
|
||||
|
||||
- clocks: References to all the clocks specified in the clock-names property
|
||||
as specified in [1]. (mandatory)
|
||||
|
||||
- clock-names:
|
||||
- "pclk" is the peripheral clock for either AHB and APB. (mandatory)
|
||||
- "px_clk" is the pixel clock for the DPI/RGB input. (optional)
|
||||
|
||||
- resets: References to all the resets specified in the reset-names property
|
||||
as specified in [2]. (optional)
|
||||
|
||||
- reset-names: string reset name, must be "apb" if used. (optional)
|
||||
|
||||
- panel or bridge node: see [3]. (mandatory)
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/reset/reset.txt
|
||||
[3] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
|
@ -33,7 +33,6 @@ stdp2690-ge-b850v3-fw required properties:
|
||||
Example:
|
||||
|
||||
&mux2_i2c2 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
stdp4028@73 {
|
||||
|
@ -13,6 +13,7 @@ Required properties:
|
||||
|
||||
- compatible : Shall contain one or more of
|
||||
- "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX
|
||||
- "renesas,r8a7796-hdmi" for R8A7796 (R-Car M3-W) compatible HDMI TX
|
||||
- "renesas,rcar-gen3-hdmi" for the generic R-Car Gen3 compatible HDMI TX
|
||||
|
||||
When compatible with generic versions, nodes must list the SoC-specific
|
||||
@ -43,7 +44,6 @@ Example:
|
||||
clocks = <&cpg CPG_CORE R8A7795_CLK_S0D4>, <&cpg CPG_MOD 729>;
|
||||
clock-names = "iahb", "isfr";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
|
@ -25,12 +25,6 @@ Required properties:
|
||||
size-cells must 1 and 0, respectively.
|
||||
- port: contains an endpoint node which is connected to the endpoint in the mic
|
||||
node. The reg value muset be 0.
|
||||
- i80-if-timings: specify whether the panel which is connected to decon uses
|
||||
i80 lcd interface or mipi video interface. This node contains
|
||||
no timing information as that of fimd does. Because there is
|
||||
no register in decon to specify i80 interface timing value,
|
||||
it is not needed, but make it remain to use same kind of node
|
||||
in fimd and exynos7 decon.
|
||||
|
||||
Example:
|
||||
SoC specific DT entry:
|
||||
@ -59,9 +53,3 @@ decon: decon@13800000 {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Board specific DT entry:
|
||||
&decon {
|
||||
i80-if-timings {
|
||||
};
|
||||
};
|
||||
|
@ -14,5 +14,4 @@ timing-controller@4003d000 {
|
||||
reg = <0x4003d000 0x1000>;
|
||||
clocks = <&clks VF610_CLK_TCON0>;
|
||||
clock-names = "ipg";
|
||||
status = "okay";
|
||||
};
|
||||
|
@ -116,7 +116,7 @@ Parallel display support
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx-parallel-display"
|
||||
Optional properties:
|
||||
- interface_pix_fmt: How this display is connected to the
|
||||
- interface-pix-fmt: How this display is connected to the
|
||||
display interface. Currently supported types: "rgb24", "rgb565", "bgr666"
|
||||
and "lvds666".
|
||||
- edid: verbatim EDID data block describing attached display.
|
||||
|
@ -23,7 +23,6 @@ Example:
|
||||
reg = <0x44000000 0x10000>;
|
||||
interrupts = <17>;
|
||||
clocks = <&clks CLK_LCD>;
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
lcdc_out: endpoint {
|
||||
|
@ -18,6 +18,5 @@ Example:
|
||||
power-supply = <...>;
|
||||
backlight = <&backlight>;
|
||||
enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
@ -36,8 +36,10 @@ Required Properties:
|
||||
When supplied they must be named "dclkin.x" with "x" being the input
|
||||
clock numerical index.
|
||||
|
||||
- vsps: A list of phandles to the VSP nodes that handle the memory
|
||||
interfaces for the DU channels.
|
||||
- vsps: A list of phandle and channel index tuples to the VSPs that handle
|
||||
the memory interfaces for the DU channels. The phandle identifies the VSP
|
||||
instance that serves the DU channel, and the channel index identifies the
|
||||
LIF instance in that VSP.
|
||||
|
||||
Required nodes:
|
||||
|
||||
@ -59,24 +61,24 @@ corresponding to each DU output.
|
||||
R8A7796 (M3-W) DPAD HDMI LVDS -
|
||||
|
||||
|
||||
Example: R8A7790 (R-Car H2) DU
|
||||
Example: R8A7795 (R-Car H3) ES2.0 DU
|
||||
|
||||
du: du@feb00000 {
|
||||
compatible = "renesas,du-r8a7790";
|
||||
reg = <0 0xfeb00000 0 0x70000>,
|
||||
<0 0xfeb90000 0 0x1c>,
|
||||
<0 0xfeb94000 0 0x1c>;
|
||||
reg-names = "du", "lvds.0", "lvds.1";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 268 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 269 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp7_clks R8A7790_CLK_DU0>,
|
||||
<&mstp7_clks R8A7790_CLK_DU1>,
|
||||
<&mstp7_clks R8A7790_CLK_DU2>,
|
||||
<&mstp7_clks R8A7790_CLK_LVDS0>,
|
||||
<&mstp7_clks R8A7790_CLK_LVDS1>;
|
||||
clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
|
||||
du: display@feb00000 {
|
||||
compatible = "renesas,du-r8a7795";
|
||||
reg = <0 0xfeb00000 0 0x80000>,
|
||||
<0 0xfeb90000 0 0x14>;
|
||||
reg-names = "du", "lvds.0";
|
||||
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 722>,
|
||||
<&cpg CPG_MOD 721>,
|
||||
<&cpg CPG_MOD 727>;
|
||||
clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0";
|
||||
vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
@ -89,12 +91,19 @@ Example: R8A7790 (R-Car H2) DU
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
du_out_lvds0: endpoint {
|
||||
du_out_hdmi0: endpoint {
|
||||
remote-endpoint = <&dw_hdmi0_in>;
|
||||
};
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
du_out_lvds1: endpoint {
|
||||
du_out_hdmi1: endpoint {
|
||||
remote-endpoint = <&dw_hdmi1_in>;
|
||||
};
|
||||
};
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
du_out_lvds0: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
52
Bindings/display/repaper.txt
Normal file
52
Bindings/display/repaper.txt
Normal file
@ -0,0 +1,52 @@
|
||||
Pervasive Displays RePaper branded e-ink displays
|
||||
|
||||
Required properties:
|
||||
- compatible: "pervasive,e1144cs021" for 1.44" display
|
||||
"pervasive,e1190cs021" for 1.9" display
|
||||
"pervasive,e2200cs021" for 2.0" display
|
||||
"pervasive,e2271cs021" for 2.7" display
|
||||
|
||||
- panel-on-gpios: Timing controller power control
|
||||
- discharge-gpios: Discharge control
|
||||
- reset-gpios: RESET pin
|
||||
- busy-gpios: BUSY pin
|
||||
|
||||
Required property for e2271cs021:
|
||||
- border-gpios: Border control
|
||||
|
||||
The node for this driver must be a child node of a SPI controller, hence
|
||||
all mandatory properties described in ../spi/spi-bus.txt must be specified.
|
||||
|
||||
Optional property:
|
||||
- pervasive,thermal-zone: name of thermometer's thermal zone
|
||||
|
||||
Example:
|
||||
|
||||
display_temp: lm75@48 {
|
||||
compatible = "lm75b";
|
||||
reg = <0x48>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
display {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&display_temp>;
|
||||
};
|
||||
};
|
||||
|
||||
papirus27@0{
|
||||
compatible = "pervasive,e2271cs021";
|
||||
reg = <0>;
|
||||
|
||||
spi-max-frequency = <8000000>;
|
||||
|
||||
panel-on-gpios = <&gpio 23 0>;
|
||||
border-gpios = <&gpio 14 0>;
|
||||
discharge-gpios = <&gpio 15 0>;
|
||||
reset-gpios = <&gpio 24 0>;
|
||||
busy-gpios = <&gpio 25 0>;
|
||||
|
||||
pervasive,thermal-zone = "display";
|
||||
};
|
@ -59,7 +59,6 @@ Example:
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&edp_hpd>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
|
@ -11,7 +11,9 @@ following device-specific properties.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Shall contain "rockchip,rk3288-dw-hdmi".
|
||||
- compatible: should be one of the following:
|
||||
"rockchip,rk3288-dw-hdmi"
|
||||
"rockchip,rk3399-dw-hdmi"
|
||||
- reg: See dw_hdmi.txt.
|
||||
- reg-io-width: See dw_hdmi.txt. Shall be 4.
|
||||
- interrupts: HDMI interrupt number
|
||||
@ -30,7 +32,8 @@ Optional properties
|
||||
I2C master controller.
|
||||
- clock-names: See dw_hdmi.txt. The "cec" clock is optional.
|
||||
- clock-names: May contain "cec" as defined in dw_hdmi.txt.
|
||||
|
||||
- clock-names: May contain "grf", power for grf io.
|
||||
- clock-names: May contain "vpll", external clock for some hdmi phy.
|
||||
|
||||
Example:
|
||||
|
||||
@ -43,7 +46,6 @@ hdmi: hdmi@ff980000 {
|
||||
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
|
||||
clock-names = "iahb", "isfr";
|
||||
status = "disabled";
|
||||
ports {
|
||||
hdmi_in: port {
|
||||
#address-cells = <1>;
|
||||
|
@ -36,7 +36,6 @@ Example:
|
||||
resets = <&cru SRST_MIPIDSI0>;
|
||||
reset-names = "apb";
|
||||
rockchip,grf = <&grf>;
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
@ -65,6 +64,5 @@ Example:
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&lcd_en>;
|
||||
backlight = <&backlight>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
@ -25,7 +25,6 @@ hdmi: hdmi@20034000 {
|
||||
clock-names = "pclk";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmi_ctl>;
|
||||
status = "disabled";
|
||||
|
||||
hdmi_in: port {
|
||||
#address-cells = <1>;
|
||||
|
@ -8,8 +8,12 @@ Required properties:
|
||||
- compatible: value should be one of the following
|
||||
"rockchip,rk3036-vop";
|
||||
"rockchip,rk3288-vop";
|
||||
"rockchip,rk3368-vop";
|
||||
"rockchip,rk3366-vop";
|
||||
"rockchip,rk3399-vop-big";
|
||||
"rockchip,rk3399-vop-lit";
|
||||
"rockchip,rk3228-vop";
|
||||
"rockchip,rk3328-vop";
|
||||
|
||||
- interrupts: should contain a list of all VOP IP block interrupts in the
|
||||
order: VSYNC, LCD_SYSTEM. The interrupt specifier
|
||||
|
@ -28,6 +28,5 @@ chosen {
|
||||
allwinner,pipeline = "de_be0-lcd0-hdmi";
|
||||
clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
|
||||
<&ahb_gates 44>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
22
Bindings/display/sitronix,st7586.txt
Normal file
22
Bindings/display/sitronix,st7586.txt
Normal file
@ -0,0 +1,22 @@
|
||||
Sitronix ST7586 display panel
|
||||
|
||||
Required properties:
|
||||
- compatible: "lego,ev3-lcd".
|
||||
- a0-gpios: The A0 signal (since this binding is for serial mode, this is
|
||||
the pin labeled D1 on the controller, not the pin labeled A0)
|
||||
- reset-gpios: Reset pin
|
||||
|
||||
The node for this driver must be a child node of a SPI controller, hence
|
||||
all mandatory properties described in ../spi/spi-bus.txt must be specified.
|
||||
|
||||
Optional properties:
|
||||
- rotation: panel rotation in degrees counter clockwise (0,90,180,270)
|
||||
|
||||
Example:
|
||||
display@0{
|
||||
compatible = "lego,ev3-lcd";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <10000000>;
|
||||
a0-gpios = <&gpio 43 GPIO_ACTIVE_HIGH>;
|
||||
reset-gpios = <&gpio 80 GPIO_ACTIVE_HIGH>;
|
||||
};
|
@ -1,7 +1,6 @@
|
||||
* STMicroelectronics STM32 lcd-tft display controller
|
||||
|
||||
- ltdc: lcd-tft display controller host
|
||||
must be a sub-node of st-display-subsystem
|
||||
Required properties:
|
||||
- compatible: "st,stm32-ltdc"
|
||||
- reg: Physical base address of the IP registers and length of memory mapped region.
|
||||
@ -13,8 +12,40 @@
|
||||
Required nodes:
|
||||
- Video port for RGB output.
|
||||
|
||||
Example:
|
||||
* STMicroelectronics STM32 DSI controller specific extensions to Synopsys
|
||||
DesignWare MIPI DSI host controller
|
||||
|
||||
The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI
|
||||
DSI host controller. For all mandatory properties & nodes, please refer
|
||||
to the related documentation in [5].
|
||||
|
||||
Mandatory properties specific to STM32 DSI:
|
||||
- #address-cells: Should be <1>.
|
||||
- #size-cells: Should be <0>.
|
||||
- compatible: "st,stm32-dsi".
|
||||
- clock-names:
|
||||
- phy pll reference clock string name, must be "ref".
|
||||
- resets: see [5].
|
||||
- reset-names: see [5].
|
||||
|
||||
Mandatory nodes specific to STM32 DSI:
|
||||
- ports: A node containing DSI input & output port nodes with endpoint
|
||||
definitions as documented in [3] & [4].
|
||||
- port@0: DSI input port node, connected to the ltdc rgb output port.
|
||||
- port@1: DSI output port node, connected to a panel or a bridge input port.
|
||||
- panel or bridge node: A node containing the panel or bridge description as
|
||||
documented in [6].
|
||||
- port: panel or bridge port node, connected to the DSI output port (port@1).
|
||||
|
||||
Note: You can find more documentation in the following references
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/reset/reset.txt
|
||||
[3] Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
[4] Documentation/devicetree/bindings/graph.txt
|
||||
[5] Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
|
||||
[6] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
|
||||
|
||||
Example 1: RGB panel
|
||||
/ {
|
||||
...
|
||||
soc {
|
||||
@ -34,3 +65,73 @@ Example:
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Example 2: DSI panel
|
||||
|
||||
/ {
|
||||
...
|
||||
soc {
|
||||
...
|
||||
ltdc: display-controller@40016800 {
|
||||
compatible = "st,stm32-ltdc";
|
||||
reg = <0x40016800 0x200>;
|
||||
interrupts = <88>, <89>;
|
||||
resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
|
||||
clocks = <&rcc 1 CLK_LCD>;
|
||||
clock-names = "lcd";
|
||||
|
||||
port {
|
||||
ltdc_out_dsi: endpoint {
|
||||
remote-endpoint = <&dsi_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
dsi: dsi@40016c00 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-dsi";
|
||||
reg = <0x40016c00 0x800>;
|
||||
clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>;
|
||||
clock-names = "ref", "pclk";
|
||||
resets = <&rcc STM32F4_APB2_RESET(DSI)>;
|
||||
reset-names = "apb";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi_in: endpoint {
|
||||
remote-endpoint = <<dc_out_dsi>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi_out: endpoint {
|
||||
remote-endpoint = <&dsi_in_panel>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
panel-dsi@0 {
|
||||
reg = <0>; /* dsi virtual channel (0..3) */
|
||||
compatible = ...;
|
||||
enable-gpios = ...;
|
||||
|
||||
port {
|
||||
dsi_in_panel: endpoint {
|
||||
remote-endpoint = <&dsi_out>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
@ -4,15 +4,33 @@ Allwinner A10 Display Pipeline
|
||||
The Allwinner A10 Display pipeline is composed of several components
|
||||
that are going to be documented below:
|
||||
|
||||
For the input port of all components up to the TCON in the display
|
||||
pipeline, if there are multiple components, the local endpoint IDs
|
||||
must correspond to the index of the upstream block. For example, if
|
||||
the remote endpoint is Frontend 1, then the local endpoint ID must
|
||||
be 1.
|
||||
For all connections between components up to the TCONs in the display
|
||||
pipeline, when there are multiple components of the same type at the
|
||||
same depth, the local endpoint ID must be the same as the remote
|
||||
component's index. For example, if the remote endpoint is Frontend 1,
|
||||
then the local endpoint ID must be 1.
|
||||
|
||||
Conversely, for the output ports of the same group, the remote endpoint
|
||||
ID must be the index of the local hardware block. If the local backend
|
||||
is backend 1, then the remote endpoint ID must be 1.
|
||||
Frontend 0 [0] ------- [0] Backend 0 [0] ------- [0] TCON 0
|
||||
[1] -- -- [1] [1] -- -- [1]
|
||||
\ / \ /
|
||||
X X
|
||||
/ \ / \
|
||||
[0] -- -- [0] [0] -- -- [0]
|
||||
Frontend 1 [1] ------- [1] Backend 1 [1] ------- [1] TCON 1
|
||||
|
||||
For a two pipeline system such as the one depicted above, the lines
|
||||
represent the connections between the components, while the numbers
|
||||
within the square brackets corresponds to the ID of the local endpoint.
|
||||
|
||||
The same rule also applies to DE 2.0 mixer-TCON connections:
|
||||
|
||||
Mixer 0 [0] ----------- [0] TCON 0
|
||||
[1] ---- ---- [1]
|
||||
\ /
|
||||
X
|
||||
/ \
|
||||
[0] ---- ---- [0]
|
||||
Mixer 1 [1] ----------- [1] TCON 1
|
||||
|
||||
HDMI Encoder
|
||||
------------
|
||||
@ -260,7 +278,6 @@ hdmi: hdmi@01c16000 {
|
||||
<&dma SUN4I_DMA_NORMAL 16>,
|
||||
<&dma SUN4I_DMA_DEDICATED 24>;
|
||||
dma-names = "ddc-tx", "ddc-rx", "audio-tx";
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
|
@ -72,5 +72,4 @@ sai2: sai@40031000 {
|
||||
dma-names = "tx", "rx";
|
||||
dmas = <&edma0 0 21>,
|
||||
<&edma0 0 20>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -30,7 +30,6 @@ xor@d0060900 {
|
||||
reg = <0xd0060900 0x100
|
||||
0xd0060b00 0x100>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "okay";
|
||||
|
||||
xor00 {
|
||||
interrupts = <51>;
|
||||
|
@ -48,7 +48,6 @@ Each dmas request consists of 3 cells:
|
||||
Example:
|
||||
|
||||
spi4: spi@1a280000 {
|
||||
status = "ok";
|
||||
spi-max-frequency = <50000000>;
|
||||
|
||||
pinctrl-0 = <&spi_pins>;
|
||||
|
@ -25,6 +25,7 @@ Required Properties:
|
||||
- "renesas,dmac-r8a7794" (R-Car E2)
|
||||
- "renesas,dmac-r8a7795" (R-Car H3)
|
||||
- "renesas,dmac-r8a7796" (R-Car M3-W)
|
||||
- "renesas,dmac-r8a77970" (R-Car V3M)
|
||||
|
||||
- reg: base address and length of the registers block for the DMAC
|
||||
|
||||
|
@ -8,6 +8,7 @@ Required Properties:
|
||||
- "renesas,r8a7793-usb-dmac" (R-Car M2-N)
|
||||
- "renesas,r8a7794-usb-dmac" (R-Car E2)
|
||||
- "renesas,r8a7795-usb-dmac" (R-Car H3)
|
||||
- "renesas,r8a7796-usb-dmac" (R-Car M3-W)
|
||||
- reg: base address and length of the registers block for the DMAC
|
||||
- interrupts: interrupt specifiers for the DMAC, one for each entry in
|
||||
interrupt-names.
|
||||
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user