Remove special handling for resuming clock interrupt when using APIC_IO.
The `generic' vector stubs do the right thing.
This commit is contained in:
Tor Egge
parent
622a086be3
commit
5dd528cd4e
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=34058
@ -1,6 +1,6 @@
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/*
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* from: vector.s, 386BSD 0.1 unknown origin
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* $Id: apic_vector.s,v 1.26 1998/03/03 20:55:24 tegge Exp $
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* $Id: apic_vector.s,v 1.27 1998/03/03 22:56:28 tegge Exp $
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*/
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@ -913,21 +913,6 @@ imasks: /* masks for interrupt handlers */
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.long SWI_VM_MASK, 0
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.long SWI_CLOCK_MASK, SWI_AST_MASK
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/*
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* IDT vector entry points for the HWIs.
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*
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* used by:
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* i386/isa/clock.c: setup Xintr8254
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*/
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.globl _ivectors
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_ivectors:
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.long _Xintr0, _Xintr1, _Xintr2, _Xintr3
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.long _Xintr4, _Xintr5, _Xintr6, _Xintr7
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.long _Xintr8, _Xintr9, _Xintr10, _Xintr11
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.long _Xintr12, _Xintr13, _Xintr14, _Xintr15
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.long _Xintr16, _Xintr17, _Xintr18, _Xintr19
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.long _Xintr20, _Xintr21, _Xintr22, _Xintr23
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/* active flag for lazy masking */
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iactive:
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.long 0
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@ -34,7 +34,7 @@
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* SUCH DAMAGE.
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*
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* from: @(#)clock.c 7.2 (Berkeley) 5/12/91
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* $Id: clock.c,v 1.113 1998/02/23 00:11:25 bde Exp $
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* $Id: clock.c,v 1.114 1998/02/28 21:16:13 phk Exp $
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*/
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/*
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@ -87,6 +87,9 @@
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#ifdef SMP
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#define disable_intr() CLOCK_DISABLE_INTR()
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#define enable_intr() CLOCK_ENABLE_INTR()
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/* The interrupt triggered by the 8254 (timer) chip */
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int apic_8254_intr;
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#endif /* SMP */
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/*
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@ -949,15 +952,12 @@ cpu_initclocks()
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else
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panic("neither pin 0 or pin 2 works for 8254");
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/* setup the vectors */
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vec[x] = (u_int)vec8254;
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Xintr8254 = (u_int)ivectors[x];
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mask8254 = (1 << x);
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apic_8254_intr = x;
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register_intr(/* irq */ x, /* XXX id */ 0, /* flags */ 0,
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/* XXX */ (inthand2_t *)clkintr, &clk_imask,
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/* unit */ 0);
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INTREN(mask8254);
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INTREN(1 << x);
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#else /* APIC_IO */
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@ -3,7 +3,7 @@
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* Garrett Wollman, September 1994.
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* This file is in the public domain.
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*
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* $Id: clock.h,v 1.32 1998/02/20 16:35:27 phk Exp $
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* $Id: clock.h,v 1.33 1998/02/25 02:20:30 bde Exp $
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*/
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#ifndef _MACHINE_CLOCK_H_
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@ -21,6 +21,9 @@ extern u_int timer_freq;
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extern int timer0_max_count;
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extern u_int tsc_freq;
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extern int wall_cmos_clock;
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#ifdef APIC_IO
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extern int apic_8254_intr;
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#endif
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/*
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* Driver to clock driver interface.
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@ -6,7 +6,7 @@
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* this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp
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* ----------------------------------------------------------------------------
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*
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* $Id: smp.h,v 1.37 1998/03/03 20:55:23 tegge Exp $
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* $Id: smp.h,v 1.38 1998/03/03 22:56:26 tegge Exp $
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*
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*/
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@ -75,20 +75,13 @@ int try_mpintrlock __P((void));
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#endif /* RECURSIVE_MPINTRLOCK */
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/* global data in apic_vector.s */
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extern u_int ivectors[];
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extern volatile u_int stopped_cpus;
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extern volatile u_int started_cpus;
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extern unsigned int checkstate_probed_cpus;
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extern unsigned int checkstate_need_ast;
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/* global data in apic_ipl.s */
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extern u_int vec[];
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extern u_int Xintr8254;
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extern u_int mask8254;
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/* functions in apic_ipl.s */
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void vec8254 __P((void));
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void apic_eoi __P((void));
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u_int io_apic_read __P((int, int));
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void io_apic_write __P((int, int, u_int));
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@ -34,7 +34,7 @@
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* SUCH DAMAGE.
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*
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* from: @(#)clock.c 7.2 (Berkeley) 5/12/91
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* $Id: clock.c,v 1.113 1998/02/23 00:11:25 bde Exp $
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* $Id: clock.c,v 1.114 1998/02/28 21:16:13 phk Exp $
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*/
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/*
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@ -87,6 +87,9 @@
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#ifdef SMP
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#define disable_intr() CLOCK_DISABLE_INTR()
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#define enable_intr() CLOCK_ENABLE_INTR()
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/* The interrupt triggered by the 8254 (timer) chip */
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int apic_8254_intr;
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#endif /* SMP */
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/*
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@ -949,15 +952,12 @@ cpu_initclocks()
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else
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panic("neither pin 0 or pin 2 works for 8254");
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/* setup the vectors */
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vec[x] = (u_int)vec8254;
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Xintr8254 = (u_int)ivectors[x];
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mask8254 = (1 << x);
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apic_8254_intr = x;
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register_intr(/* irq */ x, /* XXX id */ 0, /* flags */ 0,
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/* XXX */ (inthand2_t *)clkintr, &clk_imask,
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/* unit */ 0);
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INTREN(mask8254);
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INTREN(1 << x);
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#else /* APIC_IO */
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@ -1,6 +1,6 @@
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/*
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* from: vector.s, 386BSD 0.1 unknown origin
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* $Id: apic_vector.s,v 1.26 1998/03/03 20:55:24 tegge Exp $
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* $Id: apic_vector.s,v 1.27 1998/03/03 22:56:28 tegge Exp $
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*/
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@ -913,21 +913,6 @@ imasks: /* masks for interrupt handlers */
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.long SWI_VM_MASK, 0
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.long SWI_CLOCK_MASK, SWI_AST_MASK
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/*
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* IDT vector entry points for the HWIs.
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*
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* used by:
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* i386/isa/clock.c: setup Xintr8254
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*/
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.globl _ivectors
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_ivectors:
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.long _Xintr0, _Xintr1, _Xintr2, _Xintr3
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.long _Xintr4, _Xintr5, _Xintr6, _Xintr7
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.long _Xintr8, _Xintr9, _Xintr10, _Xintr11
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.long _Xintr12, _Xintr13, _Xintr14, _Xintr15
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.long _Xintr16, _Xintr17, _Xintr18, _Xintr19
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.long _Xintr20, _Xintr21, _Xintr22, _Xintr23
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/* active flag for lazy masking */
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iactive:
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.long 0
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@ -34,7 +34,7 @@
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* SUCH DAMAGE.
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*
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* from: @(#)clock.c 7.2 (Berkeley) 5/12/91
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* $Id: clock.c,v 1.113 1998/02/23 00:11:25 bde Exp $
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* $Id: clock.c,v 1.114 1998/02/28 21:16:13 phk Exp $
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*/
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/*
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@ -87,6 +87,9 @@
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#ifdef SMP
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#define disable_intr() CLOCK_DISABLE_INTR()
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#define enable_intr() CLOCK_ENABLE_INTR()
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/* The interrupt triggered by the 8254 (timer) chip */
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int apic_8254_intr;
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#endif /* SMP */
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/*
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@ -949,15 +952,12 @@ cpu_initclocks()
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else
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panic("neither pin 0 or pin 2 works for 8254");
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/* setup the vectors */
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vec[x] = (u_int)vec8254;
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Xintr8254 = (u_int)ivectors[x];
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mask8254 = (1 << x);
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apic_8254_intr = x;
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register_intr(/* irq */ x, /* XXX id */ 0, /* flags */ 0,
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/* XXX */ (inthand2_t *)clkintr, &clk_imask,
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/* unit */ 0);
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INTREN(mask8254);
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INTREN(1 << x);
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#else /* APIC_IO */
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@ -3,7 +3,7 @@
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* Garrett Wollman, September 1994.
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* This file is in the public domain.
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*
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* $Id: clock.h,v 1.32 1998/02/20 16:35:27 phk Exp $
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* $Id: clock.h,v 1.33 1998/02/25 02:20:30 bde Exp $
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*/
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#ifndef _MACHINE_CLOCK_H_
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@ -21,6 +21,9 @@ extern u_int timer_freq;
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extern int timer0_max_count;
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extern u_int tsc_freq;
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extern int wall_cmos_clock;
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#ifdef APIC_IO
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extern int apic_8254_intr;
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#endif
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/*
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* Driver to clock driver interface.
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@ -6,7 +6,7 @@
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* this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp
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* ----------------------------------------------------------------------------
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*
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* $Id: smp.h,v 1.37 1998/03/03 20:55:23 tegge Exp $
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* $Id: smp.h,v 1.38 1998/03/03 22:56:26 tegge Exp $
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*
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*/
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@ -75,20 +75,13 @@ int try_mpintrlock __P((void));
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#endif /* RECURSIVE_MPINTRLOCK */
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/* global data in apic_vector.s */
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extern u_int ivectors[];
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extern volatile u_int stopped_cpus;
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extern volatile u_int started_cpus;
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extern unsigned int checkstate_probed_cpus;
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extern unsigned int checkstate_need_ast;
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/* global data in apic_ipl.s */
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extern u_int vec[];
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extern u_int Xintr8254;
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extern u_int mask8254;
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/* functions in apic_ipl.s */
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void vec8254 __P((void));
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void apic_eoi __P((void));
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u_int io_apic_read __P((int, int));
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void io_apic_write __P((int, int, u_int));
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@ -22,7 +22,7 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: apic_ipl.s,v 1.17 1997/12/15 02:18:33 tegge Exp $
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* $Id: apic_ipl.s,v 1.18 1998/03/03 22:56:28 tegge Exp $
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*/
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@ -37,15 +37,6 @@ _cil: .long 0
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.globl _cml
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_cml: .long 0
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/* this allows us to change the 8254 APIC pin# assignment */
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.globl _Xintr8254
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_Xintr8254:
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.long _Xintr7
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/* used by this file, microtime.s and clock.c */
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.globl _mask8254
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_mask8254:
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.long 0
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/*
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* Routines used by splz_unpend to build an interrupt frame from a
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@ -178,44 +169,6 @@ splz_swi:
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* set from the time of the original INT.
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*/
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/*
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* generic vector function for 8254 clock
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*/
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ALIGN_TEXT
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.globl _vec8254
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_vec8254:
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popl %eax /* return address */
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pushfl
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pushl $KCSEL
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pushl %eax
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movl _mask8254, %eax /* lazy masking */
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notl %eax
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cli
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lock /* MP-safe */
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andl %eax, iactive
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MEXITCOUNT
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APIC_ITRACE(apic_itrace_splz, 0, APIC_ITRACE_SPLZ)
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movl _Xintr8254, %eax
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jmp %eax /* XXX might need _Xfastintr# */
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/*
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* generic vector function for RTC clock
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*/
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ALIGN_TEXT
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vec8:
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popl %eax
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pushfl
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pushl $KCSEL
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pushl %eax
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cli
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lock /* MP-safe */
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andl $~IRQ_BIT(8), iactive /* lazy masking */
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MEXITCOUNT
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APIC_ITRACE(apic_itrace_splz, 8, APIC_ITRACE_SPLZ)
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jmp _Xintr8 /* XXX might need _Xfastintr8 */
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/*
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* The 'generic' vector stubs.
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*/
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@ -243,7 +196,7 @@ __CONCAT(vec,irq_num): ; \
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BUILD_VEC(5)
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BUILD_VEC(6)
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BUILD_VEC(7)
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/* IRQ8 is special case, done above */
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BUILD_VEC(8)
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BUILD_VEC(9)
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BUILD_VEC(10)
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BUILD_VEC(11)
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@ -1,6 +1,6 @@
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/*
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* from: vector.s, 386BSD 0.1 unknown origin
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* $Id: apic_vector.s,v 1.26 1998/03/03 20:55:24 tegge Exp $
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* $Id: apic_vector.s,v 1.27 1998/03/03 22:56:28 tegge Exp $
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*/
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@ -913,21 +913,6 @@ imasks: /* masks for interrupt handlers */
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.long SWI_VM_MASK, 0
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.long SWI_CLOCK_MASK, SWI_AST_MASK
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/*
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* IDT vector entry points for the HWIs.
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*
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* used by:
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* i386/isa/clock.c: setup Xintr8254
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*/
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.globl _ivectors
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_ivectors:
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.long _Xintr0, _Xintr1, _Xintr2, _Xintr3
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.long _Xintr4, _Xintr5, _Xintr6, _Xintr7
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.long _Xintr8, _Xintr9, _Xintr10, _Xintr11
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.long _Xintr12, _Xintr13, _Xintr14, _Xintr15
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.long _Xintr16, _Xintr17, _Xintr18, _Xintr19
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.long _Xintr20, _Xintr21, _Xintr22, _Xintr23
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/* active flag for lazy masking */
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iactive:
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.long 0
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@ -34,7 +34,7 @@
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* SUCH DAMAGE.
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*
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* from: @(#)clock.c 7.2 (Berkeley) 5/12/91
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* $Id: clock.c,v 1.113 1998/02/23 00:11:25 bde Exp $
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* $Id: clock.c,v 1.114 1998/02/28 21:16:13 phk Exp $
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*/
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/*
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@ -87,6 +87,9 @@
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#ifdef SMP
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#define disable_intr() CLOCK_DISABLE_INTR()
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#define enable_intr() CLOCK_ENABLE_INTR()
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/* The interrupt triggered by the 8254 (timer) chip */
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int apic_8254_intr;
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#endif /* SMP */
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/*
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@ -949,15 +952,12 @@ cpu_initclocks()
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else
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panic("neither pin 0 or pin 2 works for 8254");
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/* setup the vectors */
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vec[x] = (u_int)vec8254;
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Xintr8254 = (u_int)ivectors[x];
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mask8254 = (1 << x);
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apic_8254_intr = x;
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register_intr(/* irq */ x, /* XXX id */ 0, /* flags */ 0,
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/* XXX */ (inthand2_t *)clkintr, &clk_imask,
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/* unit */ 0);
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INTREN(mask8254);
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INTREN(1 << x);
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#else /* APIC_IO */
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@ -34,7 +34,7 @@
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* SUCH DAMAGE.
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*
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* from: @(#)clock.c 7.2 (Berkeley) 5/12/91
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* $Id: clock.c,v 1.113 1998/02/23 00:11:25 bde Exp $
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* $Id: clock.c,v 1.114 1998/02/28 21:16:13 phk Exp $
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*/
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/*
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@ -87,6 +87,9 @@
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#ifdef SMP
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#define disable_intr() CLOCK_DISABLE_INTR()
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#define enable_intr() CLOCK_ENABLE_INTR()
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/* The interrupt triggered by the 8254 (timer) chip */
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int apic_8254_intr;
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#endif /* SMP */
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/*
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@ -949,15 +952,12 @@ cpu_initclocks()
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else
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panic("neither pin 0 or pin 2 works for 8254");
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/* setup the vectors */
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vec[x] = (u_int)vec8254;
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Xintr8254 = (u_int)ivectors[x];
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mask8254 = (1 << x);
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apic_8254_intr = x;
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register_intr(/* irq */ x, /* XXX id */ 0, /* flags */ 0,
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/* XXX */ (inthand2_t *)clkintr, &clk_imask,
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/* unit */ 0);
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INTREN(mask8254);
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INTREN(1 << x);
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#else /* APIC_IO */
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@ -6,7 +6,7 @@
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* this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp
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* ----------------------------------------------------------------------------
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*
|
||||
* $Id: smp.h,v 1.37 1998/03/03 20:55:23 tegge Exp $
|
||||
* $Id: smp.h,v 1.38 1998/03/03 22:56:26 tegge Exp $
|
||||
*
|
||||
*/
|
||||
|
||||
@ -75,20 +75,13 @@ int try_mpintrlock __P((void));
|
||||
#endif /* RECURSIVE_MPINTRLOCK */
|
||||
|
||||
/* global data in apic_vector.s */
|
||||
extern u_int ivectors[];
|
||||
extern volatile u_int stopped_cpus;
|
||||
extern volatile u_int started_cpus;
|
||||
|
||||
extern unsigned int checkstate_probed_cpus;
|
||||
extern unsigned int checkstate_need_ast;
|
||||
|
||||
/* global data in apic_ipl.s */
|
||||
extern u_int vec[];
|
||||
extern u_int Xintr8254;
|
||||
extern u_int mask8254;
|
||||
|
||||
/* functions in apic_ipl.s */
|
||||
void vec8254 __P((void));
|
||||
void apic_eoi __P((void));
|
||||
u_int io_apic_read __P((int, int));
|
||||
void io_apic_write __P((int, int, u_int));
|
||||
|
||||
Loading…
Reference in New Issue
Block a user