476 lines
12 KiB
ArmAsm
476 lines
12 KiB
ArmAsm
/*-
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* Copyright (c) 1997, by Steve Passe
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: apic_ipl.s,v 1.18 1998/03/03 22:56:28 tegge Exp $
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*/
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.data
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ALIGN_DATA
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/* current INTerrupt level */
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.globl _cil
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_cil: .long 0
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/* current INTerrupt level mask */
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.globl _cml
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_cml: .long 0
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/*
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* Routines used by splz_unpend to build an interrupt frame from a
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* trap frame. The _vec[] routines build the proper frame on the stack,
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* then call one of _Xintr0 thru _XintrNN.
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*
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* used by:
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* i386/isa/apic_ipl.s (this file): splz_unpend JUMPs to HWIs.
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* i386/isa/clock.c: setup _vec[clock] to point at _vec8254.
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*/
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.globl _vec
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_vec:
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.long vec0, vec1, vec2, vec3, vec4, vec5, vec6, vec7
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.long vec8, vec9, vec10, vec11, vec12, vec13, vec14, vec15
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.long vec16, vec17, vec18, vec19, vec20, vec21, vec22, vec23
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/*
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* Note:
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* This is the UP equivilant of _imen.
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* It is OPAQUE, and must NOT be accessed directly.
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* It MUST be accessed along with the IO APIC as a 'critical region'.
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* Accessed by:
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* INTREN()
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* INTRDIS()
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* MAYBE_MASK_IRQ
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* MAYBE_UNMASK_IRQ
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* imen_dump()
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*/
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.align 2 /* MUST be 32bit aligned */
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.globl _apic_imen
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_apic_imen:
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.long HWI_MASK
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/*
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*
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*/
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.text
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SUPERALIGN_TEXT
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/*
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* Interrupt priority mechanism
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* -- soft splXX masks with group mechanism (cpl)
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* -- h/w masks for currently active or unused interrupts (imen)
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* -- ipending = active interrupts currently masked by cpl
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*/
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ENTRY(splz)
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/*
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* The caller has restored cpl and checked that (ipending & ~cpl)
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* is nonzero. We have to repeat the check since if there is an
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* interrupt while we're looking, _doreti processing for the
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* interrupt will handle all the unmasked pending interrupts
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* because we restored early. We're repeating the calculation
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* of (ipending & ~cpl) anyway so that the caller doesn't have
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* to pass it, so this only costs one "jne". "bsfl %ecx,%ecx"
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* is undefined when %ecx is 0 so we can't rely on the secondary
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* btrl tests.
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*/
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AICPL_LOCK
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movl _cpl,%eax
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#ifdef CPL_AND_CML
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orl _cml, %eax /* add cml to cpl */
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#endif
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splz_next:
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/*
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* We don't need any locking here. (ipending & ~cpl) cannot grow
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* while we're looking at it - any interrupt will shrink it to 0.
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*/
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movl %eax,%ecx
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notl %ecx /* set bit = unmasked level */
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andl _ipending,%ecx /* set bit = unmasked pending INT */
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jne splz_unpend
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AICPL_UNLOCK
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ret
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ALIGN_TEXT
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splz_unpend:
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bsfl %ecx,%ecx
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lock
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btrl %ecx, _ipending
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jnc splz_next
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/*
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* HWIs: will JUMP thru *_vec[], see comments below.
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* SWIs: setup CALL of swi_tty, swi_net, _softclock, swi_ast.
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*/
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movl ihandlers(,%ecx,4),%edx
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testl %edx,%edx
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je splz_next /* "can't happen" */
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cmpl $NHWI,%ecx
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jae splz_swi
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pushl %ecx
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AICPL_UNLOCK
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popl %ecx
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/*
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* We would prefer to call the intr handler directly here but that
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* doesn't work for badly behaved handlers that want the interrupt
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* frame. Also, there's a problem determining the unit number.
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* We should change the interface so that the unit number is not
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* determined at config time.
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*
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* The vec[] routines build the proper frame on the stack,
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* then call one of _Xintr0 thru _XintrNN.
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*/
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jmp *_vec(,%ecx,4)
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ALIGN_TEXT
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splz_swi:
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cmpl $SWI_AST,%ecx
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je splz_next /* "can't happen" */
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pushl %eax
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orl imasks(,%ecx,4),%eax
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movl %eax,_cpl
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pushl %edx
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AICPL_UNLOCK
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popl %edx
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call %edx
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AICPL_LOCK
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popl %eax
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movl %eax,_cpl
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jmp splz_next
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/*
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* Fake clock interrupt(s) so that they appear to come from our caller instead
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* of from here, so that system profiling works.
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* XXX do this more generally (for all vectors; look up the C entry point).
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* XXX frame bogusness stops us from just jumping to the C entry point.
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* We have to clear iactive since this is an unpend call, and it will be
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* set from the time of the original INT.
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*/
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/*
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* The 'generic' vector stubs.
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*/
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#define BUILD_VEC(irq_num) \
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ALIGN_TEXT ; \
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__CONCAT(vec,irq_num): ; \
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popl %eax ; \
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pushfl ; \
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pushl $KCSEL ; \
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pushl %eax ; \
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cli ; \
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lock ; /* MP-safe */ \
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andl $~IRQ_BIT(irq_num), iactive ; /* lazy masking */ \
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MEXITCOUNT ; \
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APIC_ITRACE(apic_itrace_splz, irq_num, APIC_ITRACE_SPLZ) ; \
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jmp __CONCAT(_Xintr,irq_num)
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BUILD_VEC(0)
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BUILD_VEC(1)
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BUILD_VEC(2)
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BUILD_VEC(3)
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BUILD_VEC(4)
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BUILD_VEC(5)
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BUILD_VEC(6)
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BUILD_VEC(7)
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BUILD_VEC(8)
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BUILD_VEC(9)
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BUILD_VEC(10)
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BUILD_VEC(11)
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BUILD_VEC(12)
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BUILD_VEC(13)
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BUILD_VEC(14)
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BUILD_VEC(15)
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BUILD_VEC(16) /* 8 additional INTs in IO APIC */
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BUILD_VEC(17)
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BUILD_VEC(18)
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BUILD_VEC(19)
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BUILD_VEC(20)
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BUILD_VEC(21)
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BUILD_VEC(22)
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BUILD_VEC(23)
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/******************************************************************************
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* XXX FIXME: figure out where these belong.
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*/
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/* this nonsense is to verify that masks ALWAYS have 1 and only 1 bit set */
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#define QUALIFY_MASKS_NOT
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#ifdef QUALIFY_MASKS
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#define QUALIFY_MASK \
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btrl %ecx, %eax ; \
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andl %eax, %eax ; \
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jz 1f ; \
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pushl $bad_mask ; \
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call _panic ; \
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1:
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bad_mask: .asciz "bad mask"
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#else
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#define QUALIFY_MASK
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#endif
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/*
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* MULTIPLE_IOAPICSXXX: cannot assume apic #0 in the following function.
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* (soon to be) MP-safe function to clear ONE INT mask bit.
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* The passed arg is a 32bit u_int MASK.
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* It sets the associated bit in _apic_imen.
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* It sets the mask bit of the associated IO APIC register.
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*/
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ENTRY(INTREN)
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pushfl /* save state of EI flag */
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cli /* prevent recursion */
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IMASK_LOCK /* enter critical reg */
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movl 8(%esp), %eax /* mask into %eax */
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bsfl %eax, %ecx /* get pin index */
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btrl %ecx, _apic_imen /* update _apic_imen */
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QUALIFY_MASK
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leal 16(,%ecx,2), %ecx /* calculate register index */
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movl $0, %edx /* XXX FIXME: APIC # */
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movl _ioapic(,%edx,4), %edx /* %edx holds APIC base address */
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movl %ecx, (%edx) /* write the target register index */
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movl 16(%edx), %eax /* read the target register data */
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andl $~IOART_INTMASK, %eax /* clear mask bit */
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movl %eax, 16(%edx) /* write the APIC register data */
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IMASK_UNLOCK /* exit critical reg */
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popfl /* restore old state of EI flag */
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ret
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/*
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* MULTIPLE_IOAPICSXXX: cannot assume apic #0 in the following function.
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* (soon to be) MP-safe function to set ONE INT mask bit.
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* The passed arg is a 32bit u_int MASK.
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* It clears the associated bit in _apic_imen.
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* It clears the mask bit of the associated IO APIC register.
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*/
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ENTRY(INTRDIS)
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pushfl /* save state of EI flag */
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cli /* prevent recursion */
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IMASK_LOCK /* enter critical reg */
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movl 8(%esp), %eax /* mask into %eax */
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bsfl %eax, %ecx /* get pin index */
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btsl %ecx, _apic_imen /* update _apic_imen */
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QUALIFY_MASK
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leal 16(,%ecx,2), %ecx /* calculate register index */
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movl $0, %edx /* XXX FIXME: APIC # */
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movl _ioapic(,%edx,4), %edx /* %edx holds APIC base address */
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movl %ecx, (%edx) /* write the target register index */
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movl 16(%edx), %eax /* read the target register data */
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orl $IOART_INTMASK, %eax /* set mask bit */
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movl %eax, 16(%edx) /* write the APIC register data */
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IMASK_UNLOCK /* exit critical reg */
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popfl /* restore old state of EI flag */
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ret
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/******************************************************************************
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*
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*/
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/*
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* void write_ioapic_mask(int apic, u_int mask);
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*/
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#define _INT_MASK 0x00010000
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#define _PIN_MASK 0x00ffffff
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#define _OLD_ESI 0(%esp)
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#define _OLD_EBX 4(%esp)
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#define _RETADDR 8(%esp)
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#define _APIC 12(%esp)
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#define _MASK 16(%esp)
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.align 2
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write_ioapic_mask:
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pushl %ebx /* scratch */
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pushl %esi /* scratch */
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movl _apic_imen, %ebx
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xorl _MASK, %ebx /* %ebx = _apic_imen ^ mask */
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andl $_PIN_MASK, %ebx /* %ebx = _apic_imen & 0x00ffffff */
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jz all_done /* no change, return */
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movl _APIC, %esi /* APIC # */
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movl _ioapic(,%esi,4), %esi /* %esi holds APIC base address */
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next_loop: /* %ebx = diffs, %esi = APIC base */
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bsfl %ebx, %ecx /* %ecx = index if 1st/next set bit */
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jz all_done
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btrl %ecx, %ebx /* clear this bit in diffs */
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leal 16(,%ecx,2), %edx /* calculate register index */
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movl %edx, (%esi) /* write the target register index */
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movl 16(%esi), %eax /* read the target register data */
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btl %ecx, _MASK /* test for mask or unmask */
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jnc clear /* bit is clear */
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orl $_INT_MASK, %eax /* set mask bit */
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jmp write
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clear: andl $~_INT_MASK, %eax /* clear mask bit */
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write: movl %eax, 16(%esi) /* write the APIC register data */
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jmp next_loop /* try another pass */
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all_done:
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popl %esi
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popl %ebx
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ret
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#undef _OLD_ESI
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#undef _OLD_EBX
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#undef _RETADDR
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#undef _APIC
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#undef _MASK
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#undef _PIN_MASK
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#undef _INT_MASK
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#ifdef oldcode
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_INTREN:
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movl _apic_imen, %eax
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notl %eax /* mask = ~mask */
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andl _apic_imen, %eax /* %eax = _apic_imen & ~mask */
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pushl %eax /* new (future) _apic_imen value */
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pushl $0 /* APIC# arg */
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call write_ioapic_mask /* modify the APIC registers */
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addl $4, %esp /* remove APIC# arg from stack */
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popl _apic_imen /* _apic_imen |= mask */
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ret
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_INTRDIS:
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movl _apic_imen, %eax
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orl 4(%esp), %eax /* %eax = _apic_imen | mask */
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pushl %eax /* new (future) _apic_imen value */
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pushl $0 /* APIC# arg */
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call write_ioapic_mask /* modify the APIC registers */
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addl $4, %esp /* remove APIC# arg from stack */
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popl _apic_imen /* _apic_imen |= mask */
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ret
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#endif /* oldcode */
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#ifdef ready
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/*
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* u_int read_io_apic_mask(int apic);
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*/
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ALIGN_TEXT
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read_io_apic_mask:
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ret
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/*
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* Set INT mask bit for each bit set in 'mask'.
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* Ignore INT mask bit for all others.
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*
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* void set_io_apic_mask(apic, u_int32_t bits);
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*/
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ALIGN_TEXT
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set_io_apic_mask:
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ret
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/*
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* void set_ioapic_maskbit(int apic, int bit);
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*/
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ALIGN_TEXT
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set_ioapic_maskbit:
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ret
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/*
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* Clear INT mask bit for each bit set in 'mask'.
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* Ignore INT mask bit for all others.
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*
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* void clr_io_apic_mask(int apic, u_int32_t bits);
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*/
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ALIGN_TEXT
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clr_io_apic_mask:
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ret
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/*
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* void clr_ioapic_maskbit(int apic, int bit);
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*/
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ALIGN_TEXT
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clr_ioapic_maskbit:
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ret
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#endif /** ready */
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/******************************************************************************
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*
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*/
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/*
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* u_int io_apic_write(int apic, int select);
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*/
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ENTRY(io_apic_read)
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movl 4(%esp), %ecx /* APIC # */
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movl _ioapic(,%ecx,4), %edx /* APIC base register address */
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movl 8(%esp), %eax /* target register index */
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movl %eax, (%edx) /* write the target register index */
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movl 16(%edx), %eax /* read the APIC register data */
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ret /* %eax = register value */
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/*
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* void io_apic_write(int apic, int select, int value);
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*/
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ENTRY(io_apic_write)
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movl 4(%esp), %ecx /* APIC # */
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movl _ioapic(,%ecx,4), %edx /* APIC base register address */
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movl 8(%esp), %eax /* target register index */
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movl %eax, (%edx) /* write the target register index */
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movl 12(%esp), %eax /* target register value */
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movl %eax, 16(%edx) /* write the APIC register data */
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ret /* %eax = void */
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/*
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* Send an EOI to the local APIC.
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*/
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ENTRY(apic_eoi)
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movl $0, _lapic+0xb0
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ret
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