Import DTS files from Linux 5.7
This commit is contained in:
Emmanuel Vadot
parent
937eaf8bbd
commit
5df7ea339a
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/vendor/device-tree/dist/; revision=361846 svn path=/vendor/device-tree/5.7/; revision=361847; tag=vendor/device-tree/5.7
3
Bindings/.gitignore
vendored
3
Bindings/.gitignore
vendored
@ -1,2 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0-only
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*.example.dts
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processed-schema.yaml
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processed-schema*.yaml
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@ -2,7 +2,7 @@
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DT_DOC_CHECKER ?= dt-doc-validate
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DT_EXTRACT_EX ?= dt-extract-example
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DT_MK_SCHEMA ?= dt-mk-schema
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DT_MK_SCHEMA_FLAGS := $(if $(DT_SCHEMA_FILES), -u)
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DT_MK_SCHEMA_USERONLY_FLAG := $(if $(DT_SCHEMA_FILES), -u)
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quiet_cmd_chk_binding = CHKDT $(patsubst $(srctree)/%,%,$<)
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cmd_chk_binding = $(DT_DOC_CHECKER) -u $(srctree)/$(src) $< ; \
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@ -11,26 +11,37 @@ quiet_cmd_chk_binding = CHKDT $(patsubst $(srctree)/%,%,$<)
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$(obj)/%.example.dts: $(src)/%.yaml FORCE
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$(call if_changed,chk_binding)
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DT_TMP_SCHEMA := processed-schema.yaml
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# Use full schemas when checking %.example.dts
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DT_TMP_SCHEMA := $(obj)/processed-schema-examples.yaml
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find_cmd = find $(srctree)/$(src) \( -name '*.yaml' ! \
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-name 'processed-schema*' ! \
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-name '*.example.dt.yaml' \)
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quiet_cmd_mk_schema = SCHEMA $@
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cmd_mk_schema = $(DT_MK_SCHEMA) $(DT_MK_SCHEMA_FLAGS) -o $@ $(real-prereqs)
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cmd_mk_schema = rm -f $@ ; \
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$(if $(DT_MK_SCHEMA_FLAGS), \
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echo $(real-prereqs), \
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$(find_cmd)) | \
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xargs $(DT_MK_SCHEMA) $(DT_MK_SCHEMA_FLAGS) >> $@
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DT_DOCS = $(shell \
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cd $(srctree)/$(src) && \
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find * \( -name '*.yaml' ! \
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-name $(DT_TMP_SCHEMA) ! \
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-name '*.example.dt.yaml' \) \
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)
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DT_DOCS = $(shell $(find_cmd) | sed -e 's|^$(srctree)/||')
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DT_SCHEMA_FILES ?= $(addprefix $(src)/,$(DT_DOCS))
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DT_SCHEMA_FILES ?= $(DT_DOCS)
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ifeq ($(CHECK_DTBS),)
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extra-y += $(patsubst $(src)/%.yaml,%.example.dts, $(DT_SCHEMA_FILES))
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extra-y += $(patsubst $(src)/%.yaml,%.example.dt.yaml, $(DT_SCHEMA_FILES))
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endif
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extra-$(CHECK_DT_BINDING) += $(patsubst $(src)/%.yaml,%.example.dts, $(DT_SCHEMA_FILES))
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extra-$(CHECK_DT_BINDING) += $(patsubst $(src)/%.yaml,%.example.dt.yaml, $(DT_SCHEMA_FILES))
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extra-$(CHECK_DT_BINDING) += processed-schema-examples.yaml
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$(obj)/$(DT_TMP_SCHEMA): $(DT_SCHEMA_FILES) FORCE
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override DTC_FLAGS := \
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-Wno-avoid_unnecessary_addr_size \
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-Wno-graph_child_address
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$(obj)/processed-schema-examples.yaml: $(DT_DOCS) FORCE
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$(call if_changed,mk_schema)
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extra-y += $(DT_TMP_SCHEMA)
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$(obj)/processed-schema.yaml: DT_MK_SCHEMA_FLAGS := $(DT_MK_SCHEMA_USERONLY_FLAG)
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$(obj)/processed-schema.yaml: $(DT_SCHEMA_FILES) FORCE
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$(call if_changed,mk_schema)
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extra-y += processed-schema.yaml
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@ -21,6 +21,8 @@ properties:
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required:
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- compatible
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additionalProperties: false
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examples:
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- |
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clkmgr@ffd04000 {
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@ -43,6 +43,8 @@ required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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ao-secure@140 {
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86
Bindings/arm/arm,integrator.yaml
Normal file
86
Bindings/arm/arm,integrator.yaml
Normal file
@ -0,0 +1,86 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/arm,integrator.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM Integrator Boards Device Tree Bindings
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maintainers:
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- Linus Walleij <linus.walleij@linaro.org>
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description: |+
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These were the first ARM platforms officially supported by ARM Ltd.
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They are ARMv4, ARMv5 and ARMv6-capable using different core tiles,
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so the system is modular and can host a variety of CPU tiles called
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"core tiles" and referred to in the device tree as "core modules".
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properties:
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$nodename:
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const: '/'
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compatible:
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oneOf:
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- description: ARM Integrator Application Platform, this board has a PCI
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host and several PCI slots, as well as a number of slots for logical
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expansion modules, it is referred to as an "ASIC Development
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Motherboard" and is extended with custom FPGA and is intended for
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rapid prototyping. See ARM DUI 0098B. This board can physically come
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pre-packaged in a PC Tower form factor called Integrator/PP1 or a
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special metal fixture called Integrator/PP2, see ARM DUI 0169A.
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items:
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- const: arm,integrator-ap
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- description: ARM Integrator Compact Platform (HBI-0086), this board has
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a compact form factor and mainly consists of the bare minimum
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peripherals to make use of the core module. See ARM DUI 0159B.
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items:
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- const: arm,integrator-cp
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- description: ARM Integrator Standard Development Board (SDB) Platform,
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this board is a PCI-based board conforming to the Microsoft SDB
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(HARP) specification. See ARM DUI 0099A.
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items:
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- const: arm,integrator-sp
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core-module@10000000:
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type: object
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description: the root node in the Integrator platforms must contain
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a core module child node. They are always at physical address
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0x10000000 in all the Integrator variants.
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properties:
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compatible:
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items:
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- const: arm,core-module-integrator
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- const: syscon
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- const: simple-mfd
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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patternProperties:
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"^syscon@[0-9a-f]+$":
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description: All Integrator boards must provide a system controller as a
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node in the root of the device tree.
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type: object
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properties:
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compatible:
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items:
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- enum:
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- arm,integrator-ap-syscon
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- arm,integrator-cp-syscon
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- arm,integrator-sp-syscon
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- const: syscon
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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required:
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- compatible
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- core-module@10000000
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...
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123
Bindings/arm/arm,realview.yaml
Normal file
123
Bindings/arm/arm,realview.yaml
Normal file
@ -0,0 +1,123 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/arm,realview.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM RealView Boards Device Tree Bindings
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maintainers:
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- Linus Walleij <linus.walleij@linaro.org>
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description: |+
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The ARM RealView series of reference designs were built to explore the ARM
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11, Cortex A-8 and Cortex A-9 CPUs. This included new features compared to
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the earlier CPUs such as TrustZone and multicore (MPCore).
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properties:
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$nodename:
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const: '/'
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compatible:
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oneOf:
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- description: ARM RealView Emulation Baseboard (HBI-0140) was created
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as a generic platform to test different FPGA designs, and has
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pluggable CPU modules, see ARM DUI 0303E.
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items:
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- const: arm,realview-eb
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- description: ARM RealView Platform Baseboard for ARM1176JZF-S
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(HBI-0147) was created as a development board to test ARM TrustZone,
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CoreSight and Intelligent Energy Management (IEM) see ARM DUI 0425F.
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items:
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- const: arm,realview-pb1176
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- description: ARM RealView Platform Baseboard for ARM 11 MPCore
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(HBI-0159, HBI-0175 and HBI-0176) was created to showcase
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multiprocessing with ARM11 using MPCore using symmetric
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multiprocessing (SMP). See ARM DUI 0351E.
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items:
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- const: arm,realview-pb11mp
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- description: ARM RealView Platform Baseboard for Cortex-A8 (HBI-0178,
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HBI-0176 and HBI-0175) was the first reference platform for the
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Cortex CPU family, including a Cortex-A8 test chip.
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items:
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- const: arm,realview-pba8
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- description: ARM RealView Platform Baseboard Explore for Cortex-A9
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(HBI-0182 and HBI-0183) was the reference platform for the Cortex-A9
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CPU.
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items:
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- const: arm,realview-pbx
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soc:
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description: All RealView boards must provide a soc node in the root of the
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device tree, representing the System-on-Chip since these test chips are
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rather complex.
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type: object
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properties:
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compatible:
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oneOf:
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- items:
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- const: arm,realview-eb-soc
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- const: simple-bus
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- items:
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- const: arm,realview-pb1176-soc
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- const: simple-bus
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- items:
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- const: arm,realview-pb11mp-soc
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- const: simple-bus
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- items:
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- const: arm,realview-pba8-soc
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- const: simple-bus
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- items:
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- const: arm,realview-pbx-soc
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- const: simple-bus
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patternProperties:
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"^.*syscon@[0-9a-f]+$":
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type: object
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description: All RealView boards must provide a syscon system controller
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node inside the soc node.
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properties:
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compatible:
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oneOf:
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- items:
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- const: arm,realview-eb11mp-revb-syscon
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- const: arm,realview-eb-syscon
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- const: syscon
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- const: simple-mfd
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- items:
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- const: arm,realview-eb11mp-revc-syscon
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- const: arm,realview-eb-syscon
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- const: syscon
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- const: simple-mfd
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- items:
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- const: arm,realview-eb-syscon
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- const: syscon
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- const: simple-mfd
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- items:
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- const: arm,realview-pb1176-syscon
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- const: syscon
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- const: simple-mfd
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- items:
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- const: arm,realview-pb11mp-syscon
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- const: syscon
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- const: simple-mfd
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- items:
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- const: arm,realview-pba8-syscon
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- const: syscon
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- const: simple-mfd
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- items:
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- const: arm,realview-pbx-syscon
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- const: syscon
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- const: simple-mfd
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required:
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- compatible
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- reg
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required:
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- compatible
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|
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required:
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- compatible
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- soc
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...
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71
Bindings/arm/arm,versatile.yaml
Normal file
71
Bindings/arm/arm,versatile.yaml
Normal file
@ -0,0 +1,71 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/arm,versatile.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
|
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title: ARM Versatile Boards Device Tree Bindings
|
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|
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maintainers:
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- Linus Walleij <linus.walleij@linaro.org>
|
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|
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description: |+
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The ARM Versatile boards are two variants of ARM926EJ-S evaluation boards
|
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with various pluggable interface boards, in essence the Versatile PB version
|
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is a superset of the Versatile AB version.
|
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properties:
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$nodename:
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const: '/'
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compatible:
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oneOf:
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- description: The ARM Versatile Application Baseboard (HBI-0118) is an
|
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evaluation board specifically for the ARM926EJ-S. It can be connected
|
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to an IB1 interface board for a touchscreen-type use case or an IB2
|
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for a candybar phone-type use case. See ARM DUI 0225D.
|
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items:
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- const: arm,versatile-ab
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- description: The ARM Versatile Platform Baseboard (HBI-0117) is an
|
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extension of the Versatile Application Baseboard that includes a
|
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PCI host controller. Like the sibling board, it is done specifically
|
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for ARM926EJ-S. See ARM DUI 0224B.
|
||||
items:
|
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- const: arm,versatile-pb
|
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|
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core-module@10000000:
|
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type: object
|
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description: the root node in the Versatile platforms must contain
|
||||
a core module child node. They are always at physical address
|
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0x10000000 in all the Versatile variants.
|
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properties:
|
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compatible:
|
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items:
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- const: arm,core-module-versatile
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- const: syscon
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- const: simple-mfd
|
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reg:
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maxItems: 1
|
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|
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required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
patternProperties:
|
||||
"^syscon@[0-9a-f]+$":
|
||||
type: object
|
||||
description: When fitted with the IB2 Interface Board, the Versatile
|
||||
AB will present an optional system controller node which controls the
|
||||
extra peripherals on the interface board.
|
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properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: arm,versatile-ib2-syscon
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- core-module@10000000
|
||||
|
||||
...
|
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223
Bindings/arm/arm,vexpress-juno.yaml
Normal file
223
Bindings/arm/arm,vexpress-juno.yaml
Normal file
@ -0,0 +1,223 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
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%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/arm,vexpress-juno.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM Versatile Express and Juno Boards Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Sudeep Holla <sudeep.holla@arm.com>
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
|
||||
description: |+
|
||||
ARM's Versatile Express platform were built as reference designs for exploring
|
||||
multicore Cortex-A class systems. The Versatile Express family contains both
|
||||
32 bit (Aarch32) and 64 bit (Aarch64) systems.
|
||||
|
||||
The board consist of a motherboard and one or more daughterboards (tiles). The
|
||||
motherboard provides a set of peripherals. Processor and RAM "live" on the
|
||||
tiles.
|
||||
|
||||
The motherboard and each core tile should be described by a separate Device
|
||||
Tree source file, with the tile's description including the motherboard file
|
||||
using an include directive. As the motherboard can be initialized in one of
|
||||
two different configurations ("memory maps"), care must be taken to include
|
||||
the correct one.
|
||||
|
||||
When a new generation of boards were introduced under the name "Juno", these
|
||||
shared to many common characteristics with the Versatile Express that the
|
||||
"arm,vexpress" compatible was retained in the root node, and these are
|
||||
included in this binding schema as well.
|
||||
|
||||
The root node indicates the CPU SoC on the core tile, and this
|
||||
is a daughterboard to the main motherboard. The name used in the compatible
|
||||
string shall match the name given in the core tile's technical reference
|
||||
manual, followed by "arm,vexpress" as an additional compatible value. If
|
||||
further subvariants are released of the core tile, even more fine-granular
|
||||
compatible strings with up to three compatible strings are used.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: CoreTile Express A9x4 (V2P-CA9) has 4 Cortex A9 CPU cores
|
||||
in MPCore configuration in a test chip on the core tile. See ARM
|
||||
DUI 0448I. This was the first Versatile Express platform.
|
||||
items:
|
||||
- const: arm,vexpress,v2p-ca9
|
||||
- const: arm,vexpress
|
||||
- description: CoreTile Express A5x2 (V2P-CA5s) has 2 Cortex A5 CPU cores
|
||||
in a test chip on the core tile. It is intended to evaluate NEON, FPU
|
||||
and Jazelle support in the Cortex A5 family. See ARM DUI 0541C.
|
||||
items:
|
||||
- const: arm,vexpress,v2p-ca5s
|
||||
- const: arm,vexpress
|
||||
- description: Coretile Express A15x2 (V2P-CA15) has 2 Cortex A15 CPU
|
||||
cores in a MPCore configuration in a test chip on the core tile. See
|
||||
ARM DUI 0604F.
|
||||
items:
|
||||
- const: arm,vexpress,v2p-ca15
|
||||
- const: arm,vexpress
|
||||
- description: CoreTile Express A15x4 (V2P-CA15, HBI-0237A) has 4 Cortex
|
||||
A15 CPU cores in a test chip on the core tile. This is the first test
|
||||
chip called "TC1".
|
||||
items:
|
||||
- const: arm,vexpress,v2p-ca15,tc1
|
||||
- const: arm,vexpress,v2p-ca15
|
||||
- const: arm,vexpress
|
||||
- description: Coretile Express A15x2 A7x3 (V2P-CA15_A7) has 2 Cortex A15
|
||||
CPU cores and 3 Cortex A7 cores in a big.LITTLE MPCore configuration
|
||||
in a test chip on the core tile. See ARM DDI 0503I.
|
||||
items:
|
||||
- const: arm,vexpress,v2p-ca15_a7
|
||||
- const: arm,vexpress
|
||||
- description: LogicTile Express 20MG (V2F-1XV7) has 2 Cortex A53 CPU
|
||||
cores in a test chip on the core tile. See ARM DDI 0498D.
|
||||
items:
|
||||
- const: arm,vexpress,v2f-1xv7,ca53x2
|
||||
- const: arm,vexpress,v2f-1xv7
|
||||
- const: arm,vexpress
|
||||
- description: Arm Versatile Express Juno "r0" (the first Juno board,
|
||||
V2M-Juno) was introduced as a vehicle for evaluating big.LITTLE on
|
||||
AArch64 CPU cores. It has 2 Cortex A57 CPU cores and 4 Cortex A53
|
||||
cores in a big.LITTLE configuration. It also features the MALI T624
|
||||
GPU. See ARM document 100113_0000_07_en.
|
||||
items:
|
||||
- const: arm,juno
|
||||
- const: arm,vexpress
|
||||
- description: Arm Versatile Express Juno r1 Development Platform
|
||||
(V2M-Juno r1) was introduced mainly aimed at development of PCIe
|
||||
based systems. Juno r1 also has support for AXI masters placed on
|
||||
the TLX connectors to join the coherency domain. Otherwise it is the
|
||||
same configuration as Juno r0. See ARM document 100122_0100_06_en.
|
||||
items:
|
||||
- const: arm,juno-r1
|
||||
- const: arm,juno
|
||||
- const: arm,vexpress
|
||||
- description: Arm Versatile Express Juno r2 Development Platform
|
||||
(V2M-Juno r2). It has the same feature set as Juno r0 and r1. See
|
||||
ARM document 100114_0200_04_en.
|
||||
items:
|
||||
- const: arm,juno-r2
|
||||
- const: arm,juno
|
||||
- const: arm,vexpress
|
||||
- description: Arm AEMv8a Versatile Express Real-Time System Model
|
||||
(VE RTSM) is a programmers view of the Versatile Express with Arm
|
||||
v8A hardware. See ARM DUI 0575D.
|
||||
items:
|
||||
- const: arm,rtsm_ve,aemv8a
|
||||
- const: arm,vexpress
|
||||
- description: Arm FVP (Fixed Virtual Platform) base model revision C
|
||||
See ARM Document 100964_1190_00_en.
|
||||
items:
|
||||
- const: arm,fvp-base-revc
|
||||
- const: arm,vexpress
|
||||
- description: Arm Foundation model for Aarch64
|
||||
items:
|
||||
- const: arm,foundation-aarch64
|
||||
- const: arm,vexpress
|
||||
|
||||
arm,hbi:
|
||||
$ref: '/schemas/types.yaml#/definitions/uint32'
|
||||
description: This indicates the ARM HBI (Hardware Board ID), this is
|
||||
ARM's unique board model ID, visible on the PCB's silkscreen.
|
||||
|
||||
arm,vexpress,site:
|
||||
description: As Versatile Express can be configured in number of physically
|
||||
different setups, the device tree should describe platform topology.
|
||||
For this reason the root node and main motherboard node must define this
|
||||
property, describing the physical location of the children nodes.
|
||||
0 means motherboard site, while 1 and 2 are daughterboard sites, and
|
||||
0xf means "sisterboard" which is the site containing the main CPU tile.
|
||||
allOf:
|
||||
- $ref: '/schemas/types.yaml#/definitions/uint32'
|
||||
- minimum: 0
|
||||
maximum: 15
|
||||
|
||||
arm,vexpress,position:
|
||||
description: When daughterboards are stacked on one site, their position
|
||||
in the stack be be described this attribute.
|
||||
allOf:
|
||||
- $ref: '/schemas/types.yaml#/definitions/uint32'
|
||||
- minimum: 0
|
||||
maximum: 3
|
||||
|
||||
arm,vexpress,dcc:
|
||||
description: When describing tiles consisting of more than one DCC, its
|
||||
number can be specified with this attribute.
|
||||
allOf:
|
||||
- $ref: '/schemas/types.yaml#/definitions/uint32'
|
||||
- minimum: 0
|
||||
maximum: 3
|
||||
|
||||
patternProperties:
|
||||
"^bus@[0-9a-f]+$":
|
||||
description: Static Memory Bus (SMB) node, if this exists it describes
|
||||
the connection between the motherboard and any tiles. Sometimes the
|
||||
compatible is placed directly under this node, sometimes it is placed
|
||||
in a subnode named "motherboard". Sometimes the compatible includes
|
||||
"arm,vexpress,v2?-p1" sometimes (on software models) is is just
|
||||
"simple-bus". If the compatible is placed in the "motherboard" node,
|
||||
it is stricter and always has two compatibles.
|
||||
type: object
|
||||
allOf:
|
||||
- $ref: '/schemas/simple-bus.yaml'
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- arm,vexpress,v2m-p1
|
||||
- arm,vexpress,v2p-p1
|
||||
- const: simple-bus
|
||||
- const: simple-bus
|
||||
motherboard:
|
||||
type: object
|
||||
description: The motherboard description provides a single "motherboard"
|
||||
node using 2 address cells corresponding to the Static Memory Bus
|
||||
used between the motherboard and the tile. The first cell defines the
|
||||
Chip Select (CS) line number, the second cell address offset within
|
||||
the CS. All interrupt lines between the motherboard and the tile
|
||||
are active high and are described using single cell.
|
||||
properties:
|
||||
"#address-cells":
|
||||
const: 2
|
||||
"#size-cells":
|
||||
const: 1
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- arm,vexpress,v2m-p1
|
||||
- arm,vexpress,v2p-p1
|
||||
- const: simple-bus
|
||||
arm,v2m-memory-map:
|
||||
description: This describes the memory map type.
|
||||
allOf:
|
||||
- $ref: '/schemas/types.yaml#/definitions/string'
|
||||
- enum:
|
||||
- rs1
|
||||
- rs2
|
||||
required:
|
||||
- compatible
|
||||
required:
|
||||
- compatible
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- arm,vexpress,v2p-ca9
|
||||
- arm,vexpress,v2p-ca5s
|
||||
- arm,vexpress,v2p-ca15
|
||||
- arm,vexpress,v2p-ca15_a7
|
||||
- arm,vexpress,v2f-1xv7,ca53x2
|
||||
then:
|
||||
required:
|
||||
- arm,hbi
|
||||
|
||||
...
|
||||
@ -1,237 +0,0 @@
|
||||
ARM Integrator/AP (Application Platform) and Integrator/CP (Compact Platform)
|
||||
-----------------------------------------------------------------------------
|
||||
ARM's oldest Linux-supported platform with connectors for different core
|
||||
tiles of ARMv4, ARMv5 and ARMv6 type.
|
||||
|
||||
Required properties (in root node):
|
||||
compatible = "arm,integrator-ap"; /* Application Platform */
|
||||
compatible = "arm,integrator-cp"; /* Compact Platform */
|
||||
|
||||
FPGA type interrupt controllers, see the versatile-fpga-irq binding doc.
|
||||
|
||||
Required nodes:
|
||||
|
||||
- core-module: the root node to the Integrator platforms must have
|
||||
a core-module with regs and the compatible string
|
||||
"arm,core-module-integrator"
|
||||
- external-bus-interface: the root node to the Integrator platforms
|
||||
must have an external bus interface with regs and the
|
||||
compatible-string "arm,external-bus-interface"
|
||||
|
||||
Required properties for the core module:
|
||||
- regs: the location and size of the core module registers, one
|
||||
range of 0x200 bytes.
|
||||
|
||||
- syscon: the root node of the Integrator platforms must have a
|
||||
system controller node pointing to the control registers,
|
||||
with the compatible string
|
||||
"arm,integrator-ap-syscon"
|
||||
"arm,integrator-cp-syscon"
|
||||
respectively.
|
||||
|
||||
Required properties for the system controller:
|
||||
- regs: the location and size of the system controller registers,
|
||||
one range of 0x100 bytes.
|
||||
|
||||
Required properties for the AP system controller:
|
||||
- interrupts: the AP syscon node must include the logical module
|
||||
interrupts, stated in order of module instance <module 0>,
|
||||
<module 1>, <module 2> ... for the CP system controller this
|
||||
is not required not of any use.
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "integrator.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ARM Integrator/AP";
|
||||
compatible = "arm,integrator-ap";
|
||||
|
||||
core-module@10000000 {
|
||||
compatible = "arm,core-module-integrator";
|
||||
reg = <0x10000000 0x200>;
|
||||
};
|
||||
|
||||
ebi@12000000 {
|
||||
compatible = "arm,external-bus-interface";
|
||||
reg = <0x12000000 0x100>;
|
||||
};
|
||||
|
||||
syscon {
|
||||
compatible = "arm,integrator-ap-syscon";
|
||||
reg = <0x11000000 0x100>;
|
||||
interrupt-parent = <&pic>;
|
||||
/* These are the logic module IRQs */
|
||||
interrupts = <9>, <10>, <11>, <12>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
ARM Versatile Application and Platform Baseboards
|
||||
-------------------------------------------------
|
||||
ARM's development hardware platform with connectors for customizable
|
||||
core tiles. The hardware configuration of the Versatile boards is
|
||||
highly customizable.
|
||||
|
||||
Required properties (in root node):
|
||||
compatible = "arm,versatile-ab"; /* Application baseboard */
|
||||
compatible = "arm,versatile-pb"; /* Platform baseboard */
|
||||
|
||||
Interrupt controllers:
|
||||
- VIC required properties:
|
||||
compatible = "arm,versatile-vic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
- SIC required properties:
|
||||
compatible = "arm,versatile-sic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
Required nodes:
|
||||
|
||||
- core-module: the root node to the Versatile platforms must have
|
||||
a core-module with regs and the compatible strings
|
||||
"arm,core-module-versatile", "syscon"
|
||||
|
||||
Optional nodes:
|
||||
|
||||
- arm,versatile-ib2-syscon : if the Versatile has an IB2 interface
|
||||
board mounted, this has a separate system controller that is
|
||||
defined in this node.
|
||||
Required properties:
|
||||
compatible = "arm,versatile-ib2-syscon", "syscon"
|
||||
|
||||
ARM RealView Boards
|
||||
-------------------
|
||||
The RealView boards cover tailored evaluation boards that are used to explore
|
||||
the ARM11 and Cortex A-8 and Cortex A-9 processors.
|
||||
|
||||
Required properties (in root node):
|
||||
/* RealView Emulation Baseboard */
|
||||
compatible = "arm,realview-eb";
|
||||
/* RealView Platform Baseboard for ARM1176JZF-S */
|
||||
compatible = "arm,realview-pb1176";
|
||||
/* RealView Platform Baseboard for ARM11 MPCore */
|
||||
compatible = "arm,realview-pb11mp";
|
||||
/* RealView Platform Baseboard for Cortex A-8 */
|
||||
compatible = "arm,realview-pba8";
|
||||
/* RealView Platform Baseboard Explore for Cortex A-9 */
|
||||
compatible = "arm,realview-pbx";
|
||||
|
||||
Required nodes:
|
||||
|
||||
- soc: some node of the RealView platforms must be the SoC
|
||||
node that contain the SoC-specific devices, with the compatible
|
||||
string set to one of these tuples:
|
||||
"arm,realview-eb-soc", "simple-bus"
|
||||
"arm,realview-pb1176-soc", "simple-bus"
|
||||
"arm,realview-pb11mp-soc", "simple-bus"
|
||||
"arm,realview-pba8-soc", "simple-bus"
|
||||
"arm,realview-pbx-soc", "simple-bus"
|
||||
|
||||
- syscon: some subnode of the RealView SoC node must be a
|
||||
system controller node pointing to the control registers,
|
||||
with the compatible string set to one of these:
|
||||
"arm,realview-eb11mp-revb-syscon", "arm,realview-eb-syscon", "syscon"
|
||||
"arm,realview-eb11mp-revc-syscon", "arm,realview-eb-syscon", "syscon"
|
||||
"arm,realview-eb-syscon", "syscon"
|
||||
"arm,realview-pb1176-syscon", "syscon"
|
||||
"arm,realview-pb11mp-syscon", "syscon"
|
||||
"arm,realview-pba8-syscon", "syscon"
|
||||
"arm,realview-pbx-syscon", "syscon"
|
||||
|
||||
Required properties for the system controller:
|
||||
- regs: the location and size of the system controller registers,
|
||||
one range of 0x1000 bytes.
|
||||
|
||||
Example:
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
model = "ARM RealView PB1176 with device tree";
|
||||
compatible = "arm,realview-pb1176";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "arm,realview-pb1176-soc", "simple-bus";
|
||||
ranges;
|
||||
|
||||
syscon: syscon@10000000 {
|
||||
compatible = "arm,realview-syscon", "syscon";
|
||||
reg = <0x10000000 0x1000>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
ARM Versatile Express Boards
|
||||
-----------------------------
|
||||
For details on the device tree bindings for ARM Versatile Express boards
|
||||
please consult the vexpress.txt file in the same directory as this file.
|
||||
|
||||
ARM Juno Boards
|
||||
----------------
|
||||
The Juno boards are targeting development for AArch64 systems. The first
|
||||
iteration, Juno r0, is a vehicle for evaluating big.LITTLE on AArch64,
|
||||
with the second iteration, Juno r1, mainly aimed at development of PCIe
|
||||
based systems. Juno r1 also has support for AXI masters placed on the TLX
|
||||
connectors to join the coherency domain.
|
||||
|
||||
Juno boards are described in a similar way to ARM Versatile Express boards,
|
||||
with the motherboard part of the hardware being described in a separate file
|
||||
to highlight the fact that is part of the support infrastructure for the SoC.
|
||||
Juno device tree bindings also share the Versatile Express bindings as
|
||||
described under the RS1 memory mapping.
|
||||
|
||||
Required properties (in root node):
|
||||
compatible = "arm,juno"; /* For Juno r0 board */
|
||||
compatible = "arm,juno-r1"; /* For Juno r1 board */
|
||||
compatible = "arm,juno-r2"; /* For Juno r2 board */
|
||||
|
||||
Required nodes:
|
||||
The description for the board must include:
|
||||
- a "psci" node describing the boot method used for the secondary CPUs.
|
||||
A detailed description of the bindings used for "psci" nodes is present
|
||||
in the psci.yaml file.
|
||||
- a "cpus" node describing the available cores and their associated
|
||||
"enable-method"s. For more details see cpus.yaml file.
|
||||
|
||||
Example:
|
||||
|
||||
/dts-v1/;
|
||||
/ {
|
||||
model = "ARM Juno development board (r0)";
|
||||
compatible = "arm,juno", "arm,vexpress";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
A57_0: cpu@0 {
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x0>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
.....
|
||||
|
||||
A53_0: cpu@100 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0 0x100>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
.....
|
||||
};
|
||||
|
||||
};
|
||||
@ -1,36 +0,0 @@
|
||||
Broadcom Kona Family CPU Enable Method
|
||||
--------------------------------------
|
||||
This binding defines the enable method used for starting secondary
|
||||
CPUs in the following Broadcom SoCs:
|
||||
BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664
|
||||
|
||||
The enable method is specified by defining the following required
|
||||
properties in the "cpu" device tree node:
|
||||
- enable-method = "brcm,bcm11351-cpu-method";
|
||||
- secondary-boot-reg = <...>;
|
||||
|
||||
The secondary-boot-reg property is a u32 value that specifies the
|
||||
physical address of the register used to request the ROM holding pen
|
||||
code release a secondary CPU. The value written to the register is
|
||||
formed by encoding the target CPU id into the low bits of the
|
||||
physical start address it should jump to.
|
||||
|
||||
Example:
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <1>;
|
||||
enable-method = "brcm,bcm11351-cpu-method";
|
||||
secondary-boot-reg = <0x3500417c>;
|
||||
};
|
||||
};
|
||||
@ -1,10 +0,0 @@
|
||||
Broadcom BCM11351 device tree bindings
|
||||
-------------------------------------------
|
||||
|
||||
Boards with the bcm281xx SoC family (which includes bcm11130, bcm11140,
|
||||
bcm11351, bcm28145, bcm28155 SoCs) shall have the following properties:
|
||||
|
||||
Required root node property:
|
||||
|
||||
compatible = "brcm,bcm11351";
|
||||
DEPRECATED: compatible = "bcm,bcm11351";
|
||||
21
Bindings/arm/bcm/brcm,bcm11351.yaml
Normal file
21
Bindings/arm/bcm/brcm,bcm11351.yaml
Normal file
@ -0,0 +1,21 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm11351.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom BCM11351 device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Florian Fainelli <f.fainelli@gmail.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- brcm,bcm28155-ap
|
||||
- const: brcm,bcm11351
|
||||
|
||||
...
|
||||
@ -1,15 +0,0 @@
|
||||
Broadcom BCM21664 device tree bindings
|
||||
--------------------------------------
|
||||
|
||||
This document describes the device tree bindings for boards with the BCM21664
|
||||
SoC.
|
||||
|
||||
Required root node property:
|
||||
- compatible: brcm,bcm21664
|
||||
|
||||
Example:
|
||||
/ {
|
||||
model = "BCM21664 SoC";
|
||||
compatible = "brcm,bcm21664";
|
||||
[...]
|
||||
}
|
||||
21
Bindings/arm/bcm/brcm,bcm21664.yaml
Normal file
21
Bindings/arm/bcm/brcm,bcm21664.yaml
Normal file
@ -0,0 +1,21 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm21664.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom BCM21664 device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Florian Fainelli <f.fainelli@gmail.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- brcm,bcm21664-garnet
|
||||
- const: brcm,bcm21664
|
||||
|
||||
...
|
||||
@ -1,36 +0,0 @@
|
||||
Broadcom Kona Family CPU Enable Method
|
||||
--------------------------------------
|
||||
This binding defines the enable method used for starting secondary
|
||||
CPUs in the following Broadcom SoCs:
|
||||
BCM23550
|
||||
|
||||
The enable method is specified by defining the following required
|
||||
properties in the "cpu" device tree node:
|
||||
- enable-method = "brcm,bcm23550";
|
||||
- secondary-boot-reg = <...>;
|
||||
|
||||
The secondary-boot-reg property is a u32 value that specifies the
|
||||
physical address of the register used to request the ROM holding pen
|
||||
code release a secondary CPU. The value written to the register is
|
||||
formed by encoding the target CPU id into the low bits of the
|
||||
physical start address it should jump to.
|
||||
|
||||
Example:
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <1>;
|
||||
enable-method = "brcm,bcm23550";
|
||||
secondary-boot-reg = <0x3500417c>;
|
||||
};
|
||||
};
|
||||
@ -1,15 +0,0 @@
|
||||
Broadcom BCM23550 device tree bindings
|
||||
--------------------------------------
|
||||
|
||||
This document describes the device tree bindings for boards with the BCM23550
|
||||
SoC.
|
||||
|
||||
Required root node property:
|
||||
- compatible: brcm,bcm23550
|
||||
|
||||
Example:
|
||||
/ {
|
||||
model = "BCM23550 SoC";
|
||||
compatible = "brcm,bcm23550";
|
||||
[...]
|
||||
}
|
||||
21
Bindings/arm/bcm/brcm,bcm23550.yaml
Normal file
21
Bindings/arm/bcm/brcm,bcm23550.yaml
Normal file
@ -0,0 +1,21 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm23550.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom BCM23550 device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Florian Fainelli <f.fainelli@gmail.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- brcm,bcm23550-sparrow
|
||||
- const: brcm,bcm23550
|
||||
|
||||
...
|
||||
@ -1,15 +0,0 @@
|
||||
Broadcom BCM4708 device tree bindings
|
||||
-------------------------------------------
|
||||
|
||||
Boards with the BCM4708 SoC shall have the following properties:
|
||||
|
||||
Required root node property:
|
||||
|
||||
bcm4708
|
||||
compatible = "brcm,bcm4708";
|
||||
|
||||
bcm4709
|
||||
compatible = "brcm,bcm4709";
|
||||
|
||||
bcm53012
|
||||
compatible = "brcm,bcm53012";
|
||||
88
Bindings/arm/bcm/brcm,bcm4708.yaml
Normal file
88
Bindings/arm/bcm/brcm,bcm4708.yaml
Normal file
@ -0,0 +1,88 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm4708.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom BCM4708 device tree bindings
|
||||
|
||||
description:
|
||||
Broadcom BCM4708/47081/4709/47094/53012 Wi-Fi/network SoCs based
|
||||
on the iProc architecture (Northstar).
|
||||
|
||||
maintainers:
|
||||
- Florian Fainelli <f.fainelli@gmail.com>
|
||||
- Hauke Mehrtens <hauke@hauke-m.de>
|
||||
- Rafal Milecki <zajec5@gmail.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: BCM4708 based boards
|
||||
items:
|
||||
- enum:
|
||||
- asus,rt-ac56u
|
||||
- asus,rt-ac68u
|
||||
- buffalo,wzr-1750dhp
|
||||
- linksys,ea6300-v1
|
||||
- linksys,ea6500-v2
|
||||
- luxul,xap-1510v1
|
||||
- luxul,xwc-1000
|
||||
- netgear,r6250v1
|
||||
- netgear,r6300v2
|
||||
- smartrg,sr400ac
|
||||
- brcm,bcm94708
|
||||
- const: brcm,bcm4708
|
||||
|
||||
- description: BCM47081 based boards
|
||||
items:
|
||||
- enum:
|
||||
- asus,rt-n18u
|
||||
- buffalo,wzr-600dhp2
|
||||
- buffalo,wzr-900dhp
|
||||
- luxul,xap-1410v1
|
||||
- luxul,xwr-1200v1
|
||||
- tplink,archer-c5-v2
|
||||
- const: brcm,bcm47081
|
||||
- const: brcm,bcm4708
|
||||
|
||||
- description: BCM4709 based boards
|
||||
items:
|
||||
- enum:
|
||||
- asus,rt-ac87u
|
||||
- buffalo,wxr-1900dhp
|
||||
- linksys,ea9200
|
||||
- netgear,r7000
|
||||
- netgear,r8000
|
||||
- tplink,archer-c9-v1
|
||||
- brcm,bcm94709
|
||||
- const: brcm,bcm4709
|
||||
- const: brcm,bcm4708
|
||||
|
||||
- description: BCM47094 based boards
|
||||
items:
|
||||
- enum:
|
||||
- dlink,dir-885l
|
||||
- linksys,panamera
|
||||
- luxul,abr-4500-v1
|
||||
- luxul,xap-1610-v1
|
||||
- luxul,xbr-4500-v1
|
||||
- luxul,xwc-2000-v1
|
||||
- luxul,xwr-3100v1
|
||||
- luxul,xwr-3150-v1
|
||||
- netgear,r8500
|
||||
- phicomm,k3
|
||||
- const: brcm,bcm47094
|
||||
- const: brcm,bcm4708
|
||||
|
||||
- description: BCM53012 based boards
|
||||
items:
|
||||
- enum:
|
||||
- brcm,bcm953012er
|
||||
- brcm,bcm953012hr
|
||||
- brcm,bcm953012k
|
||||
- const: brcm,brcm53012
|
||||
- const: brcm,bcm4708
|
||||
...
|
||||
@ -1,31 +0,0 @@
|
||||
Broadcom Cygnus device tree bindings
|
||||
------------------------------------
|
||||
|
||||
|
||||
Boards with Cygnus SoCs shall have the following properties:
|
||||
|
||||
Required root node property:
|
||||
|
||||
BCM11300
|
||||
compatible = "brcm,bcm11300", "brcm,cygnus";
|
||||
|
||||
BCM11320
|
||||
compatible = "brcm,bcm11320", "brcm,cygnus";
|
||||
|
||||
BCM11350
|
||||
compatible = "brcm,bcm11350", "brcm,cygnus";
|
||||
|
||||
BCM11360
|
||||
compatible = "brcm,bcm11360", "brcm,cygnus";
|
||||
|
||||
BCM58300
|
||||
compatible = "brcm,bcm58300", "brcm,cygnus";
|
||||
|
||||
BCM58302
|
||||
compatible = "brcm,bcm58302", "brcm,cygnus";
|
||||
|
||||
BCM58303
|
||||
compatible = "brcm,bcm58303", "brcm,cygnus";
|
||||
|
||||
BCM58305
|
||||
compatible = "brcm,bcm58305", "brcm,cygnus";
|
||||
29
Bindings/arm/bcm/brcm,cygnus.yaml
Normal file
29
Bindings/arm/bcm/brcm,cygnus.yaml
Normal file
@ -0,0 +1,29 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/bcm/brcm,cygnus.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom Cygnus device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Ray Jui <rjui@broadcom.com>
|
||||
- Scott Branden <sbranden@broadcom.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- brcm,bcm11300
|
||||
- brcm,bcm11320
|
||||
- brcm,bcm11350
|
||||
- brcm,bcm11360
|
||||
- brcm,bcm58300
|
||||
- brcm,bcm58302
|
||||
- brcm,bcm58303
|
||||
- brcm,bcm58305
|
||||
- const: brcm,cygnus
|
||||
|
||||
...
|
||||
@ -1,14 +0,0 @@
|
||||
Broadcom Hurricane 2 device tree bindings
|
||||
---------------------------------------
|
||||
|
||||
Broadcom Hurricane 2 family of SoCs are used for switching control. These SoCs
|
||||
are based on Broadcom's iProc SoC architecture and feature a single core Cortex
|
||||
A9 ARM CPUs, DDR2/DDR3 memory, PCIe GEN-2, USB 2.0 and USB 3.0, serial and NAND
|
||||
flash and a PCIe attached integrated switching engine.
|
||||
|
||||
Boards with Hurricane SoCs shall have the following properties:
|
||||
|
||||
Required root node property:
|
||||
|
||||
BCM53342
|
||||
compatible = "brcm,bcm53342", "brcm,hr2";
|
||||
28
Bindings/arm/bcm/brcm,hr2.yaml
Normal file
28
Bindings/arm/bcm/brcm,hr2.yaml
Normal file
@ -0,0 +1,28 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/bcm/brcm,hr2.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom Hurricane 2 device tree bindings
|
||||
|
||||
description:
|
||||
Broadcom Hurricane 2 family of SoCs are used for switching control. These SoCs
|
||||
are based on Broadcom's iProc SoC architecture and feature a single core Cortex
|
||||
A9 ARM CPUs, DDR2/DDR3 memory, PCIe GEN-2, USB 2.0 and USB 3.0, serial and NAND
|
||||
flash and a PCIe attached integrated switching engine.
|
||||
|
||||
maintainers:
|
||||
- Florian Fainelli <f.fainelli@gmail.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- ubnt,unifi-switch8
|
||||
- const: brcm,bcm53342
|
||||
- const: brcm,hr2
|
||||
|
||||
...
|
||||
@ -1,9 +0,0 @@
|
||||
Broadcom North Star 2 (NS2) device tree bindings
|
||||
------------------------------------------------
|
||||
|
||||
Boards with NS2 shall have the following properties:
|
||||
|
||||
Required root node property:
|
||||
|
||||
NS2 SVK board
|
||||
compatible = "brcm,ns2-svk", "brcm,ns2";
|
||||
23
Bindings/arm/bcm/brcm,ns2.yaml
Normal file
23
Bindings/arm/bcm/brcm,ns2.yaml
Normal file
@ -0,0 +1,23 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/bcm/brcm,ns2.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom North Star 2 (NS2) device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Ray Jui <rjui@broadcom.com>
|
||||
- Scott Branden <sbranden@broadcom.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- brcm,ns2-svk
|
||||
- brcm,ns2-xmc
|
||||
- const: brcm,ns2
|
||||
|
||||
...
|
||||
@ -1,39 +0,0 @@
|
||||
Broadcom Northstar Plus SoC CPU Enable Method
|
||||
---------------------------------------------
|
||||
This binding defines the enable method used for starting secondary
|
||||
CPU in the following Broadcom SoCs:
|
||||
BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
|
||||
|
||||
The enable method is specified by defining the following required
|
||||
properties in the corresponding secondary "cpu" device tree node:
|
||||
- enable-method = "brcm,bcm-nsp-smp";
|
||||
- secondary-boot-reg = <...>;
|
||||
|
||||
The secondary-boot-reg property is a u32 value that specifies the
|
||||
physical address of the register which should hold the common
|
||||
entry point for a secondary CPU. This entry is cpu node specific
|
||||
and should be added per cpu. E.g., in case of NSP (BCM58625) which
|
||||
is a dual core CPU SoC, this entry should be added to cpu1 node.
|
||||
|
||||
|
||||
Example:
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
next-level-cache = <&L2>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
next-level-cache = <&L2>;
|
||||
enable-method = "brcm,bcm-nsp-smp";
|
||||
secondary-boot-reg = <0xffff042c>;
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
@ -1,34 +0,0 @@
|
||||
Broadcom Northstar Plus device tree bindings
|
||||
--------------------------------------------
|
||||
|
||||
Broadcom Northstar Plus family of SoCs are used for switching control
|
||||
and management applications as well as residential router/gateway
|
||||
applications. The SoC features dual core Cortex A9 ARM CPUs, integrating
|
||||
several peripheral interfaces including multiple Gigabit Ethernet PHYs,
|
||||
DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and NAND flash,
|
||||
SATA and several other IO controllers.
|
||||
|
||||
Boards with Northstar Plus SoCs shall have the following properties:
|
||||
|
||||
Required root node property:
|
||||
|
||||
BCM58522
|
||||
compatible = "brcm,bcm58522", "brcm,nsp";
|
||||
|
||||
BCM58525
|
||||
compatible = "brcm,bcm58525", "brcm,nsp";
|
||||
|
||||
BCM58535
|
||||
compatible = "brcm,bcm58535", "brcm,nsp";
|
||||
|
||||
BCM58622
|
||||
compatible = "brcm,bcm58622", "brcm,nsp";
|
||||
|
||||
BCM58623
|
||||
compatible = "brcm,bcm58623", "brcm,nsp";
|
||||
|
||||
BCM58625
|
||||
compatible = "brcm,bcm58625", "brcm,nsp";
|
||||
|
||||
BCM88312
|
||||
compatible = "brcm,bcm88312", "brcm,nsp";
|
||||
36
Bindings/arm/bcm/brcm,nsp.yaml
Normal file
36
Bindings/arm/bcm/brcm,nsp.yaml
Normal file
@ -0,0 +1,36 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/bcm/brcm,nsp.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom Northstar Plus device tree bindings
|
||||
|
||||
description:
|
||||
Broadcom Northstar Plus family of SoCs are used for switching control
|
||||
and management applications as well as residential router/gateway
|
||||
applications. The SoC features dual core Cortex A9 ARM CPUs, integrating
|
||||
several peripheral interfaces including multiple Gigabit Ethernet PHYs,
|
||||
DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and NAND flash,
|
||||
SATA and several other IO controllers.
|
||||
|
||||
maintainers:
|
||||
- Ray Jui <rjui@broadcom.com>
|
||||
- Scott Branden <sbranden@broadcom.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- brcm,bcm58522
|
||||
- brcm,bcm58525
|
||||
- brcm,bcm58535
|
||||
- brcm,bcm58622
|
||||
- brcm,bcm58623
|
||||
- brcm,bcm58625
|
||||
- brcm,bcm88312
|
||||
- const: brcm,nsp
|
||||
|
||||
...
|
||||
@ -1,12 +0,0 @@
|
||||
Broadcom Stingray device tree bindings
|
||||
------------------------------------------------
|
||||
|
||||
Boards with Stingray shall have the following properties:
|
||||
|
||||
Required root node property:
|
||||
|
||||
Stingray Combo SVK board
|
||||
compatible = "brcm,bcm958742k", "brcm,stingray";
|
||||
|
||||
Stingray SST100 board
|
||||
compatible = "brcm,bcm958742t", "brcm,stingray";
|
||||
24
Bindings/arm/bcm/brcm,stingray.yaml
Normal file
24
Bindings/arm/bcm/brcm,stingray.yaml
Normal file
@ -0,0 +1,24 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/bcm/brcm,stingray.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom Stingray device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Ray Jui <rjui@broadcom.com>
|
||||
- Scott Branden <sbranden@broadcom.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- brcm,bcm958742k
|
||||
- brcm,bcm958742t
|
||||
- brcm,bcm958802a802x
|
||||
- const: brcm,stingray
|
||||
|
||||
...
|
||||
@ -1,10 +0,0 @@
|
||||
Broadcom Vulcan device tree bindings
|
||||
------------------------------------
|
||||
|
||||
Boards with Broadcom Vulcan shall have the following root property:
|
||||
|
||||
Broadcom Vulcan Evaluation Board:
|
||||
compatible = "brcm,vulcan-eval", "brcm,vulcan-soc";
|
||||
|
||||
Generic Vulcan board:
|
||||
compatible = "brcm,vulcan-soc";
|
||||
22
Bindings/arm/bcm/brcm,vulcan-soc.yaml
Normal file
22
Bindings/arm/bcm/brcm,vulcan-soc.yaml
Normal file
@ -0,0 +1,22 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/bcm/brcm,vulcan-soc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom Vulcan device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Robert Richter <rrichter@marvell.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- brcm,vulcan-eval
|
||||
- cavium,thunderx2-cn9900
|
||||
- const: brcm,vulcan-soc
|
||||
|
||||
...
|
||||
336
Bindings/arm/coresight-cti.yaml
Normal file
336
Bindings/arm/coresight-cti.yaml
Normal file
@ -0,0 +1,336 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
# Copyright 2019 Linaro Ltd.
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/coresight-cti.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM Coresight Cross Trigger Interface (CTI) device.
|
||||
|
||||
description: |
|
||||
The CoreSight Embedded Cross Trigger (ECT) consists of CTI devices connected
|
||||
to one or more CoreSight components and/or a CPU, with CTIs interconnected in
|
||||
a star topology via the Cross Trigger Matrix (CTM), which is not programmable.
|
||||
The ECT components are not part of the trace generation data path and are thus
|
||||
not part of the CoreSight graph described in the general CoreSight bindings
|
||||
file coresight.txt.
|
||||
|
||||
The CTI component properties define the connections between the individual
|
||||
CTI and the components it is directly connected to, consisting of input and
|
||||
output hardware trigger signals. CTIs can have a maximum number of input and
|
||||
output hardware trigger signals (8 each for v1 CTI, 32 each for v2 CTI). The
|
||||
number is defined at design time, the maximum of each defined in the DEVID
|
||||
register.
|
||||
|
||||
CTIs are interconnected in a star topology via the CTM, using a number of
|
||||
programmable channels, usually 4, but again implementation defined and
|
||||
described in the DEVID register. The star topology is not required to be
|
||||
described in the bindings as the actual connections are software
|
||||
programmable.
|
||||
|
||||
In general the connections between CTI and components via the trigger signals
|
||||
are implementation defined, except when the CTI is connected to an ARM v8
|
||||
architecture core and optional ETM.
|
||||
|
||||
In this case the ARM v8 architecture defines the required signal connections
|
||||
between CTI and the CPU core and ETM if present. In the case of a v8
|
||||
architecturally connected CTI an additional compatible string is used to
|
||||
indicate this feature (arm,coresight-cti-v8-arch).
|
||||
|
||||
When CTI trigger connection information is unavailable then a minimal driver
|
||||
binding can be declared with no explicit trigger signals. This will result
|
||||
the driver detecting the maximum available triggers and channels from the
|
||||
DEVID register and make them all available for use as a single default
|
||||
connection. Any user / client application will require additional information
|
||||
on the connections between the CTI and other components for correct operation.
|
||||
This information might be found by enabling the Integration Test registers in
|
||||
the driver (set CONFIG_CORESIGHT_CTI_INTEGRATION_TEST in Kernel
|
||||
configuration). These registers may be used to explore the trigger connections
|
||||
between CTI and other CoreSight components.
|
||||
|
||||
Certain triggers between CoreSight devices and the CTI have specific types
|
||||
and usages. These can be defined along with the signal indexes with the
|
||||
constants defined in <dt-bindings/arm/coresight-cti-dt.h>
|
||||
|
||||
For example a CTI connected to a core will usually have a DBGREQ signal. This
|
||||
is defined in the binding as type PE_EDBGREQ. These types will appear in an
|
||||
optional array alongside the signal indexes. Omitting types will default all
|
||||
signals to GEN_IO.
|
||||
|
||||
Note that some hardware trigger signals can be connected to non-CoreSight
|
||||
components (e.g. UART etc) depending on hardware implementation.
|
||||
|
||||
maintainers:
|
||||
- Mike Leach <mike.leach@linaro.org>
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/arm/primecell.yaml#
|
||||
|
||||
# Need a custom select here or 'arm,primecell' will match on lots of nodes
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- arm,coresight-cti
|
||||
required:
|
||||
- compatible
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^cti(@[0-9a-f]+)$"
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: arm,coresight-cti
|
||||
- const: arm,primecell
|
||||
- items:
|
||||
- const: arm,coresight-cti-v8-arch
|
||||
- const: arm,coresight-cti
|
||||
- const: arm,primecell
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
cpu:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Handle to cpu this device is associated with. This must appear in the
|
||||
base cti node if compatible string arm,coresight-cti-v8-arch is used,
|
||||
or may appear in a trig-conns child node when appropriate.
|
||||
|
||||
arm,cti-ctm-id:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Defines the CTM this CTI is connected to, in large systems with multiple
|
||||
separate CTI/CTM nets. Typically multi-socket systems where the CTM is
|
||||
propagated between sockets.
|
||||
|
||||
arm,cs-dev-assoc:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
defines a phandle reference to an associated CoreSight trace device.
|
||||
When the associated trace device is enabled, then the respective CTI
|
||||
will be enabled. Use in a trig-conns node, or in CTI base node when
|
||||
compatible string arm,coresight-cti-v8-arch used. If the associated
|
||||
device has not been registered then the node name will be stored as
|
||||
the connection name for later resolution. If the associated device is
|
||||
not a CoreSight device or not registered then the node name will remain
|
||||
the connection name and automatic enabling will not occur.
|
||||
|
||||
# size cells and address cells required if trig-conns node present.
|
||||
"#size-cells":
|
||||
const: 0
|
||||
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
patternProperties:
|
||||
'^trig-conns@([0-9]+)$':
|
||||
type: object
|
||||
description:
|
||||
A trigger connections child node which describes the trigger signals
|
||||
between this CTI and another hardware device. This device may be a CPU,
|
||||
CoreSight device, any other hardware device or simple external IO lines.
|
||||
The connection may have both input and output triggers, or only one or the
|
||||
other.
|
||||
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
arm,trig-in-sigs:
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 1
|
||||
maxItems: 32
|
||||
description:
|
||||
List of CTI trigger in signal numbers in use by a trig-conns node.
|
||||
|
||||
arm,trig-in-types:
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 1
|
||||
maxItems: 32
|
||||
description:
|
||||
List of constants representing the types for the CTI trigger in
|
||||
signals. Types in this array match to the corresponding signal in the
|
||||
arm,trig-in-sigs array. If the -types array is smaller, or omitted
|
||||
completely, then the types will default to GEN_IO.
|
||||
|
||||
arm,trig-out-sigs:
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 1
|
||||
maxItems: 32
|
||||
description:
|
||||
List of CTI trigger out signal numbers in use by a trig-conns node.
|
||||
|
||||
arm,trig-out-types:
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 1
|
||||
maxItems: 32
|
||||
description:
|
||||
List of constants representing the types for the CTI trigger out
|
||||
signals. Types in this array match to the corresponding signal
|
||||
in the arm,trig-out-sigs array. If the "-types" array is smaller,
|
||||
or omitted completely, then the types will default to GEN_IO.
|
||||
|
||||
arm,trig-filters:
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 1
|
||||
maxItems: 32
|
||||
description:
|
||||
List of CTI trigger out signals that will be blocked from becoming
|
||||
active, unless filtering is disabled on the driver.
|
||||
|
||||
arm,trig-conn-name:
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/string
|
||||
description:
|
||||
Defines a connection name that will be displayed, if the cpu or
|
||||
arm,cs-dev-assoc properties are not being used in this connection.
|
||||
Principle use for CTI that are connected to non-CoreSight devices, or
|
||||
external IO.
|
||||
|
||||
anyOf:
|
||||
- required:
|
||||
- arm,trig-in-sigs
|
||||
- required:
|
||||
- arm,trig-out-sigs
|
||||
oneOf:
|
||||
- required:
|
||||
- arm,trig-conn-name
|
||||
- required:
|
||||
- cpu
|
||||
- required:
|
||||
- arm,cs-dev-assoc
|
||||
required:
|
||||
- reg
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: arm,coresight-cti-v8-arch
|
||||
|
||||
then:
|
||||
required:
|
||||
- cpu
|
||||
|
||||
examples:
|
||||
# minimum CTI definition. DEVID register used to set number of triggers.
|
||||
- |
|
||||
cti@20020000 {
|
||||
compatible = "arm,coresight-cti", "arm,primecell";
|
||||
reg = <0x20020000 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
# v8 architecturally defined CTI - CPU + ETM connections generated by the
|
||||
# driver according to the v8 architecture specification.
|
||||
- |
|
||||
cti@859000 {
|
||||
compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
|
||||
"arm,primecell";
|
||||
reg = <0x859000 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
cpu = <&CPU1>;
|
||||
arm,cs-dev-assoc = <&etm1>;
|
||||
};
|
||||
# Implementation defined CTI - CPU + ETM connections explicitly defined..
|
||||
# Shows use of type constants from dt-bindings/arm/coresight-cti-dt.h
|
||||
# #size-cells and #address-cells are required if trig-conns@ nodes present.
|
||||
- |
|
||||
#include <dt-bindings/arm/coresight-cti-dt.h>
|
||||
|
||||
cti@858000 {
|
||||
compatible = "arm,coresight-cti", "arm,primecell";
|
||||
reg = <0x858000 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
arm,cti-ctm-id = <1>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
trig-conns@0 {
|
||||
reg = <0>;
|
||||
arm,trig-in-sigs = <4 5 6 7>;
|
||||
arm,trig-in-types = <ETM_EXTOUT
|
||||
ETM_EXTOUT
|
||||
ETM_EXTOUT
|
||||
ETM_EXTOUT>;
|
||||
arm,trig-out-sigs = <4 5 6 7>;
|
||||
arm,trig-out-types = <ETM_EXTIN
|
||||
ETM_EXTIN
|
||||
ETM_EXTIN
|
||||
ETM_EXTIN>;
|
||||
arm,cs-dev-assoc = <&etm0>;
|
||||
};
|
||||
|
||||
trig-conns@1 {
|
||||
reg = <1>;
|
||||
cpu = <&CPU0>;
|
||||
arm,trig-in-sigs = <0 1>;
|
||||
arm,trig-in-types = <PE_DBGTRIGGER
|
||||
PE_PMUIRQ>;
|
||||
arm,trig-out-sigs=<0 1 2 >;
|
||||
arm,trig-out-types = <PE_EDBGREQ
|
||||
PE_DBGRESTART
|
||||
PE_CTIIRQ>;
|
||||
|
||||
arm,trig-filters = <0>;
|
||||
};
|
||||
};
|
||||
# Implementation defined CTI - non CoreSight component connections.
|
||||
- |
|
||||
cti@20110000 {
|
||||
compatible = "arm,coresight-cti", "arm,primecell";
|
||||
reg = <0 0x20110000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
trig-conns@0 {
|
||||
reg = <0>;
|
||||
arm,trig-in-sigs=<0>;
|
||||
arm,trig-in-types=<GEN_INTREQ>;
|
||||
arm,trig-out-sigs=<0>;
|
||||
arm,trig-out-types=<GEN_HALTREQ>;
|
||||
arm,trig-conn-name = "sys_profiler";
|
||||
};
|
||||
|
||||
trig-conns@1 {
|
||||
reg = <1>;
|
||||
arm,trig-out-sigs=<2 3>;
|
||||
arm,trig-out-types=<GEN_HALTREQ GEN_RESTARTREQ>;
|
||||
arm,trig-conn-name = "watchdog";
|
||||
};
|
||||
|
||||
trig-conns@2 {
|
||||
reg = <2>;
|
||||
arm,trig-in-sigs=<1 6>;
|
||||
arm,trig-in-types=<GEN_HALTREQ GEN_RESTARTREQ>;
|
||||
arm,trig-conn-name = "g_counter";
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@ -45,6 +45,10 @@ its hardware characteristcs.
|
||||
- Coresight Address Translation Unit (CATU)
|
||||
"arm,coresight-catu", "arm,primecell";
|
||||
|
||||
- Coresight Cross Trigger Interface (CTI):
|
||||
"arm,coresight-cti", "arm,primecell";
|
||||
See coresight-cti.yaml for full CTI definitions.
|
||||
|
||||
* reg: physical base address and length of the register
|
||||
set(s) of the component.
|
||||
|
||||
@ -72,6 +76,9 @@ its hardware characteristcs.
|
||||
* reg-names: the only acceptable values are "stm-base" and
|
||||
"stm-stimulus-base", each corresponding to the areas defined in "reg".
|
||||
|
||||
* Required properties for Coresight Cross Trigger Interface (CTI)
|
||||
See coresight-cti.yaml for full CTI definitions.
|
||||
|
||||
* Required properties for devices that don't show up on the AMBA bus, such as
|
||||
non-configurable replicators and non-configurable funnels:
|
||||
|
||||
|
||||
@ -123,11 +123,18 @@ properties:
|
||||
- arm,cortex-a12
|
||||
- arm,cortex-a15
|
||||
- arm,cortex-a17
|
||||
- arm,cortex-a32
|
||||
- arm,cortex-a34
|
||||
- arm,cortex-a35
|
||||
- arm,cortex-a53
|
||||
- arm,cortex-a55
|
||||
- arm,cortex-a57
|
||||
- arm,cortex-a65
|
||||
- arm,cortex-a72
|
||||
- arm,cortex-a73
|
||||
- arm,cortex-a75
|
||||
- arm,cortex-a76
|
||||
- arm,cortex-a77
|
||||
- arm,cortex-m0
|
||||
- arm,cortex-m0+
|
||||
- arm,cortex-m1
|
||||
@ -136,6 +143,8 @@ properties:
|
||||
- arm,cortex-r4
|
||||
- arm,cortex-r5
|
||||
- arm,cortex-r7
|
||||
- arm,neoverse-e1
|
||||
- arm,neoverse-n1
|
||||
- brcm,brahma-b15
|
||||
- brcm,brahma-b53
|
||||
- brcm,vulcan
|
||||
@ -155,6 +164,8 @@ properties:
|
||||
- nvidia,tegra194-carmel
|
||||
- qcom,krait
|
||||
- qcom,kryo
|
||||
- qcom,kryo260
|
||||
- qcom,kryo280
|
||||
- qcom,kryo385
|
||||
- qcom,kryo485
|
||||
- qcom,scorpion
|
||||
@ -201,6 +212,8 @@ properties:
|
||||
- rockchip,rk3066-smp
|
||||
- socionext,milbeaut-m10v-smp
|
||||
- ste,dbx500-smp
|
||||
- ti,am3352
|
||||
- ti,am4372
|
||||
|
||||
cpu-release-addr:
|
||||
$ref: '/schemas/types.yaml#/definitions/uint64'
|
||||
@ -287,6 +300,39 @@ properties:
|
||||
While optional, it is the preferred way to get access to
|
||||
the cpu-core power-domains.
|
||||
|
||||
secondary-boot-reg:
|
||||
$ref: '/schemas/types.yaml#/definitions/uint32'
|
||||
description: |
|
||||
Required for systems that have an "enable-method" property value of
|
||||
"brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
|
||||
|
||||
This includes the following SoCs: |
|
||||
BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
|
||||
BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
|
||||
|
||||
The secondary-boot-reg property is a u32 value that specifies the
|
||||
physical address of the register used to request the ROM holding pen
|
||||
code release a secondary CPU. The value written to the register is
|
||||
formed by encoding the target CPU id into the low bits of the
|
||||
physical start address it should jump to.
|
||||
|
||||
if:
|
||||
# If the enable-method property contains one of those values
|
||||
properties:
|
||||
enable-method:
|
||||
contains:
|
||||
enum:
|
||||
- brcm,bcm11351-cpu-method
|
||||
- brcm,bcm23550
|
||||
- brcm,bcm-nsp-smp
|
||||
# and if enable-method is present
|
||||
required:
|
||||
- enable-method
|
||||
|
||||
then:
|
||||
required:
|
||||
- secondary-boot-reg
|
||||
|
||||
required:
|
||||
- device_type
|
||||
- reg
|
||||
|
||||
@ -164,7 +164,18 @@ Required properties:
|
||||
- compatible: should be:
|
||||
"fsl,imx8qxp-sc-key"
|
||||
followed by "fsl,imx-sc-key";
|
||||
- linux,keycodes: See Documentation/devicetree/bindings/input/keys.txt
|
||||
- linux,keycodes: See Documentation/devicetree/bindings/input/input.yaml
|
||||
|
||||
Thermal bindings based on SCU Message Protocol
|
||||
------------------------------------------------------------
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be :
|
||||
"fsl,imx8qxp-sc-thermal"
|
||||
followed by "fsl,imx-sc-thermal";
|
||||
|
||||
- #thermal-sensor-cells: See Documentation/devicetree/bindings/thermal/thermal.txt
|
||||
for a description.
|
||||
|
||||
Example (imx8qxp):
|
||||
-------------
|
||||
@ -238,6 +249,11 @@ firmware {
|
||||
compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
|
||||
timeout-sec = <60>;
|
||||
};
|
||||
|
||||
tsens: thermal-sensor {
|
||||
compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -119,6 +119,10 @@ properties:
|
||||
- fsl,imx6q-sabreauto
|
||||
- fsl,imx6q-sabrelite
|
||||
- fsl,imx6q-sabresd
|
||||
- technexion,imx6q-pico-dwarf # TechNexion i.MX6Q Pico-Dwarf
|
||||
- technexion,imx6q-pico-hobbit # TechNexion i.MX6Q Pico-Hobbit
|
||||
- technexion,imx6q-pico-nymph # TechNexion i.MX6Q Pico-Nymph
|
||||
- technexion,imx6q-pico-pi # TechNexion i.MX6Q Pico-Pi
|
||||
- technologic,imx6q-ts4900
|
||||
- technologic,imx6q-ts7970
|
||||
- toradex,apalis_imx6q # Apalis iMX6 Module
|
||||
@ -166,6 +170,10 @@ properties:
|
||||
- emtrion,emcon-mx6-avari # emCON-MX6S or emCON-MX6DL SoM on Avari Base
|
||||
- fsl,imx6dl-sabreauto # i.MX6 DualLite/Solo SABRE Automotive Board
|
||||
- fsl,imx6dl-sabresd # i.MX6 DualLite SABRE Smart Device Board
|
||||
- technexion,imx6dl-pico-dwarf # TechNexion i.MX6DL Pico-Dwarf
|
||||
- technexion,imx6dl-pico-hobbit # TechNexion i.MX6DL Pico-Hobbit
|
||||
- technexion,imx6dl-pico-nymph # TechNexion i.MX6DL Pico-Nymph
|
||||
- technexion,imx6dl-pico-pi # TechNexion i.MX6DL Pico-Pi
|
||||
- technologic,imx6dl-ts4900
|
||||
- technologic,imx6dl-ts7970
|
||||
- toradex,colibri_imx6dl # Colibri iMX6 Module
|
||||
@ -225,6 +233,9 @@ properties:
|
||||
- fsl,imx6ul-14x14-evk # i.MX6 UltraLite 14x14 EVK Board
|
||||
- kontron,imx6ul-n6310-som # Kontron N6310 SOM
|
||||
- kontron,imx6ul-n6311-som # Kontron N6311 SOM
|
||||
- technexion,imx6ul-pico-dwarf # TechNexion i.MX6UL Pico-Dwarf
|
||||
- technexion,imx6ul-pico-hobbit # TechNexion i.MX6UL Pico-Hobbit
|
||||
- technexion,imx6ul-pico-pi # TechNexion i.MX6UL Pico-Pi
|
||||
- const: fsl,imx6ul
|
||||
|
||||
- description: Kontron N6310 S Board
|
||||
@ -274,6 +285,7 @@ properties:
|
||||
items:
|
||||
- enum:
|
||||
- toradex,colibri-imx7s # Colibri iMX7 Solo Module
|
||||
- toradex,colibri-imx7s-aster # Colibri iMX7 Solo Module on Aster Carrier Board
|
||||
- toradex,colibri-imx7s-eval-v3 # Colibri iMX7 Solo Module on Colibri Evaluation Board V3
|
||||
- tq,imx7s-mba7 # i.MX7S TQ MBa7 with TQMa7S SoM
|
||||
- const: fsl,imx7s
|
||||
@ -284,8 +296,14 @@ properties:
|
||||
- fsl,imx7d-sdb # i.MX7 SabreSD Board
|
||||
- fsl,imx7d-sdb-reva # i.MX7 SabreSD Rev-A Board
|
||||
- novtech,imx7d-meerkat96 # i.MX7 Meerkat96 Board
|
||||
- technexion,imx7d-pico-dwarf # TechNexion i.MX7D Pico-Dwarf
|
||||
- technexion,imx7d-pico-hobbit # TechNexion i.MX7D Pico-Hobbit
|
||||
- technexion,imx7d-pico-nymph # TechNexion i.MX7D Pico-Nymph
|
||||
- technexion,imx7d-pico-pi # TechNexion i.MX7D Pico-Pi
|
||||
- toradex,colibri-imx7d # Colibri iMX7 Dual Module
|
||||
- toradex,colibri-imx7d-aster # Colibri iMX7 Dual Module on Aster Carrier Board
|
||||
- toradex,colibri-imx7d-emmc # Colibri iMX7 Dual 1GB (eMMC) Module
|
||||
- toradex,colibri-imx7d-emmc-aster # Colibri iMX7 Dual 1GB (eMMC) Module on Aster Carrier Board
|
||||
- toradex,colibri-imx7d-emmc-eval-v3 # Colibri iMX7 Dual 1GB (eMMC) Module on Colibri Evaluation Board V3
|
||||
- toradex,colibri-imx7d-eval-v3 # Colibri iMX7 Dual Module on Colibri Evaluation Board V3
|
||||
- tq,imx7d-mba7 # i.MX7D TQ MBa7 with TQMa7D SoM
|
||||
@ -324,6 +342,12 @@ properties:
|
||||
- fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board
|
||||
- const: fsl,imx8mn
|
||||
|
||||
- description: i.MX8MP based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx8mp-evk # i.MX8MP EVK Board
|
||||
- const: fsl,imx8mp
|
||||
|
||||
- description: i.MX8MQ based Boards
|
||||
items:
|
||||
- enum:
|
||||
@ -395,6 +419,51 @@ properties:
|
||||
- fsl,ls1021a-twr
|
||||
- const: fsl,ls1021a
|
||||
|
||||
- description: LS1028A based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,ls1028a-qds
|
||||
- fsl,ls1028a-rdb
|
||||
- const: fsl,ls1028a
|
||||
|
||||
- description: Kontron KBox A-230-LS
|
||||
items:
|
||||
- const: kontron,kbox-a-230-ls
|
||||
- const: kontron,sl28-var4
|
||||
- const: kontron,sl28
|
||||
- const: fsl,ls1028a
|
||||
- description:
|
||||
Kontron SMARC-sAL28 board on the SMARC Eval Carrier 2.0
|
||||
items:
|
||||
- enum:
|
||||
- kontron,sl28-var2-ads2
|
||||
- kontron,sl28-var3-ads2
|
||||
- kontron,sl28-var4-ads2
|
||||
- enum:
|
||||
- kontron,sl28-var2
|
||||
- kontron,sl28-var3
|
||||
- kontron,sl28-var4
|
||||
- const: kontron,sl28
|
||||
- const: fsl,ls1028a
|
||||
|
||||
- description:
|
||||
Kontron SMARC-sAL28 board (on a generic/undefined carrier)
|
||||
items:
|
||||
- enum:
|
||||
- kontron,sl28-var2
|
||||
- kontron,sl28-var3
|
||||
- kontron,sl28-var4
|
||||
- const: kontron,sl28
|
||||
- const: fsl,ls1028a
|
||||
|
||||
- description:
|
||||
Kontron SMARC-sAL28 board (base). This is used in the base device
|
||||
tree which is compatible with the overlays provided by the
|
||||
vendor.
|
||||
items:
|
||||
- const: kontron,sl28
|
||||
- const: fsl,ls1028a
|
||||
|
||||
- description: LS1043A based Boards
|
||||
items:
|
||||
- enum:
|
||||
|
||||
@ -29,27 +29,30 @@ allOf:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- arm,pl310-cache
|
||||
- arm,l220-cache
|
||||
- arm,l210-cache
|
||||
# DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
|
||||
- bcm,bcm11351-a2-pl310-cache
|
||||
# For Broadcom bcm11351 chipset where an
|
||||
# offset needs to be added to the address before passing down to the L2
|
||||
# cache controller
|
||||
- brcm,bcm11351-a2-pl310-cache
|
||||
# Marvell Controller designed to be
|
||||
# compatible with the ARM one, with system cache mode (meaning
|
||||
# maintenance operations on L1 are broadcasted to the L2 and L2
|
||||
# performs the same operation).
|
||||
- marvell,aurora-system-cache
|
||||
# Marvell Controller designed to be
|
||||
# compatible with the ARM one with outer cache mode.
|
||||
- marvell,aurora-outer-cache
|
||||
# Marvell Tauros3 cache controller, compatible
|
||||
# with arm,pl310-cache controller.
|
||||
- marvell,tauros3-cache
|
||||
oneOf:
|
||||
- enum:
|
||||
- arm,pl310-cache
|
||||
- arm,l220-cache
|
||||
- arm,l210-cache
|
||||
# DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
|
||||
- bcm,bcm11351-a2-pl310-cache
|
||||
# For Broadcom bcm11351 chipset where an
|
||||
# offset needs to be added to the address before passing down to the L2
|
||||
# cache controller
|
||||
- brcm,bcm11351-a2-pl310-cache
|
||||
# Marvell Controller designed to be
|
||||
# compatible with the ARM one, with system cache mode (meaning
|
||||
# maintenance operations on L1 are broadcasted to the L2 and L2
|
||||
# performs the same operation).
|
||||
- marvell,aurora-system-cache
|
||||
# Marvell Controller designed to be
|
||||
# compatible with the ARM one with outer cache mode.
|
||||
- marvell,aurora-outer-cache
|
||||
- items:
|
||||
# Marvell Tauros3 cache controller, compatible
|
||||
# with arm,pl310-cache controller.
|
||||
- const: marvell,tauros3-cache
|
||||
- const: arm,pl310-cache
|
||||
|
||||
cache-level:
|
||||
const: 2
|
||||
|
||||
@ -28,8 +28,11 @@ properties:
|
||||
items:
|
||||
- enum:
|
||||
- mrvl,mmp2-brownstone
|
||||
- olpc,xo-1.75
|
||||
- const: mrvl,mmp2
|
||||
- description: MMP3 based boards
|
||||
items:
|
||||
- const: mrvl,mmp3
|
||||
- enum:
|
||||
- dell,wyse-ariel
|
||||
- const: marvell,mmp3
|
||||
...
|
||||
|
||||
@ -43,6 +43,8 @@ required:
|
||||
- reg-names
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
@ -20,27 +20,36 @@ properties:
|
||||
items:
|
||||
- enum:
|
||||
- apm,potenza-pmu
|
||||
- arm,armv8-pmuv3
|
||||
- arm,cortex-a73-pmu
|
||||
- arm,cortex-a72-pmu
|
||||
- arm,cortex-a57-pmu
|
||||
- arm,cortex-a53-pmu
|
||||
- arm,cortex-a35-pmu
|
||||
- arm,cortex-a17-pmu
|
||||
- arm,cortex-a15-pmu
|
||||
- arm,cortex-a12-pmu
|
||||
- arm,cortex-a9-pmu
|
||||
- arm,cortex-a8-pmu
|
||||
- arm,cortex-a7-pmu
|
||||
- arm,cortex-a5-pmu
|
||||
- arm,arm11mpcore-pmu
|
||||
- arm,arm1176-pmu
|
||||
- arm,armv8-pmuv3 # Only for s/w models
|
||||
- arm,arm1136-pmu
|
||||
- arm,arm1176-pmu
|
||||
- arm,arm11mpcore-pmu
|
||||
- arm,cortex-a5-pmu
|
||||
- arm,cortex-a7-pmu
|
||||
- arm,cortex-a8-pmu
|
||||
- arm,cortex-a9-pmu
|
||||
- arm,cortex-a12-pmu
|
||||
- arm,cortex-a15-pmu
|
||||
- arm,cortex-a17-pmu
|
||||
- arm,cortex-a32-pmu
|
||||
- arm,cortex-a34-pmu
|
||||
- arm,cortex-a35-pmu
|
||||
- arm,cortex-a53-pmu
|
||||
- arm,cortex-a55-pmu
|
||||
- arm,cortex-a57-pmu
|
||||
- arm,cortex-a65-pmu
|
||||
- arm,cortex-a72-pmu
|
||||
- arm,cortex-a73-pmu
|
||||
- arm,cortex-a75-pmu
|
||||
- arm,cortex-a76-pmu
|
||||
- arm,cortex-a77-pmu
|
||||
- arm,neoverse-e1-pmu
|
||||
- arm,neoverse-n1-pmu
|
||||
- brcm,vulcan-pmu
|
||||
- cavium,thunder-pmu
|
||||
- qcom,krait-pmu
|
||||
- qcom,scorpion-pmu
|
||||
- qcom,scorpion-mp-pmu
|
||||
- qcom,krait-pmu
|
||||
|
||||
interrupts:
|
||||
# Don't know how many CPUs, so no constraints to specify
|
||||
|
||||
@ -32,6 +32,9 @@ description: |+
|
||||
http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: psci
|
||||
|
||||
compatible:
|
||||
oneOf:
|
||||
- description:
|
||||
@ -141,6 +144,8 @@ allOf:
|
||||
- cpu_off
|
||||
- cpu_on
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |+
|
||||
|
||||
|
||||
@ -28,6 +28,7 @@ description: |
|
||||
apq8074
|
||||
apq8084
|
||||
apq8096
|
||||
ipq6018
|
||||
ipq8074
|
||||
mdm9615
|
||||
msm8916
|
||||
@ -41,6 +42,7 @@ description: |
|
||||
The 'board' element must be one of the following strings:
|
||||
|
||||
cdp
|
||||
cp01-c1
|
||||
dragonboard
|
||||
hk01
|
||||
idp
|
||||
@ -150,4 +152,10 @@ properties:
|
||||
- enum:
|
||||
- qcom,sc7180-idp
|
||||
- const: qcom,sc7180
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,ipq6018-cp01-c1
|
||||
- const: qcom,ipq6018
|
||||
|
||||
...
|
||||
|
||||
@ -27,6 +27,8 @@ required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
prr: chipid@ff000044 {
|
||||
|
||||
@ -208,6 +208,7 @@ properties:
|
||||
- description: R-Car M3-W+ (R8A77961)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,m3ulcb # M3ULCB (R-Car Starter Kit Pro, RTP8J77961ASKB0SK0SA05A (M3 ES3.0))
|
||||
- renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012SA5A)
|
||||
- const: renesas,r8a77961
|
||||
|
||||
|
||||
@ -402,6 +402,11 @@ properties:
|
||||
- const: phytec,rk3288-phycore-som
|
||||
- const: rockchip,rk3288
|
||||
|
||||
- description: Pine64 PinebookPro
|
||||
items:
|
||||
- const: pine64,pinebook-pro
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: Pine64 Rock64
|
||||
items:
|
||||
- const: pine64,rock64
|
||||
@ -443,7 +448,7 @@ properties:
|
||||
|
||||
- description: Rockchip Kylin
|
||||
items:
|
||||
- const: rockchip,kylin-rk3036
|
||||
- const: rockchip,rk3036-kylin
|
||||
- const: rockchip,rk3036
|
||||
|
||||
- description: Rockchip PX3 Evaluation board
|
||||
@ -468,6 +473,11 @@ properties:
|
||||
- const: rockchip,r88
|
||||
- const: rockchip,rk3368
|
||||
|
||||
- description: Rockchip RK3036 Evaluation board
|
||||
items:
|
||||
- const: rockchip,rk3036-evb
|
||||
- const: rockchip,rk3036
|
||||
|
||||
- description: Rockchip RK3228 Evaluation board
|
||||
items:
|
||||
- const: rockchip,rk3228-evb
|
||||
|
||||
@ -30,6 +30,8 @@ required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
chipid@10000000 {
|
||||
|
||||
@ -89,6 +89,8 @@ required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/exynos5250.h>
|
||||
|
||||
@ -23,6 +23,8 @@ required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
firmware@203f000 {
|
||||
|
||||
@ -1,60 +0,0 @@
|
||||
UniPhier outer cache controller
|
||||
|
||||
UniPhier SoCs are integrated with a full-custom outer cache controller system.
|
||||
All of them have a level 2 cache controller, and some have a level 3 cache
|
||||
controller as well.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "socionext,uniphier-system-cache"
|
||||
- reg: offsets and lengths of the register sets for the device. It should
|
||||
contain 3 regions: control register, revision register, operation register,
|
||||
in this order.
|
||||
- cache-unified: specifies the cache is a unified cache.
|
||||
- cache-size: specifies the size in bytes of the cache
|
||||
- cache-sets: specifies the number of associativity sets of the cache
|
||||
- cache-line-size: specifies the line size in bytes
|
||||
- cache-level: specifies the level in the cache hierarchy. The value should
|
||||
be 2 for L2 cache, 3 for L3 cache, etc.
|
||||
|
||||
Optional properties:
|
||||
- next-level-cache: phandle to the next level cache if present. The next level
|
||||
cache should be also compatible with "socionext,uniphier-system-cache".
|
||||
|
||||
The L2 cache must exist to use the L3 cache; the cache hierarchy must be
|
||||
indicated correctly with "next-level-cache" properties.
|
||||
|
||||
Example 1 (system with L2):
|
||||
l2: l2-cache@500c0000 {
|
||||
compatible = "socionext,uniphier-system-cache";
|
||||
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
|
||||
<0x506c0000 0x400>;
|
||||
cache-unified;
|
||||
cache-size = <0x80000>;
|
||||
cache-sets = <256>;
|
||||
cache-line-size = <128>;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
Example 2 (system with L2 and L3):
|
||||
l2: l2-cache@500c0000 {
|
||||
compatible = "socionext,uniphier-system-cache";
|
||||
reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
|
||||
<0x506c0000 0x400>;
|
||||
cache-unified;
|
||||
cache-size = <0x200000>;
|
||||
cache-sets = <512>;
|
||||
cache-line-size = <128>;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&l3>;
|
||||
};
|
||||
|
||||
l3: l3-cache@500c8000 {
|
||||
compatible = "socionext,uniphier-system-cache";
|
||||
reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
|
||||
<0x506c8000 0x400>;
|
||||
cache-unified;
|
||||
cache-size = <0x400000>;
|
||||
cache-sets = <512>;
|
||||
cache-line-size = <256>;
|
||||
cache-level = <3>;
|
||||
};
|
||||
102
Bindings/arm/socionext/socionext,uniphier-system-cache.yaml
Normal file
102
Bindings/arm/socionext/socionext,uniphier-system-cache.yaml
Normal file
@ -0,0 +1,102 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/socionext/socionext,uniphier-system-cache.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: UniPhier outer cache controller
|
||||
|
||||
description: |
|
||||
UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
|
||||
controller system. All of them have a level 2 cache controller, and some
|
||||
have a level 3 cache controller as well.
|
||||
|
||||
maintainers:
|
||||
- Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: socionext,uniphier-system-cache
|
||||
|
||||
reg:
|
||||
description: |
|
||||
should contain 3 regions: control register, revision register,
|
||||
operation register, in this order.
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
|
||||
interrupts:
|
||||
description: |
|
||||
Interrupts can be used to notify the completion of cache operations.
|
||||
The number of interrupts should match to the number of CPU cores.
|
||||
The specified interrupts correspond to CPU0, CPU1, ... in this order.
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
cache-unified: true
|
||||
|
||||
cache-size: true
|
||||
|
||||
cache-sets: true
|
||||
|
||||
cache-line-size: true
|
||||
|
||||
cache-level:
|
||||
minimum: 2
|
||||
maximum: 3
|
||||
|
||||
next-level-cache: true
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/cache-controller.yaml#
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- cache-unified
|
||||
- cache-size
|
||||
- cache-sets
|
||||
- cache-line-size
|
||||
- cache-level
|
||||
|
||||
examples:
|
||||
- |
|
||||
// System with L2.
|
||||
cache-controller@500c0000 {
|
||||
compatible = "socionext,uniphier-system-cache";
|
||||
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
|
||||
interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
|
||||
cache-unified;
|
||||
cache-size = <0x140000>;
|
||||
cache-sets = <512>;
|
||||
cache-line-size = <128>;
|
||||
cache-level = <2>;
|
||||
};
|
||||
- |
|
||||
// System with L2 and L3.
|
||||
// L2 should specify the next level cache by 'next-level-cache'.
|
||||
l2: cache-controller@500c0000 {
|
||||
compatible = "socionext,uniphier-system-cache";
|
||||
reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
|
||||
interrupts = <0 190 4>, <0 191 4>;
|
||||
cache-unified;
|
||||
cache-size = <0x200000>;
|
||||
cache-sets = <512>;
|
||||
cache-line-size = <128>;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&l3>;
|
||||
};
|
||||
|
||||
l3: cache-controller@500c8000 {
|
||||
compatible = "socionext,uniphier-system-cache";
|
||||
reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
|
||||
interrupts = <0 174 4>, <0 175 4>;
|
||||
cache-unified;
|
||||
cache-size = <0x200000>;
|
||||
cache-sets = <512>;
|
||||
cache-line-size = <256>;
|
||||
cache-level = <3>;
|
||||
};
|
||||
@ -1,47 +0,0 @@
|
||||
Socionext UniPhier SoC family
|
||||
-----------------------------
|
||||
|
||||
Required properties in the root node:
|
||||
- compatible: should contain board and SoC compatible strings
|
||||
|
||||
SoC and board compatible strings:
|
||||
(sorted chronologically)
|
||||
|
||||
- LD4 SoC: "socionext,uniphier-ld4"
|
||||
- Reference Board: "socionext,uniphier-ld4-ref"
|
||||
|
||||
- Pro4 SoC: "socionext,uniphier-pro4"
|
||||
- Reference Board: "socionext,uniphier-pro4-ref"
|
||||
- Ace Board: "socionext,uniphier-pro4-ace"
|
||||
- Sanji Board: "socionext,uniphier-pro4-sanji"
|
||||
|
||||
- sLD8 SoC: "socionext,uniphier-sld8"
|
||||
- Reference Board: "socionext,uniphier-sld8-ref"
|
||||
|
||||
- PXs2 SoC: "socionext,uniphier-pxs2"
|
||||
- Gentil Board: "socionext,uniphier-pxs2-gentil"
|
||||
- Vodka Board: "socionext,uniphier-pxs2-vodka"
|
||||
|
||||
- LD6b SoC: "socionext,uniphier-ld6b"
|
||||
- Reference Board: "socionext,uniphier-ld6b-ref"
|
||||
|
||||
- LD11 SoC: "socionext,uniphier-ld11"
|
||||
- Reference Board: "socionext,uniphier-ld11-ref"
|
||||
- Global Board: "socionext,uniphier-ld11-global"
|
||||
|
||||
- LD20 SoC: "socionext,uniphier-ld20"
|
||||
- Reference Board: "socionext,uniphier-ld20-ref"
|
||||
- Global Board: "socionext,uniphier-ld20-global"
|
||||
|
||||
- PXs3 SoC: "socionext,uniphier-pxs3"
|
||||
- Reference Board: "socionext,uniphier-pxs3-ref"
|
||||
|
||||
Example:
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
compatible = "socionext,uniphier-ld20-ref", "socionext,uniphier-ld20";
|
||||
|
||||
...
|
||||
};
|
||||
61
Bindings/arm/socionext/uniphier.yaml
Normal file
61
Bindings/arm/socionext/uniphier.yaml
Normal file
@ -0,0 +1,61 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/socionext/uniphier.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Socionext UniPhier platform device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: /
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: LD4 SoC boards
|
||||
items:
|
||||
- enum:
|
||||
- socionext,uniphier-ld4-ref
|
||||
- const: socionext,uniphier-ld4
|
||||
- description: Pro4 SoC boards
|
||||
items:
|
||||
- enum:
|
||||
- socionext,uniphier-pro4-ace
|
||||
- socionext,uniphier-pro4-ref
|
||||
- socionext,uniphier-pro4-sanji
|
||||
- const: socionext,uniphier-pro4
|
||||
- description: sLD8 SoC boards
|
||||
items:
|
||||
- enum:
|
||||
- socionext,uniphier-sld8-ref
|
||||
- const: socionext,uniphier-sld8
|
||||
- description: PXs2 SoC boards
|
||||
items:
|
||||
- enum:
|
||||
- socionext,uniphier-pxs2-gentil
|
||||
- socionext,uniphier-pxs2-vodka
|
||||
- const: socionext,uniphier-pxs2
|
||||
- description: LD6b SoC boards
|
||||
items:
|
||||
- enum:
|
||||
- socionext,uniphier-ld6b-ref
|
||||
- const: socionext,uniphier-ld6b
|
||||
- description: LD11 SoC boards
|
||||
items:
|
||||
- enum:
|
||||
- socionext,uniphier-ld11-global
|
||||
- socionext,uniphier-ld11-ref
|
||||
- const: socionext,uniphier-ld11
|
||||
- description: LD20 SoC boards
|
||||
items:
|
||||
- enum:
|
||||
- socionext,uniphier-ld20-global
|
||||
- socionext,uniphier-ld20-ref
|
||||
- const: socionext,uniphier-ld20
|
||||
- description: PXs3 SoC boards
|
||||
items:
|
||||
- enum:
|
||||
- socionext,uniphier-pxs3-ref
|
||||
- const: socionext,uniphier-pxs3
|
||||
@ -29,6 +29,8 @@ required:
|
||||
- reg
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/stm32mp1-clks.h>
|
||||
|
||||
@ -394,6 +394,12 @@ properties:
|
||||
- const: linksprite,pcduino3-nano
|
||||
- const: allwinner,sun7i-a20
|
||||
|
||||
- description: Linutronix Testbox v2
|
||||
items:
|
||||
- const: linutronix,testbox-v2
|
||||
- const: lamobo,lamobo-r1
|
||||
- const: allwinner,sun7i-a20
|
||||
|
||||
- description: HAOYU Electronics Marsboard A10
|
||||
items:
|
||||
- const: haoyu,a10-marsboard
|
||||
@ -636,6 +642,21 @@ properties:
|
||||
- const: pine64,pinebook
|
||||
- const: allwinner,sun50i-a64
|
||||
|
||||
- description: Pine64 PinePhone Developer Batch (1.0)
|
||||
items:
|
||||
- const: pine64,pinephone-1.0
|
||||
- const: allwinner,sun50i-a64
|
||||
|
||||
- description: Pine64 PinePhone Braveheart (1.1)
|
||||
items:
|
||||
- const: pine64,pinephone-1.1
|
||||
- const: allwinner,sun50i-a64
|
||||
|
||||
- description: Pine64 PineTab
|
||||
items:
|
||||
- const: pine64,pinetab
|
||||
- const: allwinner,sun50i-a64
|
||||
|
||||
- description: Pine64 SoPine Baseboard
|
||||
items:
|
||||
- const: pine64,sopine-baseboard
|
||||
@ -647,6 +668,11 @@ properties:
|
||||
- const: pineriver,mini-xplus
|
||||
- const: allwinner,sun4i-a10
|
||||
|
||||
- description: PocketBook Touch Lux 3
|
||||
items:
|
||||
- const: pocketbook,touch-lux-3
|
||||
- const: allwinner,sun5i-a13
|
||||
|
||||
- description: Point of View Protab2-IPS9
|
||||
items:
|
||||
- const: pov,protab2-ips9
|
||||
|
||||
@ -30,6 +30,7 @@ properties:
|
||||
enum:
|
||||
- allwinner,sun5i-a13-mbus
|
||||
- allwinner,sun8i-h3-mbus
|
||||
- allwinner,sun50i-a64-mbus
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@ -41,6 +42,10 @@ properties:
|
||||
description:
|
||||
See section 2.3.9 of the DeviceTree Specification.
|
||||
|
||||
'#address-cells': true
|
||||
|
||||
'#size-cells': true
|
||||
|
||||
required:
|
||||
- "#interconnect-cells"
|
||||
- compatible
|
||||
@ -58,6 +63,8 @@ examples:
|
||||
compatible = "allwinner,sun5i-a13-mbus";
|
||||
reg = <0x01c01000 0x1000>;
|
||||
clocks = <&ccu CLK_MBUS>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
dma-ranges = <0x00000000 0x40000000 0x20000000>;
|
||||
#interconnect-cells = <1>;
|
||||
};
|
||||
|
||||
@ -1,300 +0,0 @@
|
||||
NVIDIA Tegra Power Management Controller (PMC)
|
||||
|
||||
== Power Management Controller Node ==
|
||||
|
||||
The PMC block interacts with an external Power Management Unit. The PMC
|
||||
mostly controls the entry and exit of the system from different sleep
|
||||
modes. It provides power-gating controllers for SoC and CPU power-islands.
|
||||
|
||||
Required properties:
|
||||
- name : Should be pmc
|
||||
- compatible : Should contain one of the following:
|
||||
For Tegra20 must contain "nvidia,tegra20-pmc".
|
||||
For Tegra30 must contain "nvidia,tegra30-pmc".
|
||||
For Tegra114 must contain "nvidia,tegra114-pmc"
|
||||
For Tegra124 must contain "nvidia,tegra124-pmc"
|
||||
For Tegra132 must contain "nvidia,tegra124-pmc"
|
||||
For Tegra210 must contain "nvidia,tegra210-pmc"
|
||||
- reg : Offset and length of the register set for the device
|
||||
- clocks : Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names : Must include the following entries:
|
||||
"pclk" (The Tegra clock of that name),
|
||||
"clk32k_in" (The 32KHz clock input to Tegra).
|
||||
|
||||
Optional properties:
|
||||
- nvidia,invert-interrupt : If present, inverts the PMU interrupt signal.
|
||||
The PMU is an external Power Management Unit, whose interrupt output
|
||||
signal is fed into the PMC. This signal is optionally inverted, and then
|
||||
fed into the ARM GIC. The PMC is not involved in the detection or
|
||||
handling of this interrupt signal, merely its inversion.
|
||||
- nvidia,suspend-mode : The suspend mode that the platform should use.
|
||||
Valid values are 0, 1 and 2:
|
||||
0 (LP0): CPU + Core voltage off and DRAM in self-refresh
|
||||
1 (LP1): CPU voltage off and DRAM in self-refresh
|
||||
2 (LP2): CPU voltage off
|
||||
- nvidia,core-power-req-active-high : Boolean, core power request active-high
|
||||
- nvidia,sys-clock-req-active-high : Boolean, system clock request active-high
|
||||
- nvidia,combined-power-req : Boolean, combined power request for CPU & Core
|
||||
- nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC)
|
||||
is enabled.
|
||||
|
||||
Required properties when nvidia,suspend-mode is specified:
|
||||
- nvidia,cpu-pwr-good-time : CPU power good time in uS.
|
||||
- nvidia,cpu-pwr-off-time : CPU power off time in uS.
|
||||
- nvidia,core-pwr-good-time : <Oscillator-stable-time Power-stable-time>
|
||||
Core power good time in uS.
|
||||
- nvidia,core-pwr-off-time : Core power off time in uS.
|
||||
|
||||
Required properties when nvidia,suspend-mode=<0>:
|
||||
- nvidia,lp0-vec : <start length> Starting address and length of LP0 vector
|
||||
The LP0 vector contains the warm boot code that is executed by AVP when
|
||||
resuming from the LP0 state. The AVP (Audio-Video Processor) is an ARM7
|
||||
processor and always being the first boot processor when chip is power on
|
||||
or resume from deep sleep mode. When the system is resumed from the deep
|
||||
sleep mode, the warm boot code will restore some PLLs, clocks and then
|
||||
bring up CPU0 for resuming the system.
|
||||
|
||||
Hardware-triggered thermal reset:
|
||||
On Tegra30, Tegra114 and Tegra124, if the 'i2c-thermtrip' subnode exists,
|
||||
hardware-triggered thermal reset will be enabled.
|
||||
|
||||
Required properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'):
|
||||
- nvidia,i2c-controller-id : ID of I2C controller to send poweroff command to. Valid values are
|
||||
described in section 9.2.148 "APBDEV_PMC_SCRATCH53_0" of the
|
||||
Tegra K1 Technical Reference Manual.
|
||||
- nvidia,bus-addr : Bus address of the PMU on the I2C bus
|
||||
- nvidia,reg-addr : I2C register address to write poweroff command to
|
||||
- nvidia,reg-data : Poweroff command to write to PMU
|
||||
|
||||
Optional properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'):
|
||||
- nvidia,pinmux-id : Pinmux used by the hardware when issuing poweroff command.
|
||||
Defaults to 0. Valid values are described in section 12.5.2
|
||||
"Pinmux Support" of the Tegra4 Technical Reference Manual.
|
||||
|
||||
Optional nodes:
|
||||
- powergates : This node contains a hierarchy of power domain nodes, which
|
||||
should match the powergates on the Tegra SoC. See "Powergate
|
||||
Nodes" below.
|
||||
|
||||
Example:
|
||||
|
||||
/ SoC dts including file
|
||||
pmc@7000f400 {
|
||||
compatible = "nvidia,tegra20-pmc";
|
||||
reg = <0x7000e400 0x400>;
|
||||
clocks = <&tegra_car 110>, <&clk32k_in>;
|
||||
clock-names = "pclk", "clk32k_in";
|
||||
nvidia,invert-interrupt;
|
||||
nvidia,suspend-mode = <1>;
|
||||
nvidia,cpu-pwr-good-time = <2000>;
|
||||
nvidia,cpu-pwr-off-time = <100>;
|
||||
nvidia,core-pwr-good-time = <3845 3845>;
|
||||
nvidia,core-pwr-off-time = <458>;
|
||||
nvidia,core-power-req-active-high;
|
||||
nvidia,sys-clock-req-active-high;
|
||||
nvidia,lp0-vec = <0xbdffd000 0x2000>;
|
||||
};
|
||||
|
||||
/ Tegra board dts file
|
||||
{
|
||||
...
|
||||
pmc@7000f400 {
|
||||
i2c-thermtrip {
|
||||
nvidia,i2c-controller-id = <4>;
|
||||
nvidia,bus-addr = <0x40>;
|
||||
nvidia,reg-addr = <0x36>;
|
||||
nvidia,reg-data = <0x2>;
|
||||
};
|
||||
};
|
||||
...
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
...
|
||||
};
|
||||
|
||||
|
||||
== Powergate Nodes ==
|
||||
|
||||
Each of the powergate nodes represents a power-domain on the Tegra SoC
|
||||
that can be power-gated by the Tegra PMC. The name of the powergate node
|
||||
should be one of the below. Note that not every powergate is applicable
|
||||
to all Tegra devices and the following list shows which powergates are
|
||||
applicable to which devices. Please refer to the Tegra TRM for more
|
||||
details on the various powergates.
|
||||
|
||||
Name Description Devices Applicable
|
||||
3d 3D Graphics Tegra20/114/124/210
|
||||
3d0 3D Graphics 0 Tegra30
|
||||
3d1 3D Graphics 1 Tegra30
|
||||
aud Audio Tegra210
|
||||
dfd Debug Tegra210
|
||||
dis Display A Tegra114/124/210
|
||||
disb Display B Tegra114/124/210
|
||||
heg 2D Graphics Tegra30/114/124/210
|
||||
iram Internal RAM Tegra124/210
|
||||
mpe MPEG Encode All
|
||||
nvdec NVIDIA Video Decode Engine Tegra210
|
||||
nvjpg NVIDIA JPEG Engine Tegra210
|
||||
pcie PCIE Tegra20/30/124/210
|
||||
sata SATA Tegra30/124/210
|
||||
sor Display interfaces Tegra124/210
|
||||
ve2 Video Encode Engine 2 Tegra210
|
||||
venc Video Encode Engine All
|
||||
vdec Video Decode Engine Tegra20/30/114/124
|
||||
vic Video Imaging Compositor Tegra124/210
|
||||
xusba USB Partition A Tegra114/124/210
|
||||
xusbb USB Partition B Tegra114/124/210
|
||||
xusbc USB Partition C Tegra114/124/210
|
||||
|
||||
Required properties:
|
||||
- clocks: Must contain an entry for each clock required by the PMC for
|
||||
controlling a power-gate. See ../clocks/clock-bindings.txt for details.
|
||||
- resets: Must contain an entry for each reset required by the PMC for
|
||||
controlling a power-gate. See ../reset/reset.txt for details.
|
||||
- #power-domain-cells: Must be 0.
|
||||
|
||||
Example:
|
||||
|
||||
pmc: pmc@7000e400 {
|
||||
compatible = "nvidia,tegra210-pmc";
|
||||
reg = <0x0 0x7000e400 0x0 0x400>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
|
||||
clock-names = "pclk", "clk32k_in";
|
||||
|
||||
powergates {
|
||||
pd_audio: aud {
|
||||
clocks = <&tegra_car TEGRA210_CLK_APE>,
|
||||
<&tegra_car TEGRA210_CLK_APB2APE>;
|
||||
resets = <&tegra_car 198>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
== Powergate Clients ==
|
||||
|
||||
Hardware blocks belonging to a power domain should contain a "power-domains"
|
||||
property that is a phandle pointing to the corresponding powergate node.
|
||||
|
||||
Example:
|
||||
|
||||
adma: adma@702e2000 {
|
||||
...
|
||||
power-domains = <&pd_audio>;
|
||||
...
|
||||
};
|
||||
|
||||
== Pad Control ==
|
||||
|
||||
On Tegra SoCs a pad is a set of pins which are configured as a group.
|
||||
The pin grouping is a fixed attribute of the hardware. The PMC can be
|
||||
used to set pad power state and signaling voltage. A pad can be either
|
||||
in active or power down mode. The support for power state and signaling
|
||||
voltage configuration varies depending on the pad in question. 3.3 V and
|
||||
1.8 V signaling voltages are supported on pins where software
|
||||
controllable signaling voltage switching is available.
|
||||
|
||||
The pad configuration state nodes are placed under the pmc node and they
|
||||
are referred to by the pinctrl client properties. For more information
|
||||
see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
|
||||
The pad name should be used as the value of the pins property in pin
|
||||
configuration nodes.
|
||||
|
||||
The following pads are present on Tegra124 and Tegra132:
|
||||
audio bb cam comp
|
||||
csia csb cse dsi
|
||||
dsib dsic dsid hdmi
|
||||
hsic hv lvds mipi-bias
|
||||
nand pex-bias pex-clk1 pex-clk2
|
||||
pex-cntrl sdmmc1 sdmmc3 sdmmc4
|
||||
sys_ddc uart usb0 usb1
|
||||
usb2 usb_bias
|
||||
|
||||
The following pads are present on Tegra210:
|
||||
audio audio-hv cam csia
|
||||
csib csic csid csie
|
||||
csif dbg debug-nonao dmic
|
||||
dp dsi dsib dsic
|
||||
dsid emmc emmc2 gpio
|
||||
hdmi hsic lvds mipi-bias
|
||||
pex-bias pex-clk1 pex-clk2 pex-cntrl
|
||||
sdmmc1 sdmmc3 spi spi-hv
|
||||
uart usb0 usb1 usb2
|
||||
usb3 usb-bias
|
||||
|
||||
Required pin configuration properties:
|
||||
- pins: Must contain name of the pad(s) to be configured.
|
||||
|
||||
Optional pin configuration properties:
|
||||
- low-power-enable: Configure the pad into power down mode
|
||||
- low-power-disable: Configure the pad into active mode
|
||||
- power-source: Must contain either TEGRA_IO_PAD_VOLTAGE_1V8
|
||||
or TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
|
||||
The values are defined in
|
||||
include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
|
||||
|
||||
Note: The power state can be configured on all of the Tegra124 and
|
||||
Tegra132 pads. None of the Tegra124 or Tegra132 pads support
|
||||
signaling voltage switching.
|
||||
|
||||
Note: All of the listed Tegra210 pads except pex-cntrl support power
|
||||
state configuration. Signaling voltage switching is supported on
|
||||
following Tegra210 pads: audio, audio-hv, cam, dbg, dmic, gpio,
|
||||
pex-cntrl, sdmmc1, sdmmc3, spi, spi-hv, and uart.
|
||||
|
||||
Pad configuration state example:
|
||||
pmc: pmc@7000e400 {
|
||||
compatible = "nvidia,tegra210-pmc";
|
||||
reg = <0x0 0x7000e400 0x0 0x400>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
|
||||
clock-names = "pclk", "clk32k_in";
|
||||
|
||||
...
|
||||
|
||||
sdmmc1_3v3: sdmmc1-3v3 {
|
||||
pins = "sdmmc1";
|
||||
power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
|
||||
};
|
||||
|
||||
sdmmc1_1v8: sdmmc1-1v8 {
|
||||
pins = "sdmmc1";
|
||||
power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
|
||||
};
|
||||
|
||||
hdmi_off: hdmi-off {
|
||||
pins = "hdmi";
|
||||
low-power-enable;
|
||||
}
|
||||
|
||||
hdmi_on: hdmi-on {
|
||||
pins = "hdmi";
|
||||
low-power-disable;
|
||||
}
|
||||
};
|
||||
|
||||
Pinctrl client example:
|
||||
sdmmc1: sdhci@700b0000 {
|
||||
...
|
||||
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
|
||||
pinctrl-0 = <&sdmmc1_3v3>;
|
||||
pinctrl-1 = <&sdmmc1_1v8>;
|
||||
};
|
||||
...
|
||||
sor@54540000 {
|
||||
...
|
||||
pinctrl-0 = <&hdmi_off>;
|
||||
pinctrl-1 = <&hdmi_on>;
|
||||
pinctrl-names = "hdmi-on", "hdmi-off";
|
||||
};
|
||||
354
Bindings/arm/tegra/nvidia,tegra20-pmc.yaml
Normal file
354
Bindings/arm/tegra/nvidia,tegra20-pmc.yaml
Normal file
@ -0,0 +1,354 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Tegra Power Management Controller (PMC)
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jonathan Hunter <jonathanh@nvidia.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra20-pmc
|
||||
- nvidia,tegra20-pmc
|
||||
- nvidia,tegra30-pmc
|
||||
- nvidia,tegra114-pmc
|
||||
- nvidia,tegra124-pmc
|
||||
- nvidia,tegra210-pmc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
description:
|
||||
Offset and length of the register set for the device.
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pclk
|
||||
- const: clk32k_in
|
||||
description:
|
||||
Must includes entries pclk and clk32k_in.
|
||||
pclk is the Tegra clock of that name and clk32k_in is 32KHz clock
|
||||
input to Tegra.
|
||||
|
||||
clocks:
|
||||
maxItems: 2
|
||||
description:
|
||||
Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clocks-bindings.txt for details.
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
description:
|
||||
Tegra PMC has clk_out_1, clk_out_2, and clk_out_3.
|
||||
PMC also has blink control which allows 32Khz clock output to
|
||||
Tegra blink pad.
|
||||
Consumer of PMC clock should specify the desired clock by having
|
||||
the clock ID in its "clocks" phandle cell with pmc clock provider.
|
||||
See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC
|
||||
clock IDs.
|
||||
|
||||
'#interrupt-cells':
|
||||
const: 2
|
||||
description:
|
||||
Specifies number of cells needed to encode an interrupt source.
|
||||
The value must be 2.
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
nvidia,invert-interrupt:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: Inverts the PMU interrupt signal.
|
||||
The PMU is an external Power Management Unit, whose interrupt output
|
||||
signal is fed into the PMC. This signal is optionally inverted, and
|
||||
then fed into the ARM GIC. The PMC is not involved in the detection
|
||||
or handling of this interrupt signal, merely its inversion.
|
||||
|
||||
nvidia,core-power-req-active-high:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: Core power request active-high.
|
||||
|
||||
nvidia,sys-clock-req-active-high:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: System clock request active-high.
|
||||
|
||||
nvidia,combined-power-req:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: combined power request for CPU and Core.
|
||||
|
||||
nvidia,cpu-pwr-good-en:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
CPU power good signal from external PMIC to PMC is enabled.
|
||||
|
||||
nvidia,suspend-mode:
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [0, 1, 2]
|
||||
description:
|
||||
The suspend mode that the platform should use.
|
||||
Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh
|
||||
Mode 1 is for LP1, CPU voltage off and DRAM in self-refresh
|
||||
Mode 2 is for LP2, CPU voltage off
|
||||
|
||||
nvidia,cpu-pwr-good-time:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: CPU power good time in uSec.
|
||||
|
||||
nvidia,cpu-pwr-off-time:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: CPU power off time in uSec.
|
||||
|
||||
nvidia,core-pwr-good-time:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
description:
|
||||
<Oscillator-stable-time Power-stable-time>
|
||||
Core power good time in uSec.
|
||||
|
||||
nvidia,core-pwr-off-time:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Core power off time in uSec.
|
||||
|
||||
nvidia,lp0-vec:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
description:
|
||||
<start length> Starting address and length of LP0 vector.
|
||||
The LP0 vector contains the warm boot code that is executed
|
||||
by AVP when resuming from the LP0 state.
|
||||
The AVP (Audio-Video Processor) is an ARM7 processor and
|
||||
always being the first boot processor when chip is power on
|
||||
or resume from deep sleep mode. When the system is resumed
|
||||
from the deep sleep mode, the warm boot code will restore
|
||||
some PLLs, clocks and then brings up CPU0 for resuming the
|
||||
system.
|
||||
|
||||
i2c-thermtrip:
|
||||
type: object
|
||||
description:
|
||||
On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists,
|
||||
hardware-triggered thermal reset will be enabled.
|
||||
|
||||
properties:
|
||||
nvidia,i2c-controller-id:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
ID of I2C controller to send poweroff command to PMU.
|
||||
Valid values are described in section 9.2.148
|
||||
"APBDEV_PMC_SCRATCH53_0" of the Tegra K1 Technical Reference
|
||||
Manual.
|
||||
|
||||
nvidia,bus-addr:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Bus address of the PMU on the I2C bus.
|
||||
|
||||
nvidia,reg-addr:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: PMU I2C register address to issue poweroff command.
|
||||
|
||||
nvidia,reg-data:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Poweroff command to write to PMU.
|
||||
|
||||
nvidia,pinmux-id:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Pinmux used by the hardware when issuing Poweroff command.
|
||||
Defaults to 0. Valid values are described in section 12.5.2
|
||||
"Pinmux Support" of the Tegra4 Technical Reference Manual.
|
||||
|
||||
required:
|
||||
- nvidia,i2c-controller-id
|
||||
- nvidia,bus-addr
|
||||
- nvidia,reg-addr
|
||||
- nvidia,reg-data
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
powergates:
|
||||
type: object
|
||||
description: |
|
||||
This node contains a hierarchy of power domain nodes, which should
|
||||
match the powergates on the Tegra SoC. Each powergate node
|
||||
represents a power-domain on the Tegra SoC that can be power-gated
|
||||
by the Tegra PMC.
|
||||
Hardware blocks belonging to a power domain should contain
|
||||
"power-domains" property that is a phandle pointing to corresponding
|
||||
powergate node.
|
||||
The name of the powergate node should be one of the below. Note that
|
||||
not every powergate is applicable to all Tegra devices and the following
|
||||
list shows which powergates are applicable to which devices.
|
||||
Please refer to Tegra TRM for mode details on the powergate nodes to
|
||||
use for each power-gate block inside Tegra.
|
||||
Name Description Devices Applicable
|
||||
3d 3D Graphics Tegra20/114/124/210
|
||||
3d0 3D Graphics 0 Tegra30
|
||||
3d1 3D Graphics 1 Tegra30
|
||||
aud Audio Tegra210
|
||||
dfd Debug Tegra210
|
||||
dis Display A Tegra114/124/210
|
||||
disb Display B Tegra114/124/210
|
||||
heg 2D Graphics Tegra30/114/124/210
|
||||
iram Internal RAM Tegra124/210
|
||||
mpe MPEG Encode All
|
||||
nvdec NVIDIA Video Decode Engine Tegra210
|
||||
nvjpg NVIDIA JPEG Engine Tegra210
|
||||
pcie PCIE Tegra20/30/124/210
|
||||
sata SATA Tegra30/124/210
|
||||
sor Display interfaces Tegra124/210
|
||||
ve2 Video Encode Engine 2 Tegra210
|
||||
venc Video Encode Engine All
|
||||
vdec Video Decode Engine Tegra20/30/114/124
|
||||
vic Video Imaging Compositor Tegra124/210
|
||||
xusba USB Partition A Tegra114/124/210
|
||||
xusbb USB Partition B Tegra114/124/210
|
||||
xusbc USB Partition C Tegra114/124/210
|
||||
|
||||
patternProperties:
|
||||
"^[a-z0-9]+$":
|
||||
type: object
|
||||
|
||||
patternProperties:
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
description:
|
||||
Must contain an entry for each clock required by the PMC
|
||||
for controlling a power-gate.
|
||||
See ../clocks/clock-bindings.txt document for more details.
|
||||
|
||||
resets:
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
description:
|
||||
Must contain an entry for each reset required by the PMC
|
||||
for controlling a power-gate.
|
||||
See ../reset/reset.txt for more details.
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 0
|
||||
description: Must be 0.
|
||||
|
||||
required:
|
||||
- clocks
|
||||
- resets
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
patternProperties:
|
||||
"^[a-f0-9]+-[a-f0-9]+$":
|
||||
type: object
|
||||
description:
|
||||
This is a Pad configuration node. On Tegra SOCs a pad is a set of
|
||||
pins which are configured as a group. The pin grouping is a fixed
|
||||
attribute of the hardware. The PMC can be used to set pad power state
|
||||
and signaling voltage. A pad can be either in active or power down mode.
|
||||
The support for power state and signaling voltage configuration varies
|
||||
depending on the pad in question. 3.3V and 1.8V signaling voltages
|
||||
are supported on pins where software controllable signaling voltage
|
||||
switching is available.
|
||||
|
||||
The pad configuration state nodes are placed under the pmc node and they
|
||||
are referred to by the pinctrl client properties. For more information
|
||||
see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
|
||||
The pad name should be used as the value of the pins property in pin
|
||||
configuration nodes.
|
||||
|
||||
The following pads are present on Tegra124 and Tegra132
|
||||
audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi, hsic,
|
||||
hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, pex-cntrl,
|
||||
sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, usb_bias.
|
||||
|
||||
The following pads are present on Tegra210
|
||||
audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg,
|
||||
debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, hdmi,
|
||||
hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
|
||||
sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias.
|
||||
|
||||
properties:
|
||||
pins:
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
description: Must contain name of the pad(s) to be configured.
|
||||
|
||||
low-power-enable:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: Configure the pad into power down mode.
|
||||
|
||||
low-power-disable:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: Configure the pad into active mode.
|
||||
|
||||
power-source:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
|
||||
TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
|
||||
The values are defined in
|
||||
include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
|
||||
Power state can be configured on all Tegra124 and Tegra132
|
||||
pads. None of the Tegra124 or Tegra132 pads support signaling
|
||||
voltage switching.
|
||||
All of the listed Tegra210 pads except pex-cntrl support power
|
||||
state configuration. Signaling voltage switching is supported
|
||||
on below Tegra210 pads.
|
||||
audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1,
|
||||
sdmmc3, spi, spi-hv, and uart.
|
||||
|
||||
required:
|
||||
- pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clock-names
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
|
||||
dependencies:
|
||||
"nvidia,suspend-mode": ["nvidia,core-pwr-off-time", "nvidia,cpu-pwr-off-time"]
|
||||
"nvidia,core-pwr-off-time": ["nvidia,core-pwr-good-time"]
|
||||
"nvidia,cpu-pwr-off-time": ["nvidia,cpu-pwr-good-time"]
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
#include <dt-bindings/clock/tegra210-car.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
|
||||
#include <dt-bindings/soc/tegra-pmc.h>
|
||||
|
||||
tegra_pmc: pmc@7000e400 {
|
||||
compatible = "nvidia,tegra210-pmc";
|
||||
reg = <0x0 0x7000e400 0x0 0x400>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
|
||||
clock-names = "pclk", "clk32k_in";
|
||||
#clock-cells = <1>;
|
||||
|
||||
nvidia,invert-interrupt;
|
||||
nvidia,suspend-mode = <0>;
|
||||
nvidia,cpu-pwr-good-time = <0>;
|
||||
nvidia,cpu-pwr-off-time = <0>;
|
||||
nvidia,core-pwr-good-time = <4587 3876>;
|
||||
nvidia,core-pwr-off-time = <39065>;
|
||||
nvidia,core-power-req-active-high;
|
||||
nvidia,sys-clock-req-active-high;
|
||||
|
||||
powergates {
|
||||
pd_audio: aud {
|
||||
clocks = <&tegra_car TEGRA210_CLK_APE>,
|
||||
<&tegra_car TEGRA210_CLK_APB2APE>;
|
||||
resets = <&tegra_car 198>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
pd_xusbss: xusba {
|
||||
clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
|
||||
resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1,229 +0,0 @@
|
||||
ARM Versatile Express boards family
|
||||
-----------------------------------
|
||||
|
||||
ARM's Versatile Express platform consists of a motherboard and one
|
||||
or more daughterboards (tiles). The motherboard provides a set of
|
||||
peripherals. Processor and RAM "live" on the tiles.
|
||||
|
||||
The motherboard and each core tile should be described by a separate
|
||||
Device Tree source file, with the tile's description including
|
||||
the motherboard file using a /include/ directive. As the motherboard
|
||||
can be initialized in one of two different configurations ("memory
|
||||
maps"), care must be taken to include the correct one.
|
||||
|
||||
|
||||
Root node
|
||||
---------
|
||||
|
||||
Required properties in the root node:
|
||||
- compatible value:
|
||||
compatible = "arm,vexpress,<model>", "arm,vexpress";
|
||||
where <model> is the full tile model name (as used in the tile's
|
||||
Technical Reference Manual), eg.:
|
||||
- for Coretile Express A5x2 (V2P-CA5s):
|
||||
compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
|
||||
- for Coretile Express A9x4 (V2P-CA9):
|
||||
compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
|
||||
If a tile comes in several variants or can be used in more then one
|
||||
configuration, the compatible value should be:
|
||||
compatible = "arm,vexpress,<model>,<variant>", \
|
||||
"arm,vexpress,<model>", "arm,vexpress";
|
||||
eg:
|
||||
- Coretile Express A15x2 (V2P-CA15) with Tech Chip 1:
|
||||
compatible = "arm,vexpress,v2p-ca15,tc1", \
|
||||
"arm,vexpress,v2p-ca15", "arm,vexpress";
|
||||
- LogicTile Express 13MG (V2F-2XV6) running Cortex-A7 (3 cores) SMM:
|
||||
compatible = "arm,vexpress,v2f-2xv6,ca7x3", \
|
||||
"arm,vexpress,v2f-2xv6", "arm,vexpress";
|
||||
|
||||
Optional properties in the root node:
|
||||
- tile model name (use name from the tile's Technical Reference
|
||||
Manual, eg. "V2P-CA5s")
|
||||
model = "<model>";
|
||||
- tile's HBI number (unique ARM's board model ID, visible on the
|
||||
PCB's silkscreen) in hexadecimal transcription:
|
||||
arm,hbi = <0xhbi>
|
||||
eg:
|
||||
- for Coretile Express A5x2 (V2P-CA5s) HBI-0191:
|
||||
arm,hbi = <0x191>;
|
||||
- Coretile Express A9x4 (V2P-CA9) HBI-0225:
|
||||
arm,hbi = <0x225>;
|
||||
|
||||
|
||||
CPU nodes
|
||||
---------
|
||||
|
||||
Top-level standard "cpus" node is required. It must contain a node
|
||||
with device_type = "cpu" property for every available core, eg.:
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a5";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
Configuration infrastructure
|
||||
----------------------------
|
||||
|
||||
The platform has an elaborated configuration system, consisting of
|
||||
microcontrollers residing on the mother- and daughterboards known
|
||||
as Motherboard/Daughterboard Configuration Controller (MCC and DCC).
|
||||
The controllers are responsible for the platform initialization
|
||||
(reset generation, flash programming, FPGA bitfiles loading etc.)
|
||||
but also control clock generators, voltage regulators, gather
|
||||
environmental data like temperature, power consumption etc. Even
|
||||
the video output switch (FPGA) is controlled that way.
|
||||
|
||||
The controllers are not mapped into normal memory address space
|
||||
and must be accessed through bridges - other devices capable
|
||||
of generating transactions on the configuration bus.
|
||||
|
||||
The nodes describing configuration controllers must define
|
||||
the following properties:
|
||||
- compatible value:
|
||||
compatible = "arm,vexpress,config-bus";
|
||||
- bridge phandle:
|
||||
arm,vexpress,config-bridge = <phandle>;
|
||||
and children describing available functions.
|
||||
|
||||
|
||||
Platform topology
|
||||
-----------------
|
||||
|
||||
As Versatile Express can be configured in number of physically
|
||||
different setups, the device tree should describe platform topology.
|
||||
Root node and main motherboard node must define the following
|
||||
property, describing physical location of the children nodes:
|
||||
- site number:
|
||||
arm,vexpress,site = <number>;
|
||||
where 0 means motherboard, 1 or 2 are daugtherboard sites,
|
||||
0xf means "master" site (site containing main CPU tile)
|
||||
- when daughterboards are stacked on one site, their position
|
||||
in the stack be be described with:
|
||||
arm,vexpress,position = <number>;
|
||||
- when describing tiles consisting more than one DCC, its number
|
||||
can be described with:
|
||||
arm,vexpress,dcc = <number>;
|
||||
|
||||
Any of the numbers above defaults to zero if not defined in
|
||||
the node or any of its parent.
|
||||
|
||||
|
||||
Motherboard
|
||||
-----------
|
||||
|
||||
The motherboard description file provides a single "motherboard" node
|
||||
using 2 address cells corresponding to the Static Memory Bus used
|
||||
between the motherboard and the tile. The first cell defines the Chip
|
||||
Select (CS) line number, the second cell address offset within the CS.
|
||||
All interrupt lines between the motherboard and the tile are active
|
||||
high and are described using single cell.
|
||||
|
||||
Optional properties of the "motherboard" node:
|
||||
- motherboard's memory map variant:
|
||||
arm,v2m-memory-map = "<name>";
|
||||
where name is one of:
|
||||
- "rs1" - for RS1 map (i.a. peripherals on CS3); this map is also
|
||||
referred to as "ARM Cortex-A Series memory map":
|
||||
arm,v2m-memory-map = "rs1";
|
||||
When this property is missing, the motherboard is using the original
|
||||
memory map (also known as the "Legacy memory map", primarily used
|
||||
with the original CoreTile Express A9x4) with peripherals on CS7.
|
||||
|
||||
Motherboard .dtsi files provide a set of labelled peripherals that
|
||||
can be used to obtain required phandle in the tile's "aliases" node:
|
||||
- UARTs, note that the numbers correspond to the physical connectors
|
||||
on the motherboard's back panel:
|
||||
v2m_serial0, v2m_serial1, v2m_serial2 and v2m_serial3
|
||||
- I2C controllers:
|
||||
v2m_i2c_dvi and v2m_i2c_pcie
|
||||
- SP804 timers:
|
||||
v2m_timer01 and v2m_timer23
|
||||
|
||||
The tile description should define a "smb" node, describing the
|
||||
Static Memory Bus between the tile and motherboard. It must define
|
||||
the following properties:
|
||||
- "simple-bus" compatible value (to ensure creation of the children)
|
||||
compatible = "simple-bus";
|
||||
- mapping of the SMB CS/offset addresses into main address space:
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <...>;
|
||||
- interrupts mapping:
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 63>;
|
||||
interrupt-map = <...>;
|
||||
|
||||
|
||||
Example of a VE tile description (simplified)
|
||||
---------------------------------------------
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "V2P-CA5s";
|
||||
arm,hbi = <0x225>;
|
||||
arm,vexpress,site = <0xf>;
|
||||
compatible = "arm,vexpress-v2p-ca5s", "arm,vexpress";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
chosen { };
|
||||
|
||||
aliases {
|
||||
serial0 = &v2m_serial0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a5";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@2c001000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x2c001000 0x1000>,
|
||||
<0x2c000100 0x100>;
|
||||
};
|
||||
|
||||
dcc {
|
||||
compatible = "arm,vexpress,config-bus";
|
||||
arm,vexpress,config-bridge = <&v2m_sysreg>;
|
||||
|
||||
osc@0 {
|
||||
compatible = "arm,vexpress-osc";
|
||||
};
|
||||
};
|
||||
|
||||
smb {
|
||||
compatible = "simple-bus";
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
/* CS0 is visible at 0x08000000 */
|
||||
ranges = <0 0 0x08000000 0x04000000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 63>;
|
||||
/* Active high IRQ 0 is connected to GIC's SPI0 */
|
||||
interrupt-map = <0 0 0 &gic 0 0 4>;
|
||||
|
||||
/include/ "vexpress-v2m-rs1.dtsi"
|
||||
};
|
||||
};
|
||||
|
||||
71
Bindings/ata/renesas,rcar-sata.yaml
Normal file
71
Bindings/ata/renesas,rcar-sata.yaml
Normal file
@ -0,0 +1,71 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/ata/renesas,rcar-sata.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Renesas R-Car Serial-ATA Interface
|
||||
|
||||
maintainers:
|
||||
- Geert Uytterhoeven <geert+renesas@glider.be>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- renesas,sata-r8a7779 # R-Car H1
|
||||
- items:
|
||||
- enum:
|
||||
- renesas,sata-r8a7790-es1 # R-Car H2 ES1
|
||||
- renesas,sata-r8a7790 # R-Car H2 other than ES1
|
||||
- renesas,sata-r8a7791 # R-Car M2-W
|
||||
- renesas,sata-r8a7793 # R-Car M2-N
|
||||
- const: renesas,rcar-gen2-sata # generic R-Car Gen2
|
||||
- items:
|
||||
- enum:
|
||||
- renesas,sata-r8a774b1 # RZ/G2N
|
||||
- renesas,sata-r8a7795 # R-Car H3
|
||||
- renesas,sata-r8a77965 # R-Car M3-N
|
||||
- const: renesas,rcar-gen3-sata # generic R-Car Gen3 or RZ/G2
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/r8a7791-cpg-mssr.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/r8a7791-sysc.h>
|
||||
|
||||
sata@ee300000 {
|
||||
compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata";
|
||||
reg = <0xee300000 0x200000>;
|
||||
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 815>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 815>;
|
||||
};
|
||||
@ -1,36 +0,0 @@
|
||||
* Renesas R-Car SATA
|
||||
|
||||
Required properties:
|
||||
- compatible : should contain one or more of the following:
|
||||
- "renesas,sata-r8a774b1" for RZ/G2N
|
||||
- "renesas,sata-r8a7779" for R-Car H1
|
||||
- "renesas,sata-r8a7790-es1" for R-Car H2 ES1
|
||||
- "renesas,sata-r8a7790" for R-Car H2 other than ES1
|
||||
- "renesas,sata-r8a7791" for R-Car M2-W
|
||||
- "renesas,sata-r8a7793" for R-Car M2-N
|
||||
- "renesas,sata-r8a7795" for R-Car H3
|
||||
- "renesas,sata-r8a77965" for R-Car M3-N
|
||||
- "renesas,rcar-gen2-sata" for a generic R-Car Gen2
|
||||
compatible device
|
||||
- "renesas,rcar-gen3-sata" for a generic R-Car Gen3 or
|
||||
RZ/G2 compatible device
|
||||
- "renesas,rcar-sata" is deprecated
|
||||
|
||||
When compatible with the generic version nodes
|
||||
must list the SoC-specific version corresponding
|
||||
to the platform first followed by the generic
|
||||
version.
|
||||
|
||||
- reg : address and length of the SATA registers;
|
||||
- interrupts : must consist of one interrupt specifier.
|
||||
- clocks : must contain a reference to the functional clock.
|
||||
|
||||
Example:
|
||||
|
||||
sata0: sata@ee300000 {
|
||||
compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata";
|
||||
reg = <0 0xee300000 0 0x2000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
|
||||
};
|
||||
96
Bindings/bus/socionext,uniphier-system-bus.yaml
Normal file
96
Bindings/bus/socionext,uniphier-system-bus.yaml
Normal file
@ -0,0 +1,96 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/bus/socionext,uniphier-system-bus.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: UniPhier System Bus
|
||||
|
||||
description: |
|
||||
The UniPhier System Bus is an external bus that connects on-board devices to
|
||||
the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and
|
||||
some control signals. It supports up to 8 banks (chip selects).
|
||||
|
||||
Before any access to the bus, the bus controller must be configured; the bus
|
||||
controller registers provide the control for the translation from the offset
|
||||
within each bank to the CPU-viewed address. The needed setup includes the
|
||||
base address, the size of each bank. Optionally, some timing parameters can
|
||||
be optimized for faster bus access.
|
||||
|
||||
maintainers:
|
||||
- Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: socionext,uniphier-system-bus
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#address-cells":
|
||||
description: |
|
||||
The first cell is the bank number (chip select).
|
||||
The second cell is the address offset within the bank.
|
||||
const: 2
|
||||
|
||||
"#size-cells":
|
||||
const: 1
|
||||
|
||||
ranges:
|
||||
description: |
|
||||
Provide address translation from the System Bus to the parent bus.
|
||||
|
||||
Note:
|
||||
The address region(s) that can be assigned for the System Bus is
|
||||
implementation defined. Some SoCs can use 0x00000000-0x0fffffff and
|
||||
0x40000000-0x4fffffff, while other SoCs only 0x40000000-0x4fffffff.
|
||||
There might be additional limitations depending on SoCs and the boot mode.
|
||||
The address translation is arbitrary as long as the banks are assigned in
|
||||
the supported address space with the required alignment and they do not
|
||||
overlap one another.
|
||||
|
||||
For example, it is possible to map:
|
||||
bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff
|
||||
It is also possible to map:
|
||||
bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff
|
||||
There is no reason to stick to a particular translation mapping, but the
|
||||
"ranges" property should provide a "reasonable" default that is known to
|
||||
work. The software should initialize the bus controller according to it.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
- ranges
|
||||
|
||||
examples:
|
||||
- |
|
||||
// In this example,
|
||||
// - the Ethernet device is connected at the offset 0x01f00000 of CS1 and
|
||||
// mapped to 0x43f00000 of the parent bus.
|
||||
// - the UART device is connected at the offset 0x00200000 of CS5 and
|
||||
// mapped to 0x46200000 of the parent bus.
|
||||
|
||||
system-bus@58c00000 {
|
||||
compatible = "socionext,uniphier-system-bus";
|
||||
reg = <0x58c00000 0x400>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <1 0x00000000 0x42000000 0x02000000>,
|
||||
<5 0x00000000 0x46000000 0x01000000>;
|
||||
|
||||
ethernet@1,01f00000 {
|
||||
compatible = "smsc,lan9115";
|
||||
reg = <1 0x01f00000 0x1000>;
|
||||
interrupts = <0 48 4>;
|
||||
phy-mode = "mii";
|
||||
};
|
||||
|
||||
uart@5,00200000 {
|
||||
compatible = "ns16550a";
|
||||
reg = <5 0x00200000 0x20>;
|
||||
interrupts = <0 49 4>;
|
||||
clock-frequency = <12288000>;
|
||||
};
|
||||
};
|
||||
@ -38,6 +38,7 @@ Required standard properties:
|
||||
"ti,sysc-dra7-mcasp"
|
||||
"ti,sysc-usb-host-fs"
|
||||
"ti,sysc-dra7-mcan"
|
||||
"ti,sysc-pruss"
|
||||
|
||||
- reg shall have register areas implemented for the interconnect
|
||||
target module in question such as revision, sysc and syss
|
||||
|
||||
@ -1,66 +0,0 @@
|
||||
UniPhier System Bus
|
||||
|
||||
The UniPhier System Bus is an external bus that connects on-board devices to
|
||||
the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and
|
||||
some control signals. It supports up to 8 banks (chip selects).
|
||||
|
||||
Before any access to the bus, the bus controller must be configured; the bus
|
||||
controller registers provide the control for the translation from the offset
|
||||
within each bank to the CPU-viewed address. The needed setup includes the base
|
||||
address, the size of each bank. Optionally, some timing parameters can be
|
||||
optimized for faster bus access.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "socionext,uniphier-system-bus".
|
||||
- reg: offset and length of the register set for the bus controller device.
|
||||
- #address-cells: should be 2. The first cell is the bank number (chip select).
|
||||
The second cell is the address offset within the bank.
|
||||
- #size-cells: should be 1.
|
||||
- ranges: should provide a proper address translation from the System Bus to
|
||||
the parent bus.
|
||||
|
||||
Note:
|
||||
The address region(s) that can be assigned for the System Bus is implementation
|
||||
defined. Some SoCs can use 0x00000000-0x0fffffff and 0x40000000-0x4fffffff,
|
||||
while other SoCs can only use 0x40000000-0x4fffffff. There might be additional
|
||||
limitations depending on SoCs and the boot mode. The address translation is
|
||||
arbitrary as long as the banks are assigned in the supported address space with
|
||||
the required alignment and they do not overlap one another.
|
||||
For example, it is possible to map:
|
||||
bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff
|
||||
It is also possible to map:
|
||||
bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff
|
||||
There is no reason to stick to a particular translation mapping, but the
|
||||
"ranges" property should provide a "reasonable" default that is known to work.
|
||||
The software should initialize the bus controller according to it.
|
||||
|
||||
Example:
|
||||
|
||||
system-bus {
|
||||
compatible = "socionext,uniphier-system-bus";
|
||||
reg = <0x58c00000 0x400>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <1 0x00000000 0x42000000 0x02000000
|
||||
5 0x00000000 0x46000000 0x01000000>;
|
||||
|
||||
ethernet@1,01f00000 {
|
||||
compatible = "smsc,lan9115";
|
||||
reg = <1 0x01f00000 0x1000>;
|
||||
interrupts = <0 48 4>
|
||||
phy-mode = "mii";
|
||||
};
|
||||
|
||||
uart@5,00200000 {
|
||||
compatible = "ns16550a";
|
||||
reg = <5 0x00200000 0x20>;
|
||||
interrupts = <0 49 4>
|
||||
clock-frequency = <12288000>;
|
||||
};
|
||||
};
|
||||
|
||||
In this example,
|
||||
- the Ethernet device is connected at the offset 0x01f00000 of CS1 and
|
||||
mapped to 0x43f00000 of the parent bus.
|
||||
- the UART device is connected at the offset 0x00200000 of CS5 and
|
||||
mapped to 0x46200000 of the parent bus.
|
||||
54
Bindings/chrome/google,cros-ec-typec.yaml
Normal file
54
Bindings/chrome/google,cros-ec-typec.yaml
Normal file
@ -0,0 +1,54 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/chrome/google,cros-ec-typec.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Google Chrome OS EC(Embedded Controller) Type C port driver.
|
||||
|
||||
maintainers:
|
||||
- Benson Leung <bleung@chromium.org>
|
||||
- Prashant Malani <pmalani@chromium.org>
|
||||
|
||||
description:
|
||||
Chrome OS devices have an Embedded Controller(EC) which has access to
|
||||
Type C port state. This node is intended to allow the host to read and
|
||||
control the Type C ports. The node for this device should be under a
|
||||
cros-ec node like google,cros-ec-spi.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: google,cros-ec-typec
|
||||
|
||||
connector:
|
||||
$ref: /schemas/connector/usb-connector.yaml#
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
examples:
|
||||
- |+
|
||||
spi0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cros_ec: ec@0 {
|
||||
compatible = "google,cros-ec-spi";
|
||||
reg = <0>;
|
||||
|
||||
typec {
|
||||
compatible = "google,cros-ec-typec";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
connector@0 {
|
||||
compatible = "usb-c-connector";
|
||||
reg = <0>;
|
||||
power-role = "dual";
|
||||
data-role = "dual";
|
||||
try-power-role = "source";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
103
Bindings/clock/arm,syscon-icst.yaml
Normal file
103
Bindings/clock/arm,syscon-icst.yaml
Normal file
@ -0,0 +1,103 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/arm,syscon-icst.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM System Controller ICST Clocks
|
||||
|
||||
maintainers:
|
||||
- Linus Walleij <linusw@kernel.org>
|
||||
|
||||
description: |
|
||||
The ICS525 and ICS307 oscillators are produced by Integrated
|
||||
Devices Technology (IDT). ARM integrated these oscillators deeply into their
|
||||
reference designs by adding special control registers that manage such
|
||||
oscillators to their system controllers.
|
||||
|
||||
The various ARM system controllers contain logic to serialize and initialize
|
||||
an ICST clock request after a write to the 32 bit register at an offset
|
||||
into the system controller. Furthermore, to even be able to alter one of
|
||||
these frequencies, the system controller must first be unlocked by
|
||||
writing a special token to another offset in the system controller.
|
||||
|
||||
Some ARM hardware contain special versions of the serial interface that only
|
||||
connects the low 8 bits of the VDW (missing one bit), hard-wires RDW to
|
||||
different values and sometimes also hard-wires the output divider. They
|
||||
therefore have special compatible strings as per this table (the OD value is
|
||||
the value on the pins, not the resulting output divider).
|
||||
|
||||
In the core modules and logic tiles, the ICST is a configurable clock fed
|
||||
from a 24 MHz clock on the motherboard (usually the main crystal) used for
|
||||
generating e.g. video clocks. It is located on the core module and there is
|
||||
only one of these. This clock node must be a subnode of the core module.
|
||||
|
||||
Hardware variant RDW OD VDW
|
||||
|
||||
Integrator/AP 22 1 Bit 8 0, rest variable
|
||||
integratorap-cm
|
||||
|
||||
Integrator/AP 46 3 Bit 8 0, rest variable
|
||||
integratorap-sys
|
||||
|
||||
Integrator/AP 22 or 1 17 or (33 or 25 MHz)
|
||||
integratorap-pci 14 1 14
|
||||
|
||||
Integrator/CP 22 variable Bit 8 0, rest variable
|
||||
integratorcp-cm-core
|
||||
|
||||
Integrator/CP 22 variable Bit 8 0, rest variable
|
||||
integratorcp-cm-mem
|
||||
|
||||
The ICST oscillator must be provided inside a system controller node.
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- arm,syscon-icst525
|
||||
- arm,syscon-icst307
|
||||
- arm,syscon-icst525-integratorap-cm
|
||||
- arm,syscon-icst525-integratorap-sys
|
||||
- arm,syscon-icst525-integratorap-pci
|
||||
- arm,syscon-icst525-integratorcp-cm-core
|
||||
- arm,syscon-icst525-integratorcp-cm-mem
|
||||
- arm,integrator-cm-auxosc
|
||||
- arm,versatile-cm-auxosc
|
||||
- arm,impd-vco1
|
||||
- arm,impd-vco2
|
||||
|
||||
clocks:
|
||||
description: Parent clock for the ICST VCO
|
||||
maxItems: 1
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
lock-offset:
|
||||
$ref: '/schemas/types.yaml#/definitions/uint32'
|
||||
description: Offset to the unlocking register for the oscillator
|
||||
|
||||
vco-offset:
|
||||
$ref: '/schemas/types.yaml#/definitions/uint32'
|
||||
description: Offset to the VCO register for the oscillator
|
||||
|
||||
required:
|
||||
- "#clock-cells"
|
||||
- compatible
|
||||
- clocks
|
||||
|
||||
examples:
|
||||
- |
|
||||
vco1: clock {
|
||||
compatible = "arm,impd1-vco1";
|
||||
#clock-cells = <0>;
|
||||
lock-offset = <0x08>;
|
||||
vco-offset = <0x00>;
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "IM-PD1-VCO1";
|
||||
};
|
||||
|
||||
...
|
||||
@ -1,34 +0,0 @@
|
||||
Clock bindings for ARM Integrator and Versatile Core Module clocks
|
||||
|
||||
Auxiliary Oscillator Clock
|
||||
|
||||
This is a configurable clock fed from a 24 MHz chrystal,
|
||||
used for generating e.g. video clocks. It is located on the
|
||||
core module and there is only one of these.
|
||||
|
||||
This clock node *must* be a subnode of the core module, since
|
||||
it obtains the base address for it's address range from its
|
||||
parent node.
|
||||
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "arm,integrator-cm-auxosc" or "arm,versatile-cm-auxosc"
|
||||
- #clock-cells: must be <0>
|
||||
|
||||
Optional properties:
|
||||
- clocks: parent clock(s)
|
||||
|
||||
Example:
|
||||
|
||||
core-module@10000000 {
|
||||
xtal24mhz: xtal24mhz@24M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
auxosc: cm_aux_osc@25M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "arm,integrator-cm-auxosc";
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
};
|
||||
@ -1,70 +0,0 @@
|
||||
ARM System Controller ICST clocks
|
||||
|
||||
The ICS525 and ICS307 oscillators are produced by Integrated Devices
|
||||
Technology (IDT). ARM integrated these oscillators deeply into their
|
||||
reference designs by adding special control registers that manage such
|
||||
oscillators to their system controllers.
|
||||
|
||||
The various ARM system controllers contain logic to serialize and initialize
|
||||
an ICST clock request after a write to the 32 bit register at an offset
|
||||
into the system controller. Furthermore, to even be able to alter one of
|
||||
these frequencies, the system controller must first be unlocked by
|
||||
writing a special token to another offset in the system controller.
|
||||
|
||||
Some ARM hardware contain special versions of the serial interface that only
|
||||
connects the low 8 bits of the VDW (missing one bit), hardwires RDW to
|
||||
different values and sometimes also hardwire the output divider. They
|
||||
therefore have special compatible strings as per this table (the OD value is
|
||||
the value on the pins, not the resulting output divider):
|
||||
|
||||
Hardware variant: RDW OD VDW
|
||||
|
||||
Integrator/AP 22 1 Bit 8 0, rest variable
|
||||
integratorap-cm
|
||||
|
||||
Integrator/AP 46 3 Bit 8 0, rest variable
|
||||
integratorap-sys
|
||||
|
||||
Integrator/AP 22 or 1 17 or (33 or 25 MHz)
|
||||
integratorap-pci 14 1 14
|
||||
|
||||
Integrator/CP 22 variable Bit 8 0, rest variable
|
||||
integratorcp-cm-core
|
||||
|
||||
Integrator/CP 22 variable Bit 8 0, rest variable
|
||||
integratorcp-cm-mem
|
||||
|
||||
The ICST oscillator must be provided inside a system controller node.
|
||||
|
||||
Required properties:
|
||||
- compatible: must be one of
|
||||
"arm,syscon-icst525"
|
||||
"arm,syscon-icst307"
|
||||
"arm,syscon-icst525-integratorap-cm"
|
||||
"arm,syscon-icst525-integratorap-sys"
|
||||
"arm,syscon-icst525-integratorap-pci"
|
||||
"arm,syscon-icst525-integratorcp-cm-core"
|
||||
"arm,syscon-icst525-integratorcp-cm-mem"
|
||||
- lock-offset: the offset address into the system controller where the
|
||||
unlocking register is located
|
||||
- vco-offset: the offset address into the system controller where the
|
||||
ICST control register is located (even 32 bit address)
|
||||
- #clock-cells: must be <0>
|
||||
- clocks: parent clock, since the ICST needs a parent clock to derive its
|
||||
frequency from, this attribute is compulsory.
|
||||
|
||||
Example:
|
||||
|
||||
syscon: syscon@10000000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x10000000 0x1000>;
|
||||
|
||||
oscclk0: osc0@c {
|
||||
compatible = "arm,syscon-icst307";
|
||||
#clock-cells = <0>;
|
||||
lock-offset = <0x20>;
|
||||
vco-offset = <0x0c>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
(...)
|
||||
};
|
||||
@ -94,7 +94,7 @@ clock is connected to output 0 of the &ref.
|
||||
/* external oscillator */
|
||||
osc: oscillator {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <1>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32678>;
|
||||
clock-output-names = "osc";
|
||||
};
|
||||
|
||||
@ -21,6 +21,9 @@ properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 0
|
||||
|
||||
@ -41,6 +44,8 @@ required:
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Display PIXEL Clock node:
|
||||
- |
|
||||
|
||||
@ -1,29 +0,0 @@
|
||||
* Clock bindings for NXP i.MX8M Mini
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx8mm-ccm"
|
||||
- reg: Address and length of the register set
|
||||
- #clock-cells: Should be <1>
|
||||
- clocks: list of clock specifiers, must contain an entry for each required
|
||||
entry in clock-names
|
||||
- clock-names: should include the following entries:
|
||||
- "osc_32k"
|
||||
- "osc_24m"
|
||||
- "clk_ext1"
|
||||
- "clk_ext2"
|
||||
- "clk_ext3"
|
||||
- "clk_ext4"
|
||||
|
||||
clk: clock-controller@30380000 {
|
||||
compatible = "fsl,imx8mm-ccm";
|
||||
reg = <0x0 0x30380000 0x0 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
|
||||
<&clk_ext3>, <&clk_ext4>;
|
||||
clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
|
||||
"clk_ext3", "clk_ext4";
|
||||
};
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mm-clock.h
|
||||
for the full list of i.MX8M Mini clock IDs.
|
||||
68
Bindings/clock/imx8mm-clock.yaml
Normal file
68
Bindings/clock/imx8mm-clock.yaml
Normal file
@ -0,0 +1,68 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/imx8mm-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NXP i.MX8M Mini Clock Control Module Binding
|
||||
|
||||
maintainers:
|
||||
- Anson Huang <Anson.Huang@nxp.com>
|
||||
|
||||
description: |
|
||||
NXP i.MX8M Mini clock control module is an integrated clock controller, which
|
||||
generates and supplies to all modules.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx8mm-ccm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: 32k osc
|
||||
- description: 24m osc
|
||||
- description: ext1 clock input
|
||||
- description: ext2 clock input
|
||||
- description: ext3 clock input
|
||||
- description: ext4 clock input
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: osc_32k
|
||||
- const: osc_24m
|
||||
- const: clk_ext1
|
||||
- const: clk_ext2
|
||||
- const: clk_ext3
|
||||
- const: clk_ext4
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
description:
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mm-clock.h
|
||||
for the full list of i.MX8M Mini clock IDs.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
|
||||
examples:
|
||||
# Clock Control Module node:
|
||||
- |
|
||||
clk: clock-controller@30380000 {
|
||||
compatible = "fsl,imx8mm-ccm";
|
||||
reg = <0x30380000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
|
||||
<&clk_ext3>, <&clk_ext4>;
|
||||
clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
|
||||
"clk_ext3", "clk_ext4";
|
||||
};
|
||||
|
||||
...
|
||||
@ -40,7 +40,7 @@ properties:
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
description: |
|
||||
description:
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mn-clock.h
|
||||
for the full list of i.MX8M Nano clock IDs.
|
||||
@ -52,12 +52,14 @@ required:
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Clock Control Module node:
|
||||
- |
|
||||
clk: clock-controller@30380000 {
|
||||
compatible = "fsl,imx8mn-ccm";
|
||||
reg = <0x0 0x30380000 0x0 0x10000>;
|
||||
reg = <0x30380000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>,
|
||||
<&clk_ext2>, <&clk_ext3>, <&clk_ext4>;
|
||||
@ -65,48 +67,4 @@ examples:
|
||||
"clk_ext2", "clk_ext3", "clk_ext4";
|
||||
};
|
||||
|
||||
# Required external clocks for Clock Control Module node:
|
||||
- |
|
||||
osc_32k: clock-osc-32k {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "osc_32k";
|
||||
};
|
||||
|
||||
osc_24m: clock-osc-24m {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "osc_24m";
|
||||
};
|
||||
|
||||
clk_ext1: clock-ext1 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <133000000>;
|
||||
clock-output-names = "clk_ext1";
|
||||
};
|
||||
|
||||
clk_ext2: clock-ext2 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <133000000>;
|
||||
clock-output-names = "clk_ext2";
|
||||
};
|
||||
|
||||
clk_ext3: clock-ext3 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <133000000>;
|
||||
clock-output-names = "clk_ext3";
|
||||
};
|
||||
|
||||
clk_ext4: clock-ext4 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency= <133000000>;
|
||||
clock-output-names = "clk_ext4";
|
||||
};
|
||||
|
||||
...
|
||||
|
||||
@ -52,6 +52,8 @@ required:
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Clock Control Module node:
|
||||
- |
|
||||
|
||||
@ -1,20 +0,0 @@
|
||||
* Clock bindings for NXP i.MX8M Quad
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx8mq-ccm"
|
||||
- reg: Address and length of the register set
|
||||
- #clock-cells: Should be <1>
|
||||
- clocks: list of clock specifiers, must contain an entry for each required
|
||||
entry in clock-names
|
||||
- clock-names: should include the following entries:
|
||||
- "ckil"
|
||||
- "osc_25m"
|
||||
- "osc_27m"
|
||||
- "clk_ext1"
|
||||
- "clk_ext2"
|
||||
- "clk_ext3"
|
||||
- "clk_ext4"
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mq-clock.h
|
||||
for the full list of i.MX8M Quad clock IDs.
|
||||
72
Bindings/clock/imx8mq-clock.yaml
Normal file
72
Bindings/clock/imx8mq-clock.yaml
Normal file
@ -0,0 +1,72 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/imx8mq-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NXP i.MX8M Quad Clock Control Module Binding
|
||||
|
||||
maintainers:
|
||||
- Anson Huang <Anson.Huang@nxp.com>
|
||||
|
||||
description: |
|
||||
NXP i.MX8M Quad clock control module is an integrated clock controller, which
|
||||
generates and supplies to all modules.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx8mq-ccm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: 32k osc
|
||||
- description: 25m osc
|
||||
- description: 27m osc
|
||||
- description: ext1 clock input
|
||||
- description: ext2 clock input
|
||||
- description: ext3 clock input
|
||||
- description: ext4 clock input
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: ckil
|
||||
- const: osc_25m
|
||||
- const: osc_27m
|
||||
- const: clk_ext1
|
||||
- const: clk_ext2
|
||||
- const: clk_ext3
|
||||
- const: clk_ext4
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
description:
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mq-clock.h
|
||||
for the full list of i.MX8M Quad clock IDs.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
|
||||
examples:
|
||||
# Clock Control Module node:
|
||||
- |
|
||||
clk: clock-controller@30380000 {
|
||||
compatible = "fsl,imx8mq-ccm";
|
||||
reg = <0x30380000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
|
||||
<&clk_ext1>, <&clk_ext2>,
|
||||
<&clk_ext3>, <&clk_ext4>;
|
||||
clock-names = "ckil", "osc_25m", "osc_27m",
|
||||
"clk_ext1", "clk_ext2",
|
||||
"clk_ext3", "clk_ext4";
|
||||
};
|
||||
|
||||
...
|
||||
64
Bindings/clock/marvell,mmp2-clock.yaml
Normal file
64
Bindings/clock/marvell,mmp2-clock.yaml
Normal file
@ -0,0 +1,64 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/marvell,mmp2-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell MMP2 and MMP3 Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Lubomir Rintel <lkundrak@v3.sk>
|
||||
|
||||
description: |
|
||||
The clock subsystem on MMP2 or MMP3 generates and supplies clock to various
|
||||
controllers within the SoC.
|
||||
|
||||
Each clock is assigned an identifier and client nodes use this identifier
|
||||
to specify the clock which they consume.
|
||||
|
||||
All these identifiers could be found in <dt-bindings/clock/marvell,mmp2.h>.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- marvell,mmp2-clock # controller compatible with MMP2 SoC
|
||||
- marvell,mmp3-clock # controller compatible with MMP3 SoC
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: MPMU register region
|
||||
- description: APMU register region
|
||||
- description: APBC register region
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: mpmu
|
||||
- const: apmu
|
||||
- const: apbc
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@d4050000 {
|
||||
compatible = "marvell,mmp2-clock";
|
||||
reg = <0xd4050000 0x1000>,
|
||||
<0xd4282800 0x400>,
|
||||
<0xd4015000 0x1000>;
|
||||
reg-names = "mpmu", "apmu", "apbc";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -1,21 +0,0 @@
|
||||
* Marvell MMP2 Clock Controller
|
||||
|
||||
The MMP2 clock subsystem generates and supplies clock to various
|
||||
controllers within the MMP2 SoC.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be one of the following.
|
||||
- "marvell,mmp2-clock" - controller compatible with MMP2 SoC.
|
||||
|
||||
- reg: physical base address of the clock subsystem and length of memory mapped
|
||||
region. There are 3 places in SOC has clock control logic:
|
||||
"mpmu", "apmu", "apbc". So three reg spaces need to be defined.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Each clock is assigned an identifier and client nodes use this identifier
|
||||
to specify the clock which they consume.
|
||||
|
||||
All these identifiers could be found in <dt-bindings/clock/marvell,mmp2.h>.
|
||||
@ -35,6 +35,8 @@ required:
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Clock controller node:
|
||||
- |
|
||||
|
||||
@ -68,6 +68,8 @@ required:
|
||||
- nvmem-cell-names
|
||||
- '#thermal-sensor-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@900000 {
|
||||
|
||||
@ -40,6 +40,8 @@ required:
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@1800000 {
|
||||
|
||||
@ -56,6 +56,8 @@ required:
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@300000 {
|
||||
|
||||
@ -66,6 +66,8 @@ required:
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
|
||||
@ -40,6 +40,8 @@ required:
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@1800000 {
|
||||
|
||||
@ -58,6 +58,8 @@ required:
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
|
||||
@ -56,6 +56,8 @@ required:
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
|
||||
72
Bindings/clock/qcom,gcc-sm8250.yaml
Normal file
72
Bindings/clock/qcom,gcc-sm8250.yaml
Normal file
@ -0,0 +1,72 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8250.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for SM8250
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on SM8250.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-sm8250.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-sm8250
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Sleep clock source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: sleep_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sm8250";
|
||||
reg = <0 0x00100000 0 0x1f0000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&sleep_clk>;
|
||||
clock-names = "bi_tcxo", "sleep_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@ -74,6 +74,8 @@ required:
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Example for GCC for MSM8960:
|
||||
- |
|
||||
|
||||
@ -74,6 +74,8 @@ required:
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@ -50,6 +50,8 @@ required:
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-msm8998.h>
|
||||
|
||||
@ -14,7 +14,9 @@ Required properties :
|
||||
"qcom,rpmcc-apq8060", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8916", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8974", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8976", "qcom,rpmcc"
|
||||
"qcom,rpmcc-apq8064", "qcom,rpmcc"
|
||||
"qcom,rpmcc-ipq806x", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8996", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8998", "qcom,rpmcc"
|
||||
"qcom,rpmcc-qcs404", "qcom,rpmcc"
|
||||
|
||||
@ -20,6 +20,7 @@ properties:
|
||||
- qcom,sc7180-rpmh-clk
|
||||
- qcom,sdm845-rpmh-clk
|
||||
- qcom,sm8150-rpmh-clk
|
||||
- qcom,sm8250-rpmh-clk
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
@ -35,6 +36,8 @@ required:
|
||||
- compatible
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Example for GCC for SDM845: The below node should be defined inside
|
||||
# &apps_rsc node.
|
||||
|
||||
@ -58,6 +58,8 @@ required:
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
|
||||
|
||||
@ -52,6 +52,8 @@ required:
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
|
||||
|
||||
62
Bindings/clock/qcom,sc7180-mss.yaml
Normal file
62
Bindings/clock/qcom,sc7180-mss.yaml
Normal file
@ -0,0 +1,62 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sc7180-mss.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Modem Clock Controller Binding for SC7180
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm modem clock control module which supports the clocks on SC7180.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,mss-sc7180.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sc7180-mss
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: gcc_mss_mfab_axi clock from GCC
|
||||
- description: gcc_mss_nav_axi clock from GCC
|
||||
- description: gcc_mss_cfg_ahb clock from GCC
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: gcc_mss_mfab_axis
|
||||
- const: gcc_mss_nav_axi
|
||||
- const: cfg_ahb
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
|
||||
clock-controller@41a8000 {
|
||||
compatible = "qcom,sc7180-mss";
|
||||
reg = <0 0x041a8000 0 0x8000>;
|
||||
clocks = <&gcc GCC_MSS_MFAB_AXIS_CLK>,
|
||||
<&gcc GCC_MSS_NAV_AXI_CLK>,
|
||||
<&gcc GCC_MSS_CFG_AHB_CLK>;
|
||||
clock-names = "gcc_mss_mfab_axis",
|
||||
"gcc_mss_nav_axi",
|
||||
"cfg_ahb";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
...
|
||||
@ -48,6 +48,8 @@ required:
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
|
||||
@ -67,6 +67,8 @@ required:
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
|
||||
|
||||
@ -52,6 +52,8 @@ required:
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
|
||||
|
||||
@ -48,6 +48,8 @@ required:
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
|
||||
@ -1,100 +0,0 @@
|
||||
* Renesas Clock Pulse Generator / Module Standby and Software Reset
|
||||
|
||||
On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
|
||||
and MSSR (Module Standby and Software Reset) blocks are intimately connected,
|
||||
and share the same register block.
|
||||
|
||||
They provide the following functionalities:
|
||||
- The CPG block generates various core clocks,
|
||||
- The MSSR block provides two functions:
|
||||
1. Module Standby, providing a Clock Domain to control the clock supply
|
||||
to individual SoC devices,
|
||||
2. Reset Control, to perform a software reset of individual SoC devices.
|
||||
|
||||
Required Properties:
|
||||
- compatible: Must be one of:
|
||||
- "renesas,r7s9210-cpg-mssr" for the r7s9210 SoC (RZ/A2)
|
||||
- "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)
|
||||
- "renesas,r8a7744-cpg-mssr" for the r8a7744 SoC (RZ/G1N)
|
||||
- "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)
|
||||
- "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C)
|
||||
- "renesas,r8a774a1-cpg-mssr" for the r8a774a1 SoC (RZ/G2M)
|
||||
- "renesas,r8a774b1-cpg-mssr" for the r8a774b1 SoC (RZ/G2N)
|
||||
- "renesas,r8a774c0-cpg-mssr" for the r8a774c0 SoC (RZ/G2E)
|
||||
- "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)
|
||||
- "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)
|
||||
- "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H)
|
||||
- "renesas,r8a7793-cpg-mssr" for the r8a7793 SoC (R-Car M2-N)
|
||||
- "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
|
||||
- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
|
||||
- "renesas,r8a7796-cpg-mssr" for the r8a77960 SoC (R-Car M3-W)
|
||||
- "renesas,r8a77961-cpg-mssr" for the r8a77961 SoC (R-Car M3-W+)
|
||||
- "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N)
|
||||
- "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
|
||||
- "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)
|
||||
- "renesas,r8a77990-cpg-mssr" for the r8a77990 SoC (R-Car E3)
|
||||
- "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
|
||||
|
||||
- reg: Base address and length of the memory resource used by the CPG/MSSR
|
||||
block
|
||||
|
||||
- clocks: References to external parent clocks, one entry for each entry in
|
||||
clock-names
|
||||
- clock-names: List of external parent clock names. Valid names are:
|
||||
- "extal" (r7s9210, r8a7743, r8a7744, r8a7745, r8a77470, r8a774a1,
|
||||
r8a774b1, r8a774c0, r8a7790, r8a7791, r8a7792, r8a7793,
|
||||
r8a7794, r8a7795, r8a77960, r8a77961, r8a77965, r8a77970,
|
||||
r8a77980, r8a77990, r8a77995)
|
||||
- "extalr" (r8a774a1, r8a774b1, r8a7795, r8a77960, r8a77961, r8a77965,
|
||||
r8a77970, r8a77980)
|
||||
- "usb_extal" (r8a7743, r8a7744, r8a7745, r8a77470, r8a7790, r8a7791,
|
||||
r8a7793, r8a7794)
|
||||
|
||||
- #clock-cells: Must be 2
|
||||
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
|
||||
and a core clock reference, as defined in
|
||||
<dt-bindings/clock/*-cpg-mssr.h>.
|
||||
- For module clocks, the two clock specifier cells must be "CPG_MOD" and
|
||||
a module number, as defined in the datasheet.
|
||||
|
||||
- #power-domain-cells: Must be 0
|
||||
- SoC devices that are part of the CPG/MSSR Clock Domain and can be
|
||||
power-managed through Module Standby should refer to the CPG device
|
||||
node in their "power-domains" property, as documented by the generic PM
|
||||
Domain bindings in
|
||||
Documentation/devicetree/bindings/power/power-domain.yaml.
|
||||
|
||||
- #reset-cells: Must be 1
|
||||
- The single reset specifier cell must be the module number, as defined
|
||||
in the datasheet.
|
||||
|
||||
|
||||
Examples
|
||||
--------
|
||||
|
||||
- CPG device node:
|
||||
|
||||
cpg: clock-controller@e6150000 {
|
||||
compatible = "renesas,r8a7795-cpg-mssr";
|
||||
reg = <0 0xe6150000 0 0x1000>;
|
||||
clocks = <&extal_clk>, <&extalr_clk>;
|
||||
clock-names = "extal", "extalr";
|
||||
#clock-cells = <2>;
|
||||
#power-domain-cells = <0>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
|
||||
- CPG/MSSR Clock Domain member device node:
|
||||
|
||||
scif2: serial@e6e88000 {
|
||||
compatible = "renesas,scif-r8a7795", "renesas,scif";
|
||||
reg = <0 0xe6e88000 0 64>;
|
||||
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 310>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x13>, <&dmac1 0x12>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg>;
|
||||
resets = <&cpg 310>;
|
||||
};
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user