Add support for type1 pci configuration cycles for cia (not pyxis yet).
Submitted by: Andrew Gallatin <gallatin@cs.duke.edu>
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=38158
@ -23,7 +23,7 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: cia.c,v 1.3 1998/07/22 08:32:17 dfr Exp $
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* $Id: cia.c,v 1.4 1998/07/31 09:17:51 dfr Exp $
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*/
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#include <sys/param.h>
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@ -387,61 +387,96 @@ cia_swiz_maxdevs(u_int b)
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#define CIA_SWIZ_CFGOFF(b, s, f, r) \
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(((b) << 16) | ((s) << 11) | ((f) << 8) | (r))
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/* when doing a type 1 pci configuration space access, we
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* must set a bit in the CIA_CSR_CFG register & clear it
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* when we're done
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*/
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#define CIA_TYPE1_SETUP(b,s,old_cfg) if((b)) { \
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do { \
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(s) = splhigh(); \
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(old_cfg) = REGVAL(CIA_CSR_CFG); \
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alpha_mb(); \
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REGVAL(CIA_CSR_CFG) = (old_cfg) | 0x1; \
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alpha_mb(); \
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} while(0); \
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}
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#define CIA_TYPE1_TEARDOWN(b,s,old_cfg) if((b)) { \
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do { \
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alpha_mb(); \
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REGVAL(CIA_CSR_CFG) = (old_cfg); \
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alpha_mb(); \
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splx((s)); \
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} while(0); \
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}
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#define SWIZ_CFGREAD(b, s, f, r, width, type) \
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type val = ~0; \
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int ipl = 0; \
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u_int32_t old_cfg = 0; \
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struct cia_softc* sc = CIA_SOFTC(cia0); \
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vm_offset_t off = CIA_SWIZ_CFGOFF(b, s, f, r); \
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vm_offset_t kv = SPARSE_##width##_ADDRESS(sc->cfg0_base, off); \
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alpha_mb(); \
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CIA_TYPE1_SETUP(b,ipl,old_cfg); \
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if (!badaddr((caddr_t)kv, sizeof(type))) { \
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val = SPARSE_##width##_EXTRACT(off, SPARSE_READ(kv)); \
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} \
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CIA_TYPE1_TEARDOWN(b,ipl,old_cfg); \
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return val;
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#define SWIZ_CFGWRITE(b, s, f, r, data, width, type) \
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int ipl = 0; \
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u_int32_t old_cfg = 0; \
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struct cia_softc* sc = CIA_SOFTC(cia0); \
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vm_offset_t off = CIA_SWIZ_CFGOFF(b, s, f, r); \
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vm_offset_t kv = SPARSE_##width##_ADDRESS(sc->cfg0_base, off); \
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alpha_mb(); \
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CIA_TYPE1_SETUP(b,ipl,old_cfg); \
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if (!badaddr((caddr_t)kv, sizeof(type))) { \
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SPARSE_WRITE(kv, SPARSE_##width##_INSERT(off, data)); \
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alpha_wmb(); \
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} \
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CIA_TYPE1_TEARDOWN(b,ipl,old_cfg); \
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return;
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static u_int8_t
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cia_swiz_cfgreadb(u_int b, u_int s, u_int f, u_int r)
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{
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vm_offset_t off = CIA_SWIZ_CFGOFF(b, s, f, r);
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alpha_mb();
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if (badaddr((caddr_t)(KV(CIA_PCI_CONF) + SPARSE_BYTE_OFFSET(off)), 1)) return ~0;
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return SPARSE_READ_BYTE(KV(CIA_PCI_CONF), off);
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SWIZ_CFGREAD(b, s, f, r, BYTE, u_int8_t);
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}
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static u_int16_t
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cia_swiz_cfgreadw(u_int b, u_int s, u_int f, u_int r)
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{
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vm_offset_t off = CIA_SWIZ_CFGOFF(b, s, f, r);
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alpha_mb();
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if (badaddr((caddr_t)(KV(CIA_PCI_CONF) + SPARSE_WORD_OFFSET(off)), 2)) return ~0;
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return SPARSE_READ_WORD(KV(CIA_PCI_CONF), off);
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SWIZ_CFGREAD(b, s, f, r, WORD, u_int16_t);
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}
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static u_int32_t
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cia_swiz_cfgreadl(u_int b, u_int s, u_int f, u_int r)
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{
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vm_offset_t off = CIA_SWIZ_CFGOFF(b, s, f, r);
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alpha_mb();
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if (badaddr((caddr_t)(KV(CIA_PCI_CONF) + SPARSE_LONG_OFFSET(off)), 4)) return ~0;
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return SPARSE_READ_LONG(KV(CIA_PCI_CONF), off);
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SWIZ_CFGREAD(b, s, f, r, LONG, u_int32_t);
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}
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static void
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cia_swiz_cfgwriteb(u_int b, u_int s, u_int f, u_int r, u_int8_t data)
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{
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vm_offset_t off = CIA_SWIZ_CFGOFF(b, s, f, r);
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if (badaddr((caddr_t)(KV(CIA_PCI_CONF) + SPARSE_BYTE_OFFSET(off)), 1)) return;
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SPARSE_WRITE_BYTE(KV(CIA_PCI_CONF), off, data);
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alpha_wmb();
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SWIZ_CFGWRITE(b, s, f, r, data, BYTE, u_int8_t);
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}
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static void
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cia_swiz_cfgwritew(u_int b, u_int s, u_int f, u_int r, u_int16_t data)
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{
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vm_offset_t off = CIA_SWIZ_CFGOFF(b, s, f, r);
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if (badaddr((caddr_t)(KV(CIA_PCI_CONF) + SPARSE_WORD_OFFSET(off)), 2)) return;
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SPARSE_WRITE_WORD(KV(CIA_PCI_CONF), off, data);
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alpha_wmb();
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SWIZ_CFGWRITE(b, s, f, r, data, WORD, u_int16_t);
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}
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static void
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cia_swiz_cfgwritel(u_int b, u_int s, u_int f, u_int r, u_int32_t data)
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{
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vm_offset_t off = CIA_SWIZ_CFGOFF(b, s, f, r);
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if (badaddr((caddr_t)(KV(CIA_PCI_CONF) + SPARSE_LONG_OFFSET(off)), 4)) return;
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SPARSE_WRITE_LONG(KV(CIA_PCI_CONF), off, data);
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alpha_wmb();
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SWIZ_CFGWRITE(b, s, f, r, data, LONG, u_int32_t);
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}
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static int cia_probe(device_t dev);
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static int cia_attach(device_t dev);
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static void *cia_create_intr(device_t dev, device_t child, int irq, driver_intr_t *intr, void *arg);
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