593 lines
14 KiB
C
593 lines
14 KiB
C
/*-
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* Copyright (c) 1998 Doug Rabson
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: cia.c,v 1.4 1998/07/31 09:17:51 dfr Exp $
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <alpha/pci/ciareg.h>
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#include <alpha/pci/ciavar.h>
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#include <machine/bwx.h>
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#include <machine/swiz.h>
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#include <machine/intr.h>
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#include <machine/cpuconf.h>
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#define KV(pa) ALPHA_PHYS_TO_K0SEG(pa)
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static devclass_t cia_devclass;
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static device_t cia0; /* XXX only one for now */
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static u_int32_t cia_hae_mem;
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extern void eb164_intr_enable(int irq);
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extern void eb164_intr_disable(int irq);
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static void cia_intr(void* frame, u_long vector);
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struct cia_softc {
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vm_offset_t dmem_base; /* dense memory */
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vm_offset_t smem_base; /* sparse memory */
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vm_offset_t io_base; /* dense i/o */
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vm_offset_t cfg0_base; /* dense pci0 config */
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vm_offset_t cfg1_base; /* dense pci1 config */
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};
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#define CIA_SOFTC(dev) (struct cia_softc*) device_get_softc(dev)
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static alpha_chipset_inb_t cia_bwx_inb, cia_swiz_inb;
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static alpha_chipset_inw_t cia_bwx_inw, cia_swiz_inw;
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static alpha_chipset_inl_t cia_bwx_inl, cia_swiz_inl;
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static alpha_chipset_outb_t cia_bwx_outb, cia_swiz_outb;
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static alpha_chipset_outw_t cia_bwx_outw, cia_swiz_outw;
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static alpha_chipset_outl_t cia_bwx_outl, cia_swiz_outl;
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static alpha_chipset_readb_t cia_bwx_readb, cia_swiz_readb;
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static alpha_chipset_readw_t cia_bwx_readw, cia_swiz_readw;
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static alpha_chipset_readl_t cia_bwx_readl, cia_swiz_readl;
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static alpha_chipset_writeb_t cia_bwx_writeb, cia_swiz_writeb;
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static alpha_chipset_writew_t cia_bwx_writew, cia_swiz_writew;
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static alpha_chipset_writel_t cia_bwx_writel, cia_swiz_writel;
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static alpha_chipset_maxdevs_t cia_bwx_maxdevs, cia_swiz_maxdevs;
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static alpha_chipset_cfgreadb_t cia_bwx_cfgreadb, cia_swiz_cfgreadb;
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static alpha_chipset_cfgreadw_t cia_bwx_cfgreadw, cia_swiz_cfgreadw;
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static alpha_chipset_cfgreadl_t cia_bwx_cfgreadl, cia_swiz_cfgreadl;
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static alpha_chipset_cfgwriteb_t cia_bwx_cfgwriteb, cia_swiz_cfgwriteb;
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static alpha_chipset_cfgwritew_t cia_bwx_cfgwritew, cia_swiz_cfgwritew;
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static alpha_chipset_cfgwritel_t cia_bwx_cfgwritel, cia_swiz_cfgwritel;
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static alpha_chipset_t cia_bwx_chipset = {
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cia_bwx_inb,
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cia_bwx_inw,
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cia_bwx_inl,
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cia_bwx_outb,
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cia_bwx_outw,
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cia_bwx_outl,
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cia_bwx_readb,
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cia_bwx_readw,
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cia_bwx_readl,
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cia_bwx_writeb,
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cia_bwx_writew,
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cia_bwx_writel,
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cia_bwx_maxdevs,
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cia_bwx_cfgreadb,
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cia_bwx_cfgreadw,
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cia_bwx_cfgreadl,
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cia_bwx_cfgwriteb,
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cia_bwx_cfgwritew,
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cia_bwx_cfgwritel,
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};
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static alpha_chipset_t cia_swiz_chipset = {
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cia_swiz_inb,
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cia_swiz_inw,
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cia_swiz_inl,
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cia_swiz_outb,
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cia_swiz_outw,
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cia_swiz_outl,
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cia_swiz_readb,
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cia_swiz_readw,
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cia_swiz_readl,
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cia_swiz_writeb,
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cia_swiz_writew,
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cia_swiz_writel,
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cia_swiz_maxdevs,
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cia_swiz_cfgreadb,
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cia_swiz_cfgreadw,
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cia_swiz_cfgreadl,
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cia_swiz_cfgwriteb,
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cia_swiz_cfgwritew,
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cia_swiz_cfgwritel,
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};
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static u_int8_t
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cia_bwx_inb(u_int32_t port)
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{
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alpha_mb();
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return ldbu(KV(CIA_EV56_BWIO+BWX_EV56_INT1 + port));
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}
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static u_int16_t
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cia_bwx_inw(u_int32_t port)
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{
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alpha_mb();
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return ldwu(KV(CIA_EV56_BWIO+BWX_EV56_INT2 + port));
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}
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static u_int32_t
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cia_bwx_inl(u_int32_t port)
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{
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alpha_mb();
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return ldl(KV(CIA_EV56_BWIO+BWX_EV56_INT4 + port));
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}
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static void
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cia_bwx_outb(u_int32_t port, u_int8_t data)
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{
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stb(KV(CIA_EV56_BWIO+BWX_EV56_INT1 + port), data);
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alpha_wmb();
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}
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static void
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cia_bwx_outw(u_int32_t port, u_int16_t data)
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{
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stw(KV(CIA_EV56_BWIO+BWX_EV56_INT2 + port), data);
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alpha_wmb();
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}
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static void
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cia_bwx_outl(u_int32_t port, u_int32_t data)
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{
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stl(KV(CIA_EV56_BWIO+BWX_EV56_INT4 + port), data);
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alpha_wmb();
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}
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static u_int8_t
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cia_bwx_readb(u_int32_t pa)
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{
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alpha_mb();
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return ldbu(KV(CIA_EV56_BWMEM+BWX_EV56_INT1 + pa));
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}
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static u_int16_t
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cia_bwx_readw(u_int32_t pa)
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{
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alpha_mb();
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return ldwu(KV(CIA_EV56_BWMEM+BWX_EV56_INT2 + pa));
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}
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static u_int32_t
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cia_bwx_readl(u_int32_t pa)
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{
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alpha_mb();
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return ldl(KV(CIA_EV56_BWMEM+BWX_EV56_INT4 + pa));
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}
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static void
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cia_bwx_writeb(u_int32_t pa, u_int8_t data)
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{
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stb(KV(CIA_EV56_BWMEM+BWX_EV56_INT1 + pa), data);
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alpha_wmb();
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}
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static void
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cia_bwx_writew(u_int32_t pa, u_int16_t data)
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{
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stw(KV(CIA_EV56_BWMEM+BWX_EV56_INT2 + pa), data);
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alpha_wmb();
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}
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static void
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cia_bwx_writel(u_int32_t pa, u_int32_t data)
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{
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stl(KV(CIA_EV56_BWMEM+BWX_EV56_INT4 + pa), data);
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alpha_wmb();
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}
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static int
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cia_bwx_maxdevs(u_int b)
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{
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return 12; /* XXX */
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}
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#define CIA_BWX_CFGADDR(b, s, f, r) \
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KV(((b) ? CIA_EV56_BWCONF1 : CIA_EV56_BWCONF0) \
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| ((b) << 16) | ((s) << 11) | ((f) << 8) | (r))
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static u_int8_t
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cia_bwx_cfgreadb(u_int b, u_int s, u_int f, u_int r)
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{
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vm_offset_t va = CIA_BWX_CFGADDR(b, s, f, r);
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alpha_mb();
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if (badaddr((caddr_t)va, 1)) return ~0;
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return ldbu(va+BWX_EV56_INT1);
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}
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static u_int16_t
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cia_bwx_cfgreadw(u_int b, u_int s, u_int f, u_int r)
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{
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vm_offset_t va = CIA_BWX_CFGADDR(b, s, f, r);
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alpha_mb();
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if (badaddr((caddr_t)va, 2)) return ~0;
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return ldwu(va+BWX_EV56_INT2);
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}
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static u_int32_t
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cia_bwx_cfgreadl(u_int b, u_int s, u_int f, u_int r)
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{
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vm_offset_t va = CIA_BWX_CFGADDR(b, s, f, r);
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alpha_mb();
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if (badaddr((caddr_t)va, 4)) return ~0;
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return ldl(va+BWX_EV56_INT4);
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}
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static void
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cia_bwx_cfgwriteb(u_int b, u_int s, u_int f, u_int r, u_int8_t data)
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{
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vm_offset_t va = CIA_BWX_CFGADDR(b, s, f, r);
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if (badaddr((caddr_t)va, 1)) return;
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stb(va+BWX_EV56_INT1, data);
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alpha_wmb();
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}
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static void
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cia_bwx_cfgwritew(u_int b, u_int s, u_int f, u_int r, u_int16_t data)
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{
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vm_offset_t va = CIA_BWX_CFGADDR(b, s, f, r);
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if (badaddr((caddr_t)va, 2)) return;
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stw(va+BWX_EV56_INT2, data);
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alpha_wmb();
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}
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static void
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cia_bwx_cfgwritel(u_int b, u_int s, u_int f, u_int r, u_int32_t data)
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{
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vm_offset_t va = CIA_BWX_CFGADDR(b, s, f, r);
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if (badaddr((caddr_t)va, 4)) return;
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stl(va+BWX_EV56_INT4, data);
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alpha_wmb();
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}
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static u_int8_t
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cia_swiz_inb(u_int32_t port)
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{
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alpha_mb();
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return SPARSE_READ_BYTE(KV(CIA_PCI_SIO1), port);
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}
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static u_int16_t
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cia_swiz_inw(u_int32_t port)
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{
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alpha_mb();
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return SPARSE_READ_WORD(KV(CIA_PCI_SIO1), port);
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}
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static u_int32_t
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cia_swiz_inl(u_int32_t port)
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{
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alpha_mb();
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return SPARSE_READ_LONG(KV(CIA_PCI_SIO1), port);
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}
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static void
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cia_swiz_outb(u_int32_t port, u_int8_t data)
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{
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SPARSE_WRITE_BYTE(KV(CIA_PCI_SIO1), port, data);
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alpha_wmb();
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}
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static void
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cia_swiz_outw(u_int32_t port, u_int16_t data)
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{
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SPARSE_WRITE_WORD(KV(CIA_PCI_SIO1), port, data);
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alpha_wmb();
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}
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static void
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cia_swiz_outl(u_int32_t port, u_int32_t data)
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{
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SPARSE_WRITE_LONG(KV(CIA_PCI_SIO1), port, data);
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alpha_wmb();
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}
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static __inline void
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cia_swiz_set_hae_mem(u_int32_t pa)
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{
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/* Only bother with region 1 */
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#define REG1 (7 << 29)
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if ((cia_hae_mem & REG1) != (pa & REG1)) {
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/*
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* Seems fairly paranoid but this is what Linux does...
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*/
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int s = splhigh();
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cia_hae_mem = (cia_hae_mem & ~REG1) | (pa & REG1);
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REGVAL(CIA_CSR_HAE_MEM) = cia_hae_mem;
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alpha_mb();
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cia_hae_mem = REGVAL(CIA_CSR_HAE_MEM);
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splx(s);
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}
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}
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static u_int8_t
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cia_swiz_readb(u_int32_t pa)
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{
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alpha_mb();
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cia_swiz_set_hae_mem(pa);
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return SPARSE_READ_BYTE(KV(CIA_PCI_SMEM1), pa);
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}
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static u_int16_t
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cia_swiz_readw(u_int32_t pa)
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{
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alpha_mb();
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cia_swiz_set_hae_mem(pa);
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return SPARSE_READ_WORD(KV(CIA_PCI_SMEM1), pa);
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}
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static u_int32_t
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cia_swiz_readl(u_int32_t pa)
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{
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alpha_mb();
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cia_swiz_set_hae_mem(pa);
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return SPARSE_READ_LONG(KV(CIA_PCI_SMEM1), pa);
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}
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static void
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cia_swiz_writeb(u_int32_t pa, u_int8_t data)
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{
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cia_swiz_set_hae_mem(pa);
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SPARSE_WRITE_BYTE(KV(CIA_PCI_SMEM1), pa, data);
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alpha_wmb();
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}
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static void
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cia_swiz_writew(u_int32_t pa, u_int16_t data)
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{
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cia_swiz_set_hae_mem(pa);
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SPARSE_WRITE_WORD(KV(CIA_PCI_SMEM1), pa, data);
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alpha_wmb();
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}
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static void
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cia_swiz_writel(u_int32_t pa, u_int32_t data)
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{
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cia_swiz_set_hae_mem(pa);
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SPARSE_WRITE_LONG(KV(CIA_PCI_SMEM1), pa, data);
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alpha_wmb();
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}
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static int
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cia_swiz_maxdevs(u_int b)
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{
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return 12; /* XXX */
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}
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#define CIA_SWIZ_CFGOFF(b, s, f, r) \
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(((b) << 16) | ((s) << 11) | ((f) << 8) | (r))
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/* when doing a type 1 pci configuration space access, we
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* must set a bit in the CIA_CSR_CFG register & clear it
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* when we're done
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*/
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#define CIA_TYPE1_SETUP(b,s,old_cfg) if((b)) { \
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do { \
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(s) = splhigh(); \
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(old_cfg) = REGVAL(CIA_CSR_CFG); \
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alpha_mb(); \
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REGVAL(CIA_CSR_CFG) = (old_cfg) | 0x1; \
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alpha_mb(); \
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} while(0); \
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}
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#define CIA_TYPE1_TEARDOWN(b,s,old_cfg) if((b)) { \
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do { \
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alpha_mb(); \
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REGVAL(CIA_CSR_CFG) = (old_cfg); \
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alpha_mb(); \
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splx((s)); \
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} while(0); \
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}
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#define SWIZ_CFGREAD(b, s, f, r, width, type) \
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type val = ~0; \
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int ipl = 0; \
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u_int32_t old_cfg = 0; \
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struct cia_softc* sc = CIA_SOFTC(cia0); \
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vm_offset_t off = CIA_SWIZ_CFGOFF(b, s, f, r); \
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vm_offset_t kv = SPARSE_##width##_ADDRESS(sc->cfg0_base, off); \
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alpha_mb(); \
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CIA_TYPE1_SETUP(b,ipl,old_cfg); \
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if (!badaddr((caddr_t)kv, sizeof(type))) { \
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val = SPARSE_##width##_EXTRACT(off, SPARSE_READ(kv)); \
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} \
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CIA_TYPE1_TEARDOWN(b,ipl,old_cfg); \
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return val;
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#define SWIZ_CFGWRITE(b, s, f, r, data, width, type) \
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int ipl = 0; \
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u_int32_t old_cfg = 0; \
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struct cia_softc* sc = CIA_SOFTC(cia0); \
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vm_offset_t off = CIA_SWIZ_CFGOFF(b, s, f, r); \
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vm_offset_t kv = SPARSE_##width##_ADDRESS(sc->cfg0_base, off); \
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alpha_mb(); \
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CIA_TYPE1_SETUP(b,ipl,old_cfg); \
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if (!badaddr((caddr_t)kv, sizeof(type))) { \
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SPARSE_WRITE(kv, SPARSE_##width##_INSERT(off, data)); \
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alpha_wmb(); \
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} \
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CIA_TYPE1_TEARDOWN(b,ipl,old_cfg); \
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return;
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static u_int8_t
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cia_swiz_cfgreadb(u_int b, u_int s, u_int f, u_int r)
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{
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SWIZ_CFGREAD(b, s, f, r, BYTE, u_int8_t);
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}
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static u_int16_t
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cia_swiz_cfgreadw(u_int b, u_int s, u_int f, u_int r)
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{
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SWIZ_CFGREAD(b, s, f, r, WORD, u_int16_t);
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}
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static u_int32_t
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cia_swiz_cfgreadl(u_int b, u_int s, u_int f, u_int r)
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{
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SWIZ_CFGREAD(b, s, f, r, LONG, u_int32_t);
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}
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static void
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cia_swiz_cfgwriteb(u_int b, u_int s, u_int f, u_int r, u_int8_t data)
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{
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SWIZ_CFGWRITE(b, s, f, r, data, BYTE, u_int8_t);
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}
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static void
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cia_swiz_cfgwritew(u_int b, u_int s, u_int f, u_int r, u_int16_t data)
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{
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SWIZ_CFGWRITE(b, s, f, r, data, WORD, u_int16_t);
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}
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static void
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cia_swiz_cfgwritel(u_int b, u_int s, u_int f, u_int r, u_int32_t data)
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{
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SWIZ_CFGWRITE(b, s, f, r, data, LONG, u_int32_t);
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}
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static int cia_probe(device_t dev);
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static int cia_attach(device_t dev);
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static void *cia_create_intr(device_t dev, device_t child, int irq, driver_intr_t *intr, void *arg);
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static int cia_connect_intr(device_t dev, void* ih);
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static device_method_t cia_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, cia_probe),
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DEVMETHOD(device_attach, cia_attach),
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/* Bus interface */
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DEVMETHOD(bus_create_intr, cia_create_intr),
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DEVMETHOD(bus_connect_intr, cia_connect_intr),
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{ 0, 0 }
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};
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static driver_t cia_driver = {
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"cia",
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cia_methods,
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DRIVER_TYPE_MISC,
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sizeof(struct cia_softc),
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};
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|
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void
|
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cia_init()
|
|
{
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static int initted = 0;
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if (initted) return;
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initted = 1;
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|
|
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if (alpha_implver() != ALPHA_IMPLVER_EV5
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|| alpha_amask(ALPHA_AMASK_BWX))
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chipset = cia_swiz_chipset;
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else
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chipset = cia_bwx_chipset;
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cia_hae_mem = REGVAL(CIA_CSR_HAE_MEM);
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}
|
|
|
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static int
|
|
cia_probe(device_t dev)
|
|
{
|
|
if (cia0)
|
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return ENXIO;
|
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cia0 = dev;
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device_set_desc(dev, "2117x PCI adapter"); /* XXX */
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|
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device_add_child(dev, "isa", 0, 0);
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return 0;
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}
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|
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static int
|
|
cia_attach(device_t dev)
|
|
{
|
|
struct cia_softc* sc = CIA_SOFTC(dev);
|
|
|
|
cia_init();
|
|
chipset.bridge = dev;
|
|
|
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if (alpha_amask(ALPHA_AMASK_BWX) == 0) {
|
|
sc->dmem_base = CIA_EV56_BWMEM;
|
|
sc->smem_base = CIA_PCI_SMEM1;
|
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sc->io_base = CIA_EV56_BWIO;
|
|
sc->cfg0_base = CIA_EV56_BWCONF0;
|
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sc->cfg1_base = CIA_EV56_BWCONF1;
|
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} else {
|
|
sc->dmem_base = CIA_PCI_DENSE;
|
|
sc->smem_base = CIA_PCI_SMEM1;
|
|
sc->io_base = CIA_PCI_SIO1;
|
|
sc->cfg0_base = KV(CIA_PCI_CONF);
|
|
sc->cfg1_base = NULL;
|
|
}
|
|
set_iointr(cia_intr);
|
|
|
|
bus_generic_attach(dev);
|
|
return 0;
|
|
}
|
|
|
|
static void *
|
|
cia_create_intr(device_t dev, device_t child,
|
|
int irq, driver_intr_t *intr, void *arg)
|
|
{
|
|
return alpha_create_intr(irq, intr, arg);
|
|
}
|
|
|
|
static int
|
|
cia_connect_intr(device_t dev, void* ih)
|
|
{
|
|
struct alpha_intr *i = ih;
|
|
int s = splhigh();
|
|
int error = alpha_connect_intr(i);
|
|
if (!error) {
|
|
if (i->vector > 0x900)
|
|
/* PCI interrupt */
|
|
platform.pci_intr_enable((i->vector - 0x900) >> 4);
|
|
else if (i->vector > 0x800)
|
|
/* ISA interrupt chained to PCI interrupt 4 */
|
|
platform.pci_intr_enable(4);/* XXX */
|
|
}
|
|
splx(s);
|
|
return error;
|
|
}
|
|
|
|
static void
|
|
cia_intr(void* frame, u_long vector)
|
|
{
|
|
alpha_dispatch_intr(vector);
|
|
}
|
|
|
|
DRIVER_MODULE(cia, root, cia_driver, cia_devclass, 0, 0);
|
|
|