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Import device-tree files from Linux 5.13

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This commit is contained in:
Emmanuel Vadot 2021-07-01 17:50:17 +02:00
parent c7a3c7298f
commit 71ca10f8bb
939 changed files with 49866 additions and 4467 deletions
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4
Bindings/.gitignore vendored
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@ -1,4 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
*.example.dts
processed-schema*.yaml
processed-schema*.json
/processed-schema*.yaml
/processed-schema*.json

7
Bindings/Makefile
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@ -5,7 +5,7 @@ DT_MK_SCHEMA ?= dt-mk-schema
DT_SCHEMA_LINT = $(shell which yamllint)
DT_SCHEMA_MIN_VERSION = 2020.8.1
DT_SCHEMA_MIN_VERSION = 2021.2.1
PHONY += check_dtschema_version
check_dtschema_version:
@ -48,13 +48,16 @@ define rule_chkdt
$(call cmd,mk_schema)
endef
DT_DOCS = $(shell $(find_cmd) | sed -e 's|^$(srctree)/||')
DT_DOCS = $(patsubst $(srctree)/%,%,$(shell $(find_cmd)))
override DTC_FLAGS := \
-Wno-avoid_unnecessary_addr_size \
-Wno-graph_child_address \
-Wno-interrupt_provider
# Disable undocumented compatible checks until warning free
override DT_CHECKER_FLAGS ?=
$(obj)/processed-schema-examples.json: $(DT_DOCS) $(src)/.yamllint check_dtschema_version FORCE
$(call if_changed_rule,chkdt)

3
Bindings/arm/amlogic.yaml
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@ -109,6 +109,7 @@ properties:
- libretech,aml-s905d-pc
- phicomm,n1
- smartlabs,sml5442tw
- videostrong,gxl-kii-pro
- const: amlogic,s905d
- const: amlogic,meson-gxl
@ -120,8 +121,10 @@ properties:
- khadas,vim2
- kingnovel,r-box-pro
- libretech,aml-s912-pc
- minix,neo-u9h
- nexbox,a1
- tronsmart,vega-s96
- videostrong,gxm-kiii-pro
- wetek,core2
- const: amlogic,s912
- const: amlogic,meson-gxm

64
Bindings/arm/apple.yaml Normal file
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@ -0,0 +1,64 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/apple.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Apple ARM Machine Device Tree Bindings
maintainers:
- Hector Martin <marcan@marcan.st>
description: |
ARM platforms using SoCs designed by Apple Inc., branded "Apple Silicon".
This currently includes devices based on the "M1" SoC, starting with the
three Mac models released in late 2020:
- Mac mini (M1, 2020)
- MacBook Pro (13-inch, M1, 2020)
- MacBook Air (M1, 2020)
The compatible property should follow this format:
compatible = "apple,<targettype>", "apple,<socid>", "apple,arm-platform";
<targettype> represents the board/device and comes from the `target-type`
property of the root node of the Apple Device Tree, lowercased. It can be
queried on macOS using the following command:
$ ioreg -d2 -l | grep target-type
<socid> is the lowercased SoC ID. Apple uses at least *five* different
names for their SoCs:
- Marketing name ("M1")
- Internal name ("H13G")
- Codename ("Tonga")
- SoC ID ("T8103")
- Package/IC part number ("APL1102")
Devicetrees should use the lowercased SoC ID, to avoid confusion if
multiple SoCs share the same marketing name. This can be obtained from
the `compatible` property of the arm-io node of the Apple Device Tree,
which can be queried as follows on macOS:
$ ioreg -n arm-io | grep compatible
properties:
$nodename:
const: "/"
compatible:
oneOf:
- description: Apple M1 SoC based platforms
items:
- enum:
- apple,j274 # Mac mini (M1, 2020)
- apple,j293 # MacBook Pro (13-inch, M1, 2020)
- apple,j313 # MacBook Air (M1, 2020)
- const: apple,t8103
- const: apple,arm-platform
additionalProperties: true
...

1
Bindings/arm/bcm/brcm,bcm4908.yaml
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@ -21,6 +21,7 @@ properties:
items:
- enum:
- netgear,r8000p
- tplink,archer-c2300-v1
- const: brcm,bcm4906
- const: brcm,bcm4908

25
Bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml
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@ -26,10 +26,7 @@ properties:
- const: simple-mfd
mboxes:
$ref: '/schemas/types.yaml#/definitions/phandle'
description: |
Phandle to the firmware device's Mailbox.
(See: ../mailbox/mailbox.txt for more information)
maxItems: 1
clocks:
type: object
@ -64,6 +61,21 @@ properties:
- compatible
- "#reset-cells"
pwm:
type: object
properties:
compatible:
const: raspberrypi,firmware-poe-pwm
"#pwm-cells":
# See pwm.yaml in this directory for a description of the cells format.
const: 2
required:
- compatible
- "#pwm-cells"
additionalProperties: false
required:
@ -87,5 +99,10 @@ examples:
compatible = "raspberrypi,firmware-reset";
#reset-cells = <1>;
};
pwm: pwm {
compatible = "raspberrypi,firmware-poe-pwm";
#pwm-cells = <2>;
};
};
...

4
Bindings/arm/cpus.yaml
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@ -85,6 +85,8 @@ properties:
compatible:
enum:
- apple,icestorm
- apple,firestorm
- arm,arm710t
- arm,arm720t
- arm,arm740t
@ -256,13 +258,11 @@ properties:
where voltage is in V, frequency is in MHz.
power-domains:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
description:
List of phandles and PM domain specifiers, as defined by bindings of the
PM domain provider (see also ../power_domain.txt).
power-domain-names:
$ref: '/schemas/types.yaml#/definitions/string-array'
description:
A list of power domain name strings sorted in the same order as the
power-domains property.

75
Bindings/arm/ete.yaml Normal file
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@ -0,0 +1,75 @@
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
# Copyright 2021, Arm Ltd
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/ete.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: ARM Embedded Trace Extensions
maintainers:
- Suzuki K Poulose <suzuki.poulose@arm.com>
- Mathieu Poirier <mathieu.poirier@linaro.org>
description: |
Arm Embedded Trace Extension(ETE) is a per CPU trace component that
allows tracing the CPU execution. It overlaps with the CoreSight ETMv4
architecture and has extended support for future architecture changes.
The trace generated by the ETE could be stored via legacy CoreSight
components (e.g, TMC-ETR) or other means (e.g, using a per CPU buffer
Arm Trace Buffer Extension (TRBE)). Since the ETE can be connected to
legacy CoreSight components, a node must be listed per instance, along
with any optional connection graph as per the coresight bindings.
See bindings/arm/coresight.txt.
properties:
$nodename:
pattern: "^ete([0-9a-f]+)$"
compatible:
items:
- const: arm,embedded-trace-extension
cpu:
description: |
Handle to the cpu this ETE is bound to.
$ref: /schemas/types.yaml#/definitions/phandle
out-ports:
description: |
Output connections from the ETE to legacy CoreSight trace bus.
$ref: /schemas/graph.yaml#/properties/ports
properties:
port:
description: Output connection from the ETE to legacy CoreSight Trace bus.
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- cpu
additionalProperties: false
examples:
# An ETE node without legacy CoreSight connections
- |
ete0 {
compatible = "arm,embedded-trace-extension";
cpu = <&cpu_0>;
};
# An ETE node with legacy CoreSight connections
- |
ete1 {
compatible = "arm,embedded-trace-extension";
cpu = <&cpu_1>;
out-ports { /* legacy coresight connection */
port {
ete1_out_port: endpoint {
remote-endpoint = <&funnel_in_port0>;
};
};
};
};
...

16
Bindings/arm/fsl.yaml
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@ -617,6 +617,7 @@ properties:
- kam,imx7d-flex-concentrator # Kamstrup OMNIA Flex Concentrator
- kam,imx7d-flex-concentrator-mfg # Kamstrup OMNIA Flex Concentrator in manufacturing mode
- novtech,imx7d-meerkat96 # i.MX7 Meerkat96 Board
- remarkable,imx7d-remarkable2 # i.MX7D ReMarkable 2 E-Ink Tablet
- technexion,imx7d-pico-dwarf # TechNexion i.MX7D Pico-Dwarf
- technexion,imx7d-pico-hobbit # TechNexion i.MX7D Pico-Hobbit
- technexion,imx7d-pico-nymph # TechNexion i.MX7D Pico-Nymph
@ -688,6 +689,14 @@ properties:
- variscite,var-som-mx8mm # i.MX8MM Variscite VAR-SOM-MX8MM module
- const: fsl,imx8mm
- description: Engicam i.Core MX8M Mini SoM based boards
items:
- enum:
- engicam,icore-mx8mm-ctouch2 # i.MX8MM Engicam i.Core MX8M Mini C.TOUCH 2.0
- engicam,icore-mx8mm-edimm2.2 # i.MX8MM Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit
- const: engicam,icore-mx8mm # i.MX8MM Engicam i.Core MX8M Mini SoM
- const: fsl,imx8mm
- description: Kontron BL i.MX8MM (N801X S) Board
items:
- const: kontron,imx8mm-n801x-s
@ -733,6 +742,7 @@ properties:
- einfochips,imx8mq-thor96 # i.MX8MQ Thor96 Board
- fsl,imx8mq-evk # i.MX8MQ EVK Board
- google,imx8mq-phanbell # Google Coral Edge TPU
- kontron,pitx-imx8m # Kontron pITX-imx8m Board
- purism,librem5-devkit # Purism Librem5 devkit
- solidrun,hummingboard-pulse # SolidRun Hummingboard Pulse
- technexion,pico-pi-imx8m # TechNexion PICO-PI-8M evk
@ -755,6 +765,12 @@ properties:
- const: zii,imx8mq-ultra
- const: fsl,imx8mq
- description: i.MX8QM based Boards
items:
- enum:
- fsl,imx8qm-mek # i.MX8QM MEK Board
- const: fsl,imx8qm
- description: i.MX8QXP based Boards
items:
- enum:

4
Bindings/arm/marvell/cp110-system-controller.txt
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@ -142,8 +142,8 @@ mpp50 50 gpio, ge1(rxclk), mss_i2c(sda), spi1(csn0), uart2(txd), uart0(rxd), xg(
mpp51 51 gpio, ge1(rxd0), mss_i2c(sck), spi1(csn1), uart2(rxd), uart0(cts), sdio(pwr10)
mpp52 52 gpio, ge1(rxd1), synce1(clk), synce2(clk), spi1(csn2), uart1(cts), led(clk), pcie(rstoutn), pcie0(clkreq)
mpp53 53 gpio, ge1(rxd2), ptp(clk), spi1(csn3), uart1(rxd), led(stb), sdio(led)
mpp54 54 gpio, ge1(rxd3), synce2(clk), ptp(pclk_out), synce1(clk), led(data), sdio(hw_rst), sdio(wr_protect)
mpp55 55 gpio, ge1(rxctl_rxdv), ptp(pulse), sdio(led), sdio(card_detect)
mpp54 54 gpio, ge1(rxd3), synce2(clk), ptp(pclk_out), synce1(clk), led(data), sdio(hw_rst), sdio_wp(wr_protect)
mpp55 55 gpio, ge1(rxctl_rxdv), ptp(pulse), sdio(led), sdio_cd(card_detect)
mpp56 56 gpio, tdm(drx), au(i2sdo_spdifo), spi0(clk), uart1(rxd), sata1(present_act), sdio(clk)
mpp57 57 gpio, mss_i2c(sda), ptp(pclk_out), tdm(intn), au(i2sbclk), spi0(mosi), uart1(txd), sata0(present_act), sdio(cmd)
mpp58 58 gpio, mss_i2c(sck), ptp(clk), tdm(rstn), au(i2sdi), spi0(miso), uart1(cts), led(clk), sdio(d0)

36
Bindings/arm/mediatek.yaml
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@ -118,6 +118,10 @@ properties:
- enum:
- mediatek,mt8183-evb
- const: mediatek,mt8183
- items:
- enum:
- mediatek,mt8195-evb
- const: mediatek,mt8195
- description: Google Krane (Lenovo IdeaPad Duet, 10e,...)
items:
- enum:
@ -125,6 +129,38 @@ properties:
- google,krane-sku176
- const: google,krane
- const: mediatek,mt8183
- description: Google Damu (ASUS Chromebook Flip CM3)
items:
- const: google,damu
- const: mediatek,mt8183
- description: Google Juniper (Acer Chromebook Spin 311)
items:
- const: google,juniper-sku16
- const: google,juniper
- const: mediatek,mt8183
- description: Google Kakadu (ASUS Chromebook Detachable CM3)
items:
- const: google,kakadu-rev3
- const: google,kakadu-rev2
- const: google,kakadu
- const: mediatek,mt8183
- description: Google Kodama (Lenovo 10e Chromebook Tablet)
items:
- enum:
- google,kodama-sku16
- google,kodama-sku272
- google,kodama-sku288
- google,kodama-sku32
- const: google,kodama
- const: mediatek,mt8183
- items:
- enum:
- mediatek,mt8183-pumpkin
- const: mediatek,mt8183
- items:
- enum:
- mediatek,mt8516-pumpkin
- const: mediatek,mt8516
additionalProperties: true

1
Bindings/arm/mediatek/mediatek,mmsys.txt
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@ -13,6 +13,7 @@ Required Properties:
- "mediatek,mt6779-mmsys", "syscon"
- "mediatek,mt6797-mmsys", "syscon"
- "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon"
- "mediatek,mt8167-mmsys", "syscon"
- "mediatek,mt8173-mmsys", "syscon"
- "mediatek,mt8183-mmsys", "syscon"
- #clock-cells: Must be 1

1
Bindings/arm/msm/qcom,llcc.yaml
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@ -22,6 +22,7 @@ properties:
compatible:
enum:
- qcom,sc7180-llcc
- qcom,sc7280-llcc
- qcom,sdm845-llcc
- qcom,sm8150-llcc
- qcom,sm8250-llcc

1
Bindings/arm/mstar/mstar.yaml
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@ -24,6 +24,7 @@ properties:
items:
- enum:
- honestar,ssd201htv2 # Honestar SSD201_HT_V2 devkit
- m5stack,unitv2 # M5Stack UnitV2
- const: mstar,infinity2m
- description: infinity3 boards

29
Bindings/arm/npcm/npcm.yaml Normal file
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@ -0,0 +1,29 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/npcm/npcm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NPCM Platforms Device Tree Bindings
maintainers:
- Jonathan Neuschäfer <j.neuschaefer@gmx.net>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: WPCM450 based boards
items:
- enum:
- supermicro,x9sci-ln4f-bmc # Supermicro X9SCI-LN4F server's BMC
- const: nuvoton,wpcm450
- description: NPCM750 based boards
items:
- enum:
- nuvoton,npcm750-evb # NPCM750 evaluation board
- const: nuvoton,npcm750
additionalProperties: true

20
Bindings/arm/qcom.yaml
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@ -37,6 +37,7 @@ description: |
msm8994
msm8996
sc7180
sc7280
sdm630
sdm660
sdm845
@ -136,6 +137,16 @@ properties:
- samsung,a5u-eur
- const: qcom,msm8916
- items:
- enum:
- sony,karin_windy
- sony,karin-row
- sony,satsuki-row
- sony,sumire-row
- sony,suzuran-row
- qcom,msm8994
- const: qcom,apq8094
- items:
- const: qcom,msm8996-mtp
@ -164,6 +175,11 @@ properties:
- qcom,sc7180-idp
- const: qcom,sc7180
- items:
- enum:
- qcom,sc7280-idp
- const: qcom,sc7280
- items:
- enum:
- xiaomi,lavender
@ -172,10 +188,13 @@ properties:
- items:
- enum:
- qcom,sdx55-mtp
- qcom,sdx55-telit-fn980-tlb
- qcom,sdx55-t55
- const: qcom,sdx55
- items:
- enum:
- qcom,ipq6018-cp01
- qcom,ipq6018-cp01-c1
- const: qcom,ipq6018
@ -187,6 +206,7 @@ properties:
- items:
- enum:
- qcom,sm8350-hdk
- qcom,sm8350-mtp
- const: qcom,sm8350

1
Bindings/arm/rockchip.yaml
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@ -134,6 +134,7 @@ properties:
- friendlyarm,nanopi-m4
- friendlyarm,nanopi-m4b
- friendlyarm,nanopi-neo4
- friendlyarm,nanopi-r4s
- const: rockchip,rk3399
- description: GeekBuying GeekBox

21
Bindings/arm/stm32/stm32.yaml
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@ -51,6 +51,10 @@ properties:
- st,stm32h743i-disco
- st,stm32h743i-eval
- const: st,stm32h743
- items:
- enum:
- st,stm32h750i-art-pi
- const: st,stm32h750
- items:
- enum:
- shiratech,stm32mp157a-iot-box # IoT Box
@ -64,6 +68,23 @@ properties:
- const: st,stm32mp157c-ev1
- const: st,stm32mp157c-ed1
- const: st,stm32mp157
- description: Engicam i.Core STM32MP1 SoM based Boards
items:
- enum:
- engicam,icore-stm32mp1-ctouch2 # STM32MP1 Engicam i.Core STM32MP1 C.TOUCH 2.0
- engicam,icore-stm32mp1-edimm2.2 # STM32MP1 Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit
- const: engicam,icore-stm32mp1 # STM32MP1 Engicam i.Core STM32MP1 SoM
- const: st,stm32mp157
- description: Engicam MicroGEA STM32MP1 SoM based Boards
items:
- enum:
- engicam,microgea-stm32mp1-microdev2.0
- engicam,microgea-stm32mp1-microdev2.0-of7
- const: engicam,microgea-stm32mp1
- const: st,stm32mp157
- description: Octavo OSD32MP15x System-in-Package based boards
items:
- enum:

5
Bindings/arm/sunxi.yaml
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@ -802,6 +802,11 @@ properties:
- const: tbs-biometrics,a711
- const: allwinner,sun8i-a83t
- description: Topwise A721 Tablet
items:
- const: topwise,a721
- const: allwinner,sun4i-a10
- description: Utoo P66
items:
- const: utoo,p66

9
Bindings/arm/ti/k3.yaml
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@ -23,6 +23,8 @@ properties:
items:
- enum:
- ti,am654-evm
- siemens,iot2050-basic
- siemens,iot2050-advanced
- const: ti,am654
- description: K3 J721E SoC
@ -33,6 +35,13 @@ properties:
items:
- const: ti,j7200
- description: K3 AM642 SoC
items:
- enum:
- ti,am642-evm
- ti,am642-sk
- const: ti,am642
additionalProperties: true
...

49
Bindings/arm/trbe.yaml Normal file
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@ -0,0 +1,49 @@
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
# Copyright 2021, Arm Ltd
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/trbe.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: ARM Trace Buffer Extensions
maintainers:
- Anshuman Khandual <anshuman.khandual@arm.com>
description: |
Arm Trace Buffer Extension (TRBE) is a per CPU component
for storing trace generated on the CPU to memory. It is
accessed via CPU system registers. The software can verify
if it is permitted to use the component by checking the
TRBIDR register.
properties:
$nodename:
const: "trbe"
compatible:
items:
- const: arm,trace-buffer-extension
interrupts:
description: |
Exactly 1 PPI must be listed. For heterogeneous systems where
TRBE is only supported on a subset of the CPUs, please consult
the arm,gic-v3 binding for details on describing a PPI partition.
maxItems: 1
required:
- compatible
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
trbe {
compatible = "arm,trace-buffer-extension";
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
...

4
Bindings/ata/ahci-ceva.txt
View File

@ -38,6 +38,8 @@ Required properties:
Optional properties:
- ceva,broken-gen2: limit to gen1 speed instead of gen2.
- phys: phandle for the PHY device
- resets: phandle to the reset controller for the SATA IP
Examples:
ahci@fd0c0000 {
@ -56,4 +58,6 @@ Examples:
ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>;
ceva,broken-gen2;
phys = <&psgtr 1 PHY_TYPE_SATA 1 1>;
resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
};

176
Bindings/ata/nvidia,tegra-ahci.yaml Normal file
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@ -0,0 +1,176 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/nvidia,tegra-ahci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Tegra AHCI SATA Controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jonathan Hunter <jonathanh@nvidia.com>
properties:
compatible:
enum:
- nvidia,tegra124-ahci
- nvidia,tegra132-ahci
- nvidia,tegra210-ahci
- nvidia,tegra186-ahci
reg:
minItems: 2
maxItems: 3
items:
- description: AHCI registers
- description: SATA configuration and IPFS registers
- description: SATA AUX registers
interrupts:
maxItems: 1
clock-names:
items:
- const: sata
- const: sata-oob
clocks:
maxItems: 2
reset-names:
minItems: 2
items:
- const: sata
- const: sata-cold
- const: sata-oob
resets:
minItems: 2
maxItems: 3
iommus:
maxItems: 1
interconnect-names:
items:
- const: dma-mem
- const: write
interconnects:
maxItems: 2
power-domains:
items:
- description: SAX power-domain
phy-names:
items:
- const: sata-0
phys:
maxItems: 1
hvdd-supply:
description: SATA HVDD regulator supply.
vddio-supply:
description: SATA VDDIO regulator supply.
avdd-supply:
description: SATA AVDD regulator supply.
target-5v-supply:
description: SATA 5V power regulator supply.
target-12v-supply:
description: SATA 12V power regulator supply.
required:
- compatible
- reg
- interrupts
- clock-names
- clocks
- reset-names
- resets
allOf:
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra124-ahci
- nvidia,tegra132-ahci
then:
properties:
reg:
maxItems: 2
reset-names:
minItems: 3
resets:
minItems: 3
required:
- phys
- phy-names
- hvdd-supply
- vddio-supply
- avdd-supply
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra210-ahci
then:
properties:
reg:
minItems: 3
reset-names:
minItems: 3
resets:
minItems: 3
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra186-ahci
then:
properties:
reg:
minItems: 3
reset-names:
maxItems: 2
resets:
maxItems: 2
required:
- iommus
- interconnect-names
- interconnects
- power-domains
additionalProperties: true
examples:
- |
#include <dt-bindings/clock/tegra210-car.h>
#include <dt-bindings/reset/tegra210-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
sata@70020000 {
compatible = "nvidia,tegra210-ahci";
reg = <0x70027000 0x00002000>, /* AHCI */
<0x70020000 0x00007000>, /* SATA */
<0x70001100 0x00010000>; /* SATA AUX */
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_SATA>,
<&tegra_car TEGRA210_CLK_SATA_OOB>;
clock-names = "sata", "sata-oob";
resets = <&tegra_car 124>,
<&tegra_car 129>,
<&tegra_car 123>;
reset-names = "sata", "sata-cold", "sata-oob";
};

2
Bindings/clock/allwinner,sun4i-a10-pll1-clk.yaml
View File

@ -44,7 +44,7 @@ examples:
- |
clk@1c20000 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-pll1";
compatible = "allwinner,sun4i-a10-pll1-clk";
reg = <0x01c20000 0x4>;
clocks = <&osc24M>;
clock-output-names = "osc24M";

2
Bindings/clock/armada3700-tbg-clock.txt
View File

@ -1,6 +1,6 @@
* Time Base Generator Clock bindings for Marvell Armada 37xx SoCs
Marvell Armada 37xx SoCs provde Time Base Generator clocks which are
Marvell Armada 37xx SoCs provide Time Base Generator clocks which are
used as parent clocks for the peripheral clocks.
The TBG clock consumer should specify the desired clock by having the

2
Bindings/clock/idt,versaclock5.yaml
View File

@ -60,7 +60,6 @@ properties:
maxItems: 2
idt,xtal-load-femtofarads:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 9000
maximum: 22760
description: Optional load capacitor for XTAL1 and XTAL2
@ -84,7 +83,6 @@ patternProperties:
enum: [ 1800000, 2500000, 3300000 ]
idt,slew-percent:
description: The Slew rate control for CMOS single-ended.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 80, 85, 90, 100 ]
required:

6
Bindings/clock/imx8qxp-lpcg.yaml
View File

@ -107,8 +107,8 @@ examples:
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b010000 0x10000>;
clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>,
<&sdhc0_lpcg IMX_LPCG_CLK_0>,
<&sdhc0_lpcg IMX_LPCG_CLK_5>;
clock-names = "ipg", "per", "ahb";
<&sdhc0_lpcg IMX_LPCG_CLK_5>,
<&sdhc0_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "ahb", "per";
power-domains = <&pd IMX_SC_R_SDHC_0>;
};

68
Bindings/clock/mediatek,mt7621-sysc.yaml Normal file
View File

@ -0,0 +1,68 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt7621-sysc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MT7621 Clock Device Tree Bindings
maintainers:
- Sergio Paracuellos <sergio.paracuellos@gmail.com>
description: |
The MT7621 has a PLL controller from where the cpu clock is provided
as well as derived clocks for the bus and the peripherals. It also
can gate SoC device clocks.
Each clock is assigned an identifier and client nodes use this identifier
to specify the clock which they consume.
All these identifiers could be found in:
[1]: <include/dt-bindings/clock/mt7621-clk.h>.
The clocks are provided inside a system controller node.
properties:
compatible:
items:
- const: mediatek,mt7621-sysc
- const: syscon
reg:
maxItems: 1
"#clock-cells":
description:
The first cell indicates the clock number, see [1] for available
clocks.
const: 1
ralink,memctl:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle of syscon used to control memory registers
clock-output-names:
maxItems: 8
required:
- compatible
- reg
- '#clock-cells'
- ralink,memctl
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/mt7621-clk.h>
sysc: sysc@0 {
compatible = "mediatek,mt7621-sysc", "syscon";
reg = <0x0 0x100>;
#clock-cells = <1>;
ralink,memctl = <&memc>;
clock-output-names = "xtal", "cpu", "bus",
"50m", "125m", "150m",
"250m", "270m";
};

12
Bindings/clock/milbeaut-clock.yaml
View File

@ -18,10 +18,12 @@ description: |
properties:
compatible:
oneOf:
- items:
- enum:
- socionext,milbeaut-m10v-ccu
enum:
- socionext,milbeaut-m10v-ccu
reg:
maxItems: 1
clocks:
maxItems: 1
description: external clock
@ -41,7 +43,7 @@ examples:
# Clock controller node:
- |
m10v-clk-ctrl@1d021000 {
compatible = "socionext,milbeaut-m10v-clk-ccu";
compatible = "socionext,milbeaut-m10v-ccu";
reg = <0x1d021000 0x4000>;
#clock-cells = <1>;
clocks = <&clki40mhz>;

82
Bindings/clock/qcom,gcc-sdm845.yaml Normal file
View File

@ -0,0 +1,82 @@
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-sdm845.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on SDM845
See also:
- dt-bindings/clock/qcom,gcc-sdm845.h
properties:
compatible:
const: qcom,gcc-sdm845
clocks:
items:
- description: Board XO source
- description: Board active XO source
- description: Sleep clock source
- description: PCIE 0 Pipe clock source
- description: PCIE 1 Pipe clock source
clock-names:
items:
- const: bi_tcxo
- const: bi_tcxo_ao
- const: sleep_clk
- const: pcie_0_pipe_clk
- const: pcie_1_pipe_clk
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
protected-clocks:
description:
Protected clock specifier list as per common clock binding.
required:
- compatible
- reg
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
# Example for GCC for SDM845:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@100000 {
compatible = "qcom,gcc-sdm845";
reg = <0x100000 0x1f0000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>,
<&pcie0_lane>,
<&pcie1_lane>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk", "pcie_1_pipe_clk";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

2
Bindings/clock/qcom,gcc.yaml
View File

@ -32,7 +32,6 @@ description: |
- dt-bindings/clock/qcom,gcc-mdm9615.h
- dt-bindings/reset/qcom,gcc-mdm9615.h
- dt-bindings/clock/qcom,gcc-sdm660.h (qcom,gcc-sdm630 and qcom,gcc-sdm660)
- dt-bindings/clock/qcom,gcc-sdm845.h
properties:
compatible:
@ -52,7 +51,6 @@ properties:
- qcom,gcc-mdm9615
- qcom,gcc-sdm630
- qcom,gcc-sdm660
- qcom,gcc-sdm845
'#clock-cells':
const: 1

60
Bindings/clock/rockchip,rk3568-cru.yaml Normal file
View File

@ -0,0 +1,60 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/rockchip,rk3568-cru.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ROCKCHIP rk3568 Family Clock Control Module Binding
maintainers:
- Elaine Zhang <zhangqing@rock-chips.com>
- Heiko Stuebner <heiko@sntech.de>
description: |
The RK3568 clock controller generates the clock and also implements a
reset controller for SoC peripherals.
(examples: provide SCLK_UART1\PCLK_UART1 and SRST_P_UART1\SRST_S_UART1 for UART module)
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/rk3568-cru.h headers and can be
used in device tree sources.
properties:
compatible:
enum:
- rockchip,rk3568-cru
- rockchip,rk3568-pmucru
reg:
maxItems: 1
"#clock-cells":
const: 1
"#reset-cells":
const: 1
required:
- compatible
- reg
- "#clock-cells"
- "#reset-cells"
additionalProperties: false
examples:
# Clock Control Module node:
- |
pmucru: clock-controller@fdd00000 {
compatible = "rockchip,rk3568-pmucru";
reg = <0xfdd00000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
- |
cru: clock-controller@fdd20000 {
compatible = "rockchip,rk3568-cru";
reg = <0xfdd20000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};

25
Bindings/connector/usb-connector.yaml
View File

@ -149,6 +149,17 @@ properties:
maxItems: 6
$ref: /schemas/types.yaml#/definitions/uint32-array
sink-vdos-v1:
description: An array of u32 with each entry, a Vendor Defined Message Object (VDO),
providing additional information corresponding to the product, the detailed bit
definitions and the order of each VDO can be found in
"USB Power Delivery Specification Revision 2.0, Version 1.3" chapter 6.4.4.3.1 Discover
Identity. User can specify the VDO array via VDO_IDH/_CERT/_PRODUCT/_CABLE/_AMA defined in
dt-bindings/usb/pd.h.
minItems: 3
maxItems: 6
$ref: /schemas/types.yaml#/definitions/uint32-array
op-sink-microwatt:
description: Sink required operating power in microwatt, if source can't
offer the power, Capability Mismatch is set. Required for power sink and
@ -197,6 +208,20 @@ properties:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 2, 3]
slow-charger-loop:
description: Allows PMIC charger loops which are slow(i.e. cannot meet the 15ms deadline) to
still comply to pSnkStby i.e Maximum power that can be consumed by sink while in Sink Standby
state as defined in 7.4.2 Sink Electrical Parameters of USB Power Delivery Specification
Revision 3.0, Version 1.2. When the property is set, the port requests pSnkStby(2.5W -
5V@500mA) upon entering SNK_DISCOVERY(instead of 3A or the 1.5A, Rp current advertised, during
SNK_DISCOVERY) and the actual currrent limit after reception of PS_Ready for PD link or during
SNK_READY for non-pd link.
type: boolean
dependencies:
sink-vdos-v1: [ 'sink-vdos' ]
sink-vdos: [ 'sink-vdos-v1' ]
required:
- compatible

62
Bindings/counter/interrupt-counter.yaml Normal file
View File

@ -0,0 +1,62 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/counter/interrupt-counter.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Interrupt counter
maintainers:
- Oleksij Rempel <o.rempel@pengutronix.de>
description: |
A generic interrupt counter to measure interrupt frequency. It was developed
and used for agricultural devices to measure rotation speed of wheels or
other tools. Since the direction of rotation is not important, only one
signal line is needed.
Interrupts or gpios are required. If both are defined, the interrupt will
take precedence for counting interrupts.
properties:
compatible:
const: interrupt-counter
interrupts:
maxItems: 1
gpios:
maxItems: 1
required:
- compatible
anyOf:
- required: [ interrupts-extended ]
- required: [ interrupts ]
- required: [ gpios ]
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
counter-0 {
compatible = "interrupt-counter";
interrupts-extended = <&gpio 0 IRQ_TYPE_EDGE_RISING>;
};
counter-1 {
compatible = "interrupt-counter";
gpios = <&gpio 2 GPIO_ACTIVE_HIGH>;
};
counter-2 {
compatible = "interrupt-counter";
interrupts-extended = <&gpio 2 IRQ_TYPE_EDGE_RISING>;
gpios = <&gpio 2 GPIO_ACTIVE_HIGH>;
};
...

24
Bindings/crypto/ti,sa2ul.yaml
View File

@ -14,6 +14,7 @@ properties:
enum:
- ti,j721e-sa2ul
- ti,am654-sa2ul
- ti,am64-sa2ul
reg:
maxItems: 1
@ -45,6 +46,18 @@ properties:
description:
Address translation for the possible RNG child node for SA2UL
clocks:
items:
- description: Clock used by PKA
- description: Main Input Clock
- description: Clock used by rng
clock-names:
items:
- const: pka_in_clk
- const: x1_clk
- const: x2_clk
patternProperties:
"^rng@[a-f0-9]+$":
type: object
@ -57,7 +70,16 @@ required:
- power-domains
- dmas
- dma-names
- dma-coherent
if:
properties:
compatible:
enum:
- ti,j721e-sa2ul
- ti,am654-sa2ul
then:
required:
- dma-coherent
additionalProperties: false

5
Bindings/ddr/lpddr3.txt
View File

@ -12,6 +12,9 @@ Required properties:
Optional properties:
- manufacturer-id : <u32> Manufacturer ID value read from Mode Register 5
- revision-id : <u32 u32> Revision IDs read from Mode Registers 6 and 7
The following optional properties represent the minimum value of some AC
timing parameters of the DDR device in terms of number of clock cycles.
These values shall be obtained from the device data-sheet.
@ -49,6 +52,8 @@ samsung_K3QF2F20DB: lpddr3 {
compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
density = <16384>;
io-width = <32>;
manufacturer-id = <1>;
revision-id = <123 234>;
#address-cells = <1>;
#size-cells = <0>;

75
Bindings/devfreq/rk3399_dmc.txt
View File

@ -12,6 +12,8 @@ Required properties:
for details.
- center-supply: DMC supply node.
- status: Marks the node enabled/disabled.
- rockchip,pmu: Phandle to the syscon managing the "PMU general register
files".
Optional properties:
- interrupts: The CPU interrupt number. The interrupt specifier
@ -77,24 +79,23 @@ Following properties relate to DDR timing:
- rockchip,ddr3_drv : When the DRAM type is DDR3, this parameter defines
the DRAM side driver strength in ohms. Default
value is DDR3_DS_40ohm.
value is 40.
- rockchip,ddr3_odt : When the DRAM type is DDR3, this parameter defines
the DRAM side ODT strength in ohms. Default value
is DDR3_ODT_120ohm.
is 120.
- rockchip,phy_ddr3_ca_drv : When the DRAM type is DDR3, this parameter defines
the phy side CA line (incluing command line,
address line and clock line) driver strength.
Default value is PHY_DRV_ODT_40.
Default value is 40.
- rockchip,phy_ddr3_dq_drv : When the DRAM type is DDR3, this parameter defines
the PHY side DQ line (including DQS/DQ/DM line)
driver strength. Default value is PHY_DRV_ODT_40.
driver strength. Default value is 40.
- rockchip,phy_ddr3_odt : When the DRAM type is DDR3, this parameter defines
the PHY side ODT strength. Default value is
PHY_DRV_ODT_240.
the PHY side ODT strength. Default value is 240.
- rockchip,lpddr3_odt_dis_freq : When the DRAM type is LPDDR3, this parameter defines
then ODT disable frequency in MHz (Mega Hz).
@ -104,25 +105,23 @@ Following properties relate to DDR timing:
- rockchip,lpddr3_drv : When the DRAM type is LPDDR3, this parameter defines
the DRAM side driver strength in ohms. Default
value is LP3_DS_34ohm.
value is 34.
- rockchip,lpddr3_odt : When the DRAM type is LPDDR3, this parameter defines
the DRAM side ODT strength in ohms. Default value
is LP3_ODT_240ohm.
is 240.
- rockchip,phy_lpddr3_ca_drv : When the DRAM type is LPDDR3, this parameter defines
the PHY side CA line (including command line,
address line and clock line) driver strength.
Default value is PHY_DRV_ODT_40.
Default value is 40.
- rockchip,phy_lpddr3_dq_drv : When the DRAM type is LPDDR3, this parameter defines
the PHY side DQ line (including DQS/DQ/DM line)
driver strength. Default value is
PHY_DRV_ODT_40.
driver strength. Default value is 40.
- rockchip,phy_lpddr3_odt : When dram type is LPDDR3, this parameter define
the phy side odt strength, default value is
PHY_DRV_ODT_240.
the phy side odt strength, default value is 240.
- rockchip,lpddr4_odt_dis_freq : When the DRAM type is LPDDR4, this parameter
defines the ODT disable frequency in
@ -132,32 +131,30 @@ Following properties relate to DDR timing:
- rockchip,lpddr4_drv : When the DRAM type is LPDDR4, this parameter defines
the DRAM side driver strength in ohms. Default
value is LP4_PDDS_60ohm.
value is 60.
- rockchip,lpddr4_dq_odt : When the DRAM type is LPDDR4, this parameter defines
the DRAM side ODT on DQS/DQ line strength in ohms.
Default value is LP4_DQ_ODT_40ohm.
Default value is 40.
- rockchip,lpddr4_ca_odt : When the DRAM type is LPDDR4, this parameter defines
the DRAM side ODT on CA line strength in ohms.
Default value is LP4_CA_ODT_40ohm.
Default value is 40.
- rockchip,phy_lpddr4_ca_drv : When the DRAM type is LPDDR4, this parameter defines
the PHY side CA line (including command address
line) driver strength. Default value is
PHY_DRV_ODT_40.
line) driver strength. Default value is 40.
- rockchip,phy_lpddr4_ck_cs_drv : When the DRAM type is LPDDR4, this parameter defines
the PHY side clock line and CS line driver
strength. Default value is PHY_DRV_ODT_80.
strength. Default value is 80.
- rockchip,phy_lpddr4_dq_drv : When the DRAM type is LPDDR4, this parameter defines
the PHY side DQ line (including DQS/DQ/DM line)
driver strength. Default value is PHY_DRV_ODT_80.
driver strength. Default value is 80.
- rockchip,phy_lpddr4_odt : When the DRAM type is LPDDR4, this parameter defines
the PHY side ODT strength. Default value is
PHY_DRV_ODT_60.
the PHY side ODT strength. Default value is 60.
Example:
dmc_opp_table: dmc_opp_table {
@ -193,23 +190,23 @@ Example:
rockchip,phy_dll_dis_freq = <125>;
rockchip,auto_pd_dis_freq = <666>;
rockchip,ddr3_odt_dis_freq = <333>;
rockchip,ddr3_drv = <DDR3_DS_40ohm>;
rockchip,ddr3_odt = <DDR3_ODT_120ohm>;
rockchip,phy_ddr3_ca_drv = <PHY_DRV_ODT_40>;
rockchip,phy_ddr3_dq_drv = <PHY_DRV_ODT_40>;
rockchip,phy_ddr3_odt = <PHY_DRV_ODT_240>;
rockchip,ddr3_drv = <40>;
rockchip,ddr3_odt = <120>;
rockchip,phy_ddr3_ca_drv = <40>;
rockchip,phy_ddr3_dq_drv = <40>;
rockchip,phy_ddr3_odt = <240>;
rockchip,lpddr3_odt_dis_freq = <333>;
rockchip,lpddr3_drv = <LP3_DS_34ohm>;
rockchip,lpddr3_odt = <LP3_ODT_240ohm>;
rockchip,phy_lpddr3_ca_drv = <PHY_DRV_ODT_40>;
rockchip,phy_lpddr3_dq_drv = <PHY_DRV_ODT_40>;
rockchip,phy_lpddr3_odt = <PHY_DRV_ODT_240>;
rockchip,lpddr3_drv = <34>;
rockchip,lpddr3_odt = <240>;
rockchip,phy_lpddr3_ca_drv = <40>;
rockchip,phy_lpddr3_dq_drv = <40>;
rockchip,phy_lpddr3_odt = <240>;
rockchip,lpddr4_odt_dis_freq = <333>;
rockchip,lpddr4_drv = <LP4_PDDS_60ohm>;
rockchip,lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
rockchip,lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
rockchip,phy_lpddr4_ca_drv = <PHY_DRV_ODT_40>;
rockchip,phy_lpddr4_ck_cs_drv = <PHY_DRV_ODT_80>;
rockchip,phy_lpddr4_dq_drv = <PHY_DRV_ODT_80>;
rockchip,phy_lpddr4_odt = <PHY_DRV_ODT_60>;
rockchip,lpddr4_drv = <60>;
rockchip,lpddr4_dq_odt = <40>;
rockchip,lpddr4_ca_odt = <40>;
rockchip,phy_lpddr4_ca_drv = <40>;
rockchip,phy_lpddr4_ck_cs_drv = <80>;
rockchip,phy_lpddr4_dq_drv = <80>;
rockchip,phy_lpddr4_odt = <60>;
};

1
Bindings/display/allwinner,sun4i-a10-tcon.yaml
View File

@ -73,7 +73,6 @@ properties:
clock-output-names:
description:
Name of the LCD pixel clock created.
$ref: /schemas/types.yaml#/definitions/string-array
maxItems: 1
dmas:

4
Bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml
View File

@ -12,8 +12,8 @@ description: |
and CEC.
These DT bindings follow the Synopsys DWC HDMI TX bindings defined
in Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with
the following device-specific properties.
in bridge/synopsys,dw-hdmi.yaml with the following device-specific
properties.
maintainers:
- Chen-Yu Tsai <wens@csie.org>

6
Bindings/display/brcm,bcm2835-dsi0.yaml
View File

@ -77,12 +77,6 @@ examples:
clock-output-names = "dsi1_byte", "dsi1_ddr2", "dsi1_ddr";
pitouchscreen: panel@0 {
compatible = "raspberrypi,touchscreen";
reg = <0>;
/* ... */
};
};
...

15
Bindings/display/bridge/analogix,anx7625.yaml
View File

@ -34,6 +34,15 @@ properties:
description: used for reset chip control, RESET_N pin B7.
maxItems: 1
vdd10-supply:
description: Regulator that provides the supply 1.0V power.
vdd18-supply:
description: Regulator that provides the supply 1.8V power.
vdd33-supply:
description: Regulator that provides the supply 3.3V power.
ports:
$ref: /schemas/graph.yaml#/properties/ports
@ -55,6 +64,9 @@ properties:
required:
- compatible
- reg
- vdd10-supply
- vdd18-supply
- vdd33-supply
- ports
additionalProperties: false
@ -72,6 +84,9 @@ examples:
reg = <0x58>;
enable-gpios = <&pio 45 GPIO_ACTIVE_HIGH>;
reset-gpios = <&pio 73 GPIO_ACTIVE_HIGH>;
vdd10-supply = <&pp1000_mipibrdg>;
vdd18-supply = <&pp1800_mipibrdg>;
vdd33-supply = <&pp3300_mipibrdg>;
ports {
#address-cells = <1>;

99
Bindings/display/bridge/chipone,icn6211.yaml Normal file
View File

@ -0,0 +1,99 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/chipone,icn6211.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Chipone ICN6211 MIPI-DSI to RGB Converter bridge
maintainers:
- Jagan Teki <jagan@amarulasolutions.com>
description: |
ICN6211 is MIPI-DSI to RGB Converter bridge from chipone.
It has a flexible configuration of MIPI DSI signal input and
produce RGB565, RGB666, RGB888 output format.
properties:
compatible:
enum:
- chipone,icn6211
reg:
maxItems: 1
description: virtual channel number of a DSI peripheral
enable-gpios:
description: Bridge EN pin, chip is reset when EN is low.
vdd1-supply:
description: A 1.8V/2.5V/3.3V supply that power the MIPI RX.
vdd2-supply:
description: A 1.8V/2.5V/3.3V supply that power the PLL.
vdd3-supply:
description: A 1.8V/2.5V/3.3V supply that power the RGB output.
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description:
Video port for MIPI DSI input
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
Video port for MIPI DPI output (panel or connector).
required:
- port@0
- port@1
required:
- compatible
- reg
- enable-gpios
- ports
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
dsi {
#address-cells = <1>;
#size-cells = <0>;
bridge@0 {
compatible = "chipone,icn6211";
reg = <0>;
enable-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* LCD-RST: PL5 */
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
bridge_in_dsi: endpoint {
remote-endpoint = <&dsi_out_bridge>;
};
};
port@1 {
reg = <1>;
bridge_out_panel: endpoint {
remote-endpoint = <&panel_out_bridge>;
};
};
};
};
};

102
Bindings/display/bridge/lontium,lt8912b.yaml Normal file
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@ -0,0 +1,102 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/lontium,lt8912b.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Lontium LT8912B MIPI to HDMI Bridge
maintainers:
- Adrien Grassein <adrien.grassein@gmail.com>
description: |
The LT8912B is a bridge device which convert DSI to HDMI
properties:
compatible:
enum:
- lontium,lt8912b
reg:
maxItems: 1
reset-gpios:
maxItems: 1
description: GPIO connected to active high RESET pin.
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description:
Primary MIPI port for MIPI input
properties:
endpoint:
$ref: /schemas/media/video-interfaces.yaml#
unevaluatedProperties: false
properties:
data-lanes: true
required:
- data-lanes
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: |
HDMI port, should be connected to a node compatible with the
hdmi-connector binding.
required:
- port@0
- port@1
required:
- compatible
- reg
- reset-gpios
- ports
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
i2c4 {
#address-cells = <1>;
#size-cells = <0>;
hdmi-bridge@48 {
compatible = "lontium,lt8912b";
reg = <0x48>;
reset-gpios = <&max7323 0 GPIO_ACTIVE_LOW>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hdmi_out_in: endpoint {
data-lanes = <0 1 2 3>;
remote-endpoint = <&mipi_dsi_out>;
};
};
port@1 {
reg = <1>;
endpoint {
remote-endpoint = <&hdmi_in>;
};
};
};
};
};
...

125
Bindings/display/bridge/renesas,dw-hdmi.yaml Normal file
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@ -0,0 +1,125 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/renesas,dw-hdmi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas R-Car DWC HDMI TX Encoder
maintainers:
- Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
description: |
The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
with a companion PHY IP.
allOf:
- $ref: synopsys,dw-hdmi.yaml#
properties:
compatible:
items:
- enum:
- renesas,r8a774a1-hdmi # for RZ/G2M compatible HDMI TX
- renesas,r8a774b1-hdmi # for RZ/G2N compatible HDMI TX
- renesas,r8a774e1-hdmi # for RZ/G2H compatible HDMI TX
- renesas,r8a7795-hdmi # for R-Car H3 compatible HDMI TX
- renesas,r8a7796-hdmi # for R-Car M3-W compatible HDMI TX
- renesas,r8a77961-hdmi # for R-Car M3-W+ compatible HDMI TX
- renesas,r8a77965-hdmi # for R-Car M3-N compatible HDMI TX
- const: renesas,rcar-gen3-hdmi
reg-io-width:
const: 1
clocks:
maxItems: 2
clock-names:
maxItems: 2
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: Parallel RGB input port
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: HDMI output port
port@2:
$ref: /schemas/graph.yaml#/properties/port
description: Sound input port
required:
- port@0
- port@1
- port@2
power-domains:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- interrupts
- ports
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/r8a7795-sysc.h>
hdmi@fead0000 {
compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
reg = <0xfead0000 0x10000>;
interrupts = <0 389 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_CORE R8A7795_CLK_S0D4>, <&cpg CPG_MOD 729>;
clock-names = "iahb", "isfr";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dw_hdmi0_in: endpoint {
remote-endpoint = <&du_out_hdmi0>;
};
};
port@1 {
reg = <1>;
rcar_dw_hdmi0_out: endpoint {
remote-endpoint = <&hdmi0_con>;
};
};
port@2 {
reg = <2>;
rcar_dw_hdmi0_sound_in: endpoint {
remote-endpoint = <&hdmi_sound_out>;
};
};
};
};
hdmi0-out {
compatible = "hdmi-connector";
label = "HDMI0 OUT";
type = "a";
port {
hdmi0_con: endpoint {
remote-endpoint = <&rcar_dw_hdmi0_out>;
};
};
};
...

55
Bindings/display/bridge/synopsys,dw-hdmi.yaml Normal file
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@ -0,0 +1,55 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Common Properties for Synopsys DesignWare HDMI TX Controller
maintainers:
- Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
description: |
This document defines device tree properties for the Synopsys DesignWare HDMI
TX controller (DWC HDMI TX) IP core. It doesn't constitute a full device tree
binding specification by itself but is meant to be referenced by device tree
bindings for the platform-specific integrations of the DWC HDMI TX.
When referenced from platform device tree bindings the properties defined in
this document are defined as follows. The platform device tree bindings are
responsible for defining whether each property is required or optional.
properties:
reg:
maxItems: 1
reg-io-width:
description:
Width (in bytes) of the registers specified by the reg property.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [1, 4]
default: 1
clocks:
minItems: 2
maxItems: 5
items:
- description: The bus clock for either AHB and APB
- description: The internal register configuration clock
additionalItems: true
clock-names:
minItems: 2
maxItems: 5
items:
- const: iahb
- const: isfr
additionalItems: true
interrupts:
maxItems: 1
additionalProperties: true
...

110
Bindings/display/fsl,lcdif.yaml Normal file
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@ -0,0 +1,110 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/fsl,lcdif.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale/NXP i.MX LCD Interface (LCDIF)
maintainers:
- Marek Vasut <marex@denx.de>
- Stefan Agner <stefan@agner.ch>
description: |
(e)LCDIF display controller found in the Freescale/NXP i.MX SoCs.
properties:
compatible:
oneOf:
- enum:
- fsl,imx23-lcdif
- fsl,imx28-lcdif
- fsl,imx6sx-lcdif
- items:
- enum:
- fsl,imx6sl-lcdif
- fsl,imx6sll-lcdif
- fsl,imx6ul-lcdif
- fsl,imx7d-lcdif
- fsl,imx8mm-lcdif
- fsl,imx8mq-lcdif
- const: fsl,imx6sx-lcdif
reg:
maxItems: 1
clocks:
items:
- description: Pixel clock
- description: Bus clock
- description: Display AXI clock
minItems: 1
clock-names:
items:
- const: pix
- const: axi
- const: disp_axi
minItems: 1
interrupts:
maxItems: 1
port:
$ref: /schemas/graph.yaml#/properties/port
description: The LCDIF output port
required:
- compatible
- reg
- clocks
- interrupts
- port
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
const: fsl,imx6sx-lcdif
then:
properties:
clocks:
minItems: 2
maxItems: 3
clock-names:
minItems: 2
maxItems: 3
required:
- clock-names
else:
properties:
clocks:
maxItems: 1
clock-names:
maxItems: 1
examples:
- |
#include <dt-bindings/clock/imx6sx-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
display-controller@2220000 {
compatible = "fsl,imx6sx-lcdif";
reg = <0x02220000 0x4000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
<&clks IMX6SX_CLK_LCDIF_APB>,
<&clks IMX6SX_CLK_DISPLAY_AXI>;
clock-names = "pix", "axi", "disp_axi";
port {
endpoint {
remote-endpoint = <&panel_in>;
};
};
};
...

126
Bindings/display/imx/fsl,imx6-hdmi.yaml Normal file
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@ -0,0 +1,126 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx6-hdmi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX6 DWC HDMI TX Encoder
maintainers:
- Philipp Zabel <p.zabel@pengutronix.de>
description: |
The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
with a companion PHY IP.
allOf:
- $ref: ../bridge/synopsys,dw-hdmi.yaml#
properties:
compatible:
enum:
- fsl,imx6dl-hdmi
- fsl,imx6q-hdmi
reg-io-width:
const: 1
clocks:
maxItems: 2
clock-names:
maxItems: 2
ddc-i2c-bus:
$ref: /schemas/types.yaml#/definitions/phandle
description:
The HDMI DDC bus can be connected to either a system I2C master or the
functionally-reduced I2C master contained in the DWC HDMI. When connected
to a system I2C master this property contains a phandle to that I2C
master controller.
gpr:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle to the iomuxc-gpr region containing the HDMI multiplexer control
register.
ports:
$ref: /schemas/graph.yaml#/properties/ports
description: |
This device has four video ports, corresponding to the four inputs of the
HDMI multiplexer. Each port shall have a single endpoint.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: First input of the HDMI multiplexer
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: Second input of the HDMI multiplexer
port@2:
$ref: /schemas/graph.yaml#/properties/port
description: Third input of the HDMI multiplexer
port@3:
$ref: /schemas/graph.yaml#/properties/port
description: Fourth input of the HDMI multiplexer
anyOf:
- required:
- port@0
- required:
- port@1
- required:
- port@2
- required:
- port@3
required:
- compatible
- reg
- clocks
- clock-names
- gpr
- interrupts
- ports
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx6qdl-clock.h>
hdmi: hdmi@120000 {
reg = <0x00120000 0x9000>;
interrupts = <0 115 0x04>;
gpr = <&gpr>;
clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
<&clks IMX6QDL_CLK_HDMI_ISFR>;
clock-names = "iahb", "isfr";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hdmi_mux_0: endpoint {
remote-endpoint = <&ipu1_di0_hdmi>;
};
};
port@1 {
reg = <1>;
hdmi_mux_1: endpoint {
remote-endpoint = <&ipu1_di1_hdmi>;
};
};
};
};
...

2
Bindings/display/mediatek/mediatek,disp.txt
View File

@ -64,7 +64,7 @@ Required properties (DMA function blocks):
- larb: Should contain a phandle pointing to the local arbiter device as defined
in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
- iommus: Should point to the respective IOMMU block with master port as
argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
for details.
Optional properties (RDMA function blocks):

12
Bindings/display/mediatek/mediatek,dpi.yaml
View File

@ -22,6 +22,7 @@ properties:
- mediatek,mt7623-dpi
- mediatek,mt8173-dpi
- mediatek,mt8183-dpi
- mediatek,mt8192-dpi
reg:
maxItems: 1
@ -50,15 +51,10 @@ properties:
- const: sleep
port:
type: object
$ref: /schemas/graph.yaml#/properties/port
description:
Output port node with endpoint definitions as described in
Documentation/devicetree/bindings/graph.txt. This port should be connected
to the input port of an attached HDMI or LVDS encoder chip.
properties:
endpoint:
type: object
Output port node. This port should be connected to the input port of an
attached HDMI or LVDS encoder chip.
required:
- compatible

4
Bindings/display/msm/dpu.txt
View File

@ -2,14 +2,14 @@ Qualcomm Technologies, Inc. DPU KMS
Description:
Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
sub-blocks like DPU display controller, DSI and DP interfaces etc.
The DPU display controller is found in SDM845 SoC.
MDSS:
Required properties:
- compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss"
- reg: physical base address and length of contoller's registers.
- reg: physical base address and length of controller's registers.
- reg-names: register region names. The following region is required:
* "mdss"
- power-domains: a power domain consumer specifier according to

1
Bindings/display/panel/kingdisplay,kd035g6-54nt.yaml
View File

@ -47,7 +47,6 @@ examples:
spi-max-frequency = <3125000>;
spi-3wire;
spi-cs-high;
reset-gpios = <&gpe 2 GPIO_ACTIVE_LOW>;

2
Bindings/display/panel/panel-dpi.yaml
View File

@ -40,7 +40,7 @@ additionalProperties: false
examples:
- |
panel {
compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
compatible = "startek,startek-kd050c", "panel-dpi";
label = "osddisplay";
power-supply = <&vcc_supply>;
backlight = <&backlight>;

2
Bindings/display/panel/panel-simple.yaml
View File

@ -161,6 +161,8 @@ properties:
# Innolux Corporation 12.1" G121X1-L03 XGA (1024x768) TFT LCD panel
- innolux,g121x1-l03
# Innolux Corporation 11.6" WXGA (1366x768) TFT LCD panel
- innolux,n116bca-ea1
# Innolux Corporation 11.6" WXGA (1366x768) TFT LCD panel
- innolux,n116bge
# InnoLux 13.3" FHD (1920x1080) eDP TFT LCD panel
- innolux,n125hce-gn1

834
Bindings/display/renesas,du.yaml Normal file
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@ -0,0 +1,834 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/renesas,du.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas R-Car Display Unit (DU)
maintainers:
- Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
description: |
These DT bindings describe the Display Unit embedded in the Renesas R-Car
Gen1, R-Car Gen2, R-Car Gen3, RZ/G1 and RZ/G2 SoCs.
properties:
compatible:
enum:
- renesas,du-r8a7742 # for RZ/G1H compatible DU
- renesas,du-r8a7743 # for RZ/G1M compatible DU
- renesas,du-r8a7744 # for RZ/G1N compatible DU
- renesas,du-r8a7745 # for RZ/G1E compatible DU
- renesas,du-r8a77470 # for RZ/G1C compatible DU
- renesas,du-r8a774a1 # for RZ/G2M compatible DU
- renesas,du-r8a774b1 # for RZ/G2N compatible DU
- renesas,du-r8a774c0 # for RZ/G2E compatible DU
- renesas,du-r8a774e1 # for RZ/G2H compatible DU
- renesas,du-r8a7779 # for R-Car H1 compatible DU
- renesas,du-r8a7790 # for R-Car H2 compatible DU
- renesas,du-r8a7791 # for R-Car M2-W compatible DU
- renesas,du-r8a7792 # for R-Car V2H compatible DU
- renesas,du-r8a7793 # for R-Car M2-N compatible DU
- renesas,du-r8a7794 # for R-Car E2 compatible DU
- renesas,du-r8a7795 # for R-Car H3 compatible DU
- renesas,du-r8a7796 # for R-Car M3-W compatible DU
- renesas,du-r8a77961 # for R-Car M3-W+ compatible DU
- renesas,du-r8a77965 # for R-Car M3-N compatible DU
- renesas,du-r8a77970 # for R-Car V3M compatible DU
- renesas,du-r8a77980 # for R-Car V3H compatible DU
- renesas,du-r8a77990 # for R-Car E3 compatible DU
- renesas,du-r8a77995 # for R-Car D3 compatible DU
reg:
maxItems: 1
# See compatible-specific constraints below.
clocks: true
clock-names: true
interrupts:
description: Interrupt specifiers, one per DU channel
resets: true
reset-names: true
power-domains:
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/port
description: |
The connections to the DU output video ports are modeled using the OF
graph bindings specified in Documentation/devicetree/bindings/graph.txt.
The number of ports and their assignment are model-dependent. Each port
shall have a single endpoint.
patternProperties:
"^port@[0-3]$":
$ref: /schemas/graph.yaml#/properties/port
unevaluatedProperties: false
required:
- port@0
- port@1
unevaluatedProperties: false
renesas,cmms:
$ref: "/schemas/types.yaml#/definitions/phandle-array"
description:
A list of phandles to the CMM instances present in the SoC, one for each
available DU channel.
renesas,vsps:
$ref: "/schemas/types.yaml#/definitions/phandle-array"
description:
A list of phandle and channel index tuples to the VSPs that handle the
memory interfaces for the DU channels. The phandle identifies the VSP
instance that serves the DU channel, and the channel index identifies
the LIF instance in that VSP.
required:
- compatible
- reg
- clocks
- interrupts
- resets
- ports
allOf:
- if:
properties:
compatible:
contains:
const: renesas,du-r8a7779
then:
properties:
clocks:
minItems: 1
maxItems: 3
items:
- description: Functional clock
- description: DU_DOTCLKIN0 input clock
- description: DU_DOTCLKIN1 input clock
clock-names:
minItems: 1
maxItems: 3
items:
- const: du.0
- pattern: '^dclkin\.[01]$'
- pattern: '^dclkin\.[01]$'
interrupts:
maxItems: 1
resets:
maxItems: 1
ports:
properties:
port@0:
description: DPAD 0
port@1:
description: DPAD 1
# port@2 is TCON, not supported yet
port@2: false
port@3: false
required:
- port@0
- port@1
required:
- interrupts
- if:
properties:
compatible:
contains:
enum:
- renesas,du-r8a7743
- renesas,du-r8a7744
- renesas,du-r8a7791
- renesas,du-r8a7793
then:
properties:
clocks:
minItems: 2
maxItems: 4
items:
- description: Functional clock for DU0
- description: Functional clock for DU1
- description: DU_DOTCLKIN0 input clock
- description: DU_DOTCLKIN1 input clock
clock-names:
minItems: 2
maxItems: 4
items:
- const: du.0
- const: du.1
- pattern: '^dclkin\.[01]$'
- pattern: '^dclkin\.[01]$'
interrupts:
maxItems: 2
resets:
maxItems: 1
reset-names:
items:
- const: du.0
ports:
properties:
port@0:
description: DPAD 0
port@1:
description: LVDS 0
# port@2 is TCON, not supported yet
port@2: false
port@3: false
required:
- port@0
- port@1
required:
- clock-names
- interrupts
- resets
- reset-names
- if:
properties:
compatible:
contains:
enum:
- renesas,du-r8a7745
- renesas,du-r8a7792
then:
properties:
clocks:
minItems: 2
maxItems: 4
items:
- description: Functional clock for DU0
- description: Functional clock for DU1
- description: DU_DOTCLKIN0 input clock
- description: DU_DOTCLKIN1 input clock
clock-names:
minItems: 2
maxItems: 4
items:
- const: du.0
- const: du.1
- pattern: '^dclkin\.[01]$'
- pattern: '^dclkin\.[01]$'
interrupts:
maxItems: 2
resets:
maxItems: 1
reset-names:
items:
- const: du.0
ports:
properties:
port@0:
description: DPAD 0
port@1:
description: DPAD 1
port@2: false
port@3: false
required:
- port@0
- port@1
required:
- clock-names
- interrupts
- resets
- reset-names
- if:
properties:
compatible:
contains:
enum:
- renesas,du-r8a7794
then:
properties:
clocks:
minItems: 2
maxItems: 4
items:
- description: Functional clock for DU0
- description: Functional clock for DU1
- description: DU_DOTCLKIN0 input clock
- description: DU_DOTCLKIN1 input clock
clock-names:
minItems: 2
maxItems: 4
items:
- const: du.0
- const: du.1
- pattern: '^dclkin\.[01]$'
- pattern: '^dclkin\.[01]$'
interrupts:
maxItems: 2
resets:
maxItems: 1
reset-names:
items:
- const: du.0
ports:
properties:
port@0:
description: DPAD 0
port@1:
description: DPAD 1
# port@2 is TCON, not supported yet
port@2: false
port@3: false
required:
- port@0
- port@1
required:
- clock-names
- interrupts
- resets
- reset-names
- if:
properties:
compatible:
contains:
enum:
- renesas,du-r8a77470
then:
properties:
clocks:
minItems: 2
maxItems: 4
items:
- description: Functional clock for DU0
- description: Functional clock for DU1
- description: DU_DOTCLKIN0 input clock
- description: DU_DOTCLKIN1 input clock
clock-names:
minItems: 2
maxItems: 4
items:
- const: du.0
- const: du.1
- pattern: '^dclkin\.[01]$'
- pattern: '^dclkin\.[01]$'
interrupts:
maxItems: 2
resets:
maxItems: 1
reset-names:
items:
- const: du.0
ports:
properties:
port@0:
description: DPAD 0
port@1:
description: DPAD 1
port@2:
description: LVDS 0
# port@3 is DVENC, not supported yet
port@3: false
required:
- port@0
- port@1
- port@2
required:
- clock-names
- interrupts
- resets
- reset-names
- if:
properties:
compatible:
contains:
enum:
- renesas,du-r8a7742
- renesas,du-r8a7790
then:
properties:
clocks:
minItems: 3
maxItems: 6
items:
- description: Functional clock for DU0
- description: Functional clock for DU1
- description: Functional clock for DU2
- description: DU_DOTCLKIN0 input clock
- description: DU_DOTCLKIN1 input clock
- description: DU_DOTCLKIN2 input clock
clock-names:
minItems: 3
maxItems: 6
items:
- const: du.0
- const: du.1
- const: du.2
- pattern: '^dclkin\.[012]$'
- pattern: '^dclkin\.[012]$'
- pattern: '^dclkin\.[012]$'
interrupts:
maxItems: 3
resets:
maxItems: 1
reset-names:
items:
- const: du.0
ports:
properties:
port@0:
description: DPAD 0
port@1:
description: LVDS 0
port@2:
description: LVDS 1
# port@3 is TCON, not supported yet
port@3: false
required:
- port@0
- port@1
- port@2
required:
- clock-names
- interrupts
- resets
- reset-names
- if:
properties:
compatible:
contains:
enum:
- renesas,du-r8a7795
then:
properties:
clocks:
minItems: 4
maxItems: 8
items:
- description: Functional clock for DU0
- description: Functional clock for DU1
- description: Functional clock for DU2
- description: Functional clock for DU4
- description: DU_DOTCLKIN0 input clock
- description: DU_DOTCLKIN1 input clock
- description: DU_DOTCLKIN2 input clock
- description: DU_DOTCLKIN3 input clock
clock-names:
minItems: 4
maxItems: 8
items:
- const: du.0
- const: du.1
- const: du.2
- const: du.3
- pattern: '^dclkin\.[0123]$'
- pattern: '^dclkin\.[0123]$'
- pattern: '^dclkin\.[0123]$'
- pattern: '^dclkin\.[0123]$'
interrupts:
maxItems: 4
resets:
maxItems: 2
reset-names:
items:
- const: du.0
- const: du.2
ports:
properties:
port@0:
description: DPAD 0
port@1:
description: HDMI 0
port@2:
description: HDMI 1
port@3:
description: LVDS 0
required:
- port@0
- port@1
- port@2
- port@3
renesas,cmms:
minItems: 4
renesas,vsps:
minItems: 4
required:
- clock-names
- interrupts
- resets
- reset-names
- renesas,vsps
- if:
properties:
compatible:
contains:
enum:
- renesas,du-r8a774a1
- renesas,du-r8a7796
- renesas,du-r8a77961
then:
properties:
clocks:
minItems: 3
maxItems: 6
items:
- description: Functional clock for DU0
- description: Functional clock for DU1
- description: Functional clock for DU2
- description: DU_DOTCLKIN0 input clock
- description: DU_DOTCLKIN1 input clock
- description: DU_DOTCLKIN2 input clock
clock-names:
minItems: 3
maxItems: 6
items:
- const: du.0
- const: du.1
- const: du.2
- pattern: '^dclkin\.[012]$'
- pattern: '^dclkin\.[012]$'
- pattern: '^dclkin\.[012]$'
interrupts:
maxItems: 3
resets:
maxItems: 2
reset-names:
items:
- const: du.0
- const: du.2
ports:
properties:
port@0:
description: DPAD 0
port@1:
description: HDMI 0
port@2:
description: LVDS 0
port@3: false
required:
- port@0
- port@1
- port@2
renesas,cmms:
minItems: 3
renesas,vsps:
minItems: 3
required:
- clock-names
- interrupts
- resets
- reset-names
- renesas,vsps
- if:
properties:
compatible:
contains:
enum:
- renesas,du-r8a774b1
- renesas,du-r8a774e1
- renesas,du-r8a77965
then:
properties:
clocks:
minItems: 3
maxItems: 6
items:
- description: Functional clock for DU0
- description: Functional clock for DU1
- description: Functional clock for DU3
- description: DU_DOTCLKIN0 input clock
- description: DU_DOTCLKIN1 input clock
- description: DU_DOTCLKIN3 input clock
clock-names:
minItems: 3
maxItems: 6
items:
- const: du.0
- const: du.1
- const: du.3
- pattern: '^dclkin\.[013]$'
- pattern: '^dclkin\.[013]$'
- pattern: '^dclkin\.[013]$'
interrupts:
maxItems: 3
resets:
maxItems: 2
reset-names:
items:
- const: du.0
- const: du.3
ports:
properties:
port@0:
description: DPAD 0
port@1:
description: HDMI 0
port@2:
description: LVDS 0
port@3: false
required:
- port@0
- port@1
- port@2
renesas,cmms:
minItems: 3
renesas,vsps:
minItems: 3
required:
- clock-names
- interrupts
- resets
- reset-names
- renesas,vsps
- if:
properties:
compatible:
contains:
enum:
- renesas,du-r8a77970
- renesas,du-r8a77980
then:
properties:
clocks:
minItems: 1
maxItems: 2
items:
- description: Functional clock for DU0
- description: DU_DOTCLKIN0 input clock
clock-names:
minItems: 1
maxItems: 2
items:
- const: du.0
- const: dclkin.0
interrupts:
maxItems: 1
resets:
maxItems: 1
reset-names:
items:
- const: du.0
ports:
properties:
port@0:
description: DPAD 0
port@1:
description: LVDS 0
port@2: false
port@3: false
required:
- port@0
- port@1
renesas,vsps:
minItems: 1
required:
- clock-names
- interrupts
- resets
- reset-names
- renesas,vsps
- if:
properties:
compatible:
contains:
enum:
- renesas,du-r8a774c0
- renesas,du-r8a77990
- renesas,du-r8a77995
then:
properties:
clocks:
minItems: 2
maxItems: 4
items:
- description: Functional clock for DU0
- description: Functional clock for DU1
- description: DU_DOTCLKIN0 input clock
- description: DU_DOTCLKIN1 input clock
clock-names:
minItems: 2
maxItems: 4
items:
- const: du.0
- const: du.1
- pattern: '^dclkin\.[01]$'
- pattern: '^dclkin\.[01]$'
interrupts:
maxItems: 2
resets:
maxItems: 1
reset-names:
items:
- const: du.0
ports:
properties:
port@0:
description: DPAD 0
port@1:
description: LVDS 0
port@2:
description: LVDS 1
# port@3 is TCON, not supported yet
port@3: false
required:
- port@0
- port@1
- port@2
renesas,cmms:
minItems: 2
renesas,vsps:
minItems: 2
required:
- clock-names
- interrupts
- resets
- reset-names
- renesas,vsps
additionalProperties: false
examples:
# R-Car H3 ES2.0 DU
- |
#include <dt-bindings/clock/renesas-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
display@feb00000 {
compatible = "renesas,du-r8a7795";
reg = <0xfeb00000 0x80000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&cpg CPG_MOD 721>;
clock-names = "du.0", "du.1", "du.2", "du.3";
resets = <&cpg 724>, <&cpg 722>;
reset-names = "du.0", "du.2";
renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>;
renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
endpoint {
remote-endpoint = <&adv7123_in>;
};
};
port@1 {
reg = <1>;
endpoint {
remote-endpoint = <&dw_hdmi0_in>;
};
};
port@2 {
reg = <2>;
endpoint {
remote-endpoint = <&dw_hdmi1_in>;
};
};
port@3 {
reg = <3>;
endpoint {
remote-endpoint = <&lvds0_in>;
};
};
};
};
...

156
Bindings/display/rockchip/rockchip,dw-hdmi.yaml Normal file
View File

@ -0,0 +1,156 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip DWC HDMI TX Encoder
maintainers:
- Mark Yao <markyao0591@gmail.com>
description: |
The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
with a companion PHY IP.
allOf:
- $ref: ../bridge/synopsys,dw-hdmi.yaml#
properties:
compatible:
enum:
- rockchip,rk3228-dw-hdmi
- rockchip,rk3288-dw-hdmi
- rockchip,rk3328-dw-hdmi
- rockchip,rk3399-dw-hdmi
reg-io-width:
const: 4
clocks:
minItems: 2
maxItems: 5
items:
- {}
- {}
# The next three clocks are all optional, but shall be specified in this
# order when present.
- description: The HDMI CEC controller main clock
- description: Power for GRF IO
- description: External clock for some HDMI PHY
clock-names:
minItems: 2
maxItems: 5
items:
- {}
- {}
- enum:
- cec
- grf
- vpll
- enum:
- grf
- vpll
- const: vpll
ddc-i2c-bus:
$ref: /schemas/types.yaml#/definitions/phandle
description:
The HDMI DDC bus can be connected to either a system I2C master or the
functionally-reduced I2C master contained in the DWC HDMI. When connected
to a system I2C master this property contains a phandle to that I2C
master controller.
phys:
maxItems: 1
description: The HDMI PHY
phy-names:
const: hdmi
pinctrl-names:
description:
The unwedge pinctrl entry shall drive the DDC SDA line low. This is
intended to work around a hardware errata that can cause the DDC I2C
bus to be wedged.
items:
- const: default
- const: unwedge
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: Input of the DWC HDMI TX
properties:
endpoint@0:
$ref: /schemas/graph.yaml#/properties/endpoint
description: Connection to the VOPB
endpoint@1:
$ref: /schemas/graph.yaml#/properties/endpoint
description: Connection to the VOPL
required:
- endpoint@0
- endpoint@1
required:
- port
rockchip,grf:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle to the GRF to mux vopl/vopb.
required:
- compatible
- reg
- reg-io-width
- clocks
- clock-names
- interrupts
- ports
- rockchip,grf
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/rk3288-cru.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
hdmi: hdmi@ff980000 {
compatible = "rockchip,rk3288-dw-hdmi";
reg = <0xff980000 0x20000>;
reg-io-width = <4>;
ddc-i2c-bus = <&i2c5>;
rockchip,grf = <&grf>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
clock-names = "iahb", "isfr";
ports {
port {
#address-cells = <1>;
#size-cells = <0>;
hdmi_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_hdmi>;
};
hdmi_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_hdmi>;
};
};
};
};
...

5
Bindings/display/simple-framebuffer.yaml
View File

@ -54,6 +54,7 @@ properties:
compatible:
items:
- enum:
- apple,simple-framebuffer
- allwinner,simple-framebuffer
- amlogic,simple-framebuffer
- const: simple-framebuffer
@ -84,9 +85,13 @@ properties:
Format of the framebuffer:
* `a8b8g8r8` - 32-bit pixels, d[31:24]=a, d[23:16]=b, d[15:8]=g, d[7:0]=r
* `r5g6b5` - 16-bit pixels, d[15:11]=r, d[10:5]=g, d[4:0]=b
* `x2r10g10b10` - 32-bit pixels, d[29:20]=r, d[19:10]=g, d[9:0]=b
* `x8r8g8b8` - 32-bit pixels, d[23:16]=r, d[15:8]=g, d[7:0]=b
enum:
- a8b8g8r8
- r5g6b5
- x2r10g10b10
- x8r8g8b8
display:
$ref: /schemas/types.yaml#/definitions/phandle

3
Bindings/dma/qcom,gpi.yaml
View File

@ -20,6 +20,7 @@ properties:
compatible:
enum:
- qcom,sdm845-gpi-dma
- qcom,sm8150-gpi-dma
reg:
maxItems: 1
@ -64,7 +65,7 @@ examples:
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/dma/qcom-gpi.h>
gpi_dma0: dma-controller@800000 {
compatible = "qcom,gpi-dma";
compatible = "qcom,sdm845-gpi-dma";
#dma-cells = <3>;
reg = <0x00800000 0x60000>;
iommus = <&apps_smmu 0x0016 0x0>;

62
Bindings/extcon/qcom,pm8941-misc.yaml Normal file
View File

@ -0,0 +1,62 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/extcon/qcom,pm8941-misc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. PM8941 USB ID Extcon device
maintainers:
- Guru Das Srinagesh <gurus@codeaurora.org>
description: |
Some Qualcomm PMICs have a "misc" module that can be used to detect when
the USB ID pin has been pulled low or high.
properties:
compatible:
items:
- const: qcom,pm8941-misc
reg:
maxItems: 1
interrupts:
minItems: 1
maxItems: 2
interrupt-names:
minItems: 1
items:
- const: usb_id
- const: usb_vbus
required:
- compatible
- reg
- interrupts
- interrupt-names
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
pmic {
#address-cells = <1>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
usb_id: misc@900 {
compatible = "qcom,pm8941-misc";
reg = <0x900>;
interrupts = <0x0 0x9 0 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "usb_id";
};
};
usb-controller {
extcon = <&usb_id>;
};

2
Bindings/firmware/qcom,scm.txt
View File

@ -20,7 +20,9 @@ Required properties:
* "qcom,scm-msm8996"
* "qcom,scm-msm8998"
* "qcom,scm-sc7180"
* "qcom,scm-sc7280"
* "qcom,scm-sdm845"
* "qcom,scm-sdx55"
* "qcom,scm-sm8150"
* "qcom,scm-sm8250"
* "qcom,scm-sm8350"

167
Bindings/fpga/fpga-region.txt
View File

@ -245,36 +245,31 @@ Base tree contains:
Overlay contains:
/dts-v1/ /plugin/;
/ {
fragment@0 {
target = <&fpga_region0>;
#address-cells = <1>;
#size-cells = <1>;
__overlay__ {
#address-cells = <1>;
#size-cells = <1>;
/dts-v1/;
/plugin/;
firmware-name = "soc_system.rbf";
fpga-bridges = <&fpga_bridge1>;
ranges = <0x20000 0xff200000 0x100000>,
<0x0 0xc0000000 0x20000000>;
&fpga_region0 {
#address-cells = <1>;
#size-cells = <1>;
gpio@10040 {
compatible = "altr,pio-1.0";
reg = <0x10040 0x20>;
altr,ngpio = <4>;
#gpio-cells = <2>;
clocks = <2>;
gpio-controller;
};
firmware-name = "soc_system.rbf";
fpga-bridges = <&fpga_bridge1>;
ranges = <0x20000 0xff200000 0x100000>,
<0x0 0xc0000000 0x20000000>;
onchip-memory {
device_type = "memory";
compatible = "altr,onchipmem-15.1";
reg = <0x0 0x10000>;
};
};
gpio@10040 {
compatible = "altr,pio-1.0";
reg = <0x10040 0x20>;
altr,ngpio = <4>;
#gpio-cells = <2>;
clocks = <2>;
gpio-controller;
};
onchip-memory {
device_type = "memory";
compatible = "altr,onchipmem-15.1";
reg = <0x0 0x10000>;
};
};
@ -371,25 +366,22 @@ Live Device Tree contains:
};
DT Overlay contains:
/dts-v1/ /plugin/;
/ {
fragment@0 {
target = <&fpga_region0>;
/dts-v1/;
/plugin/;
&fpga_region0 {
#address-cells = <1>;
#size-cells = <1>;
__overlay__ {
#address-cells = <1>;
#size-cells = <1>;
firmware-name = "zynq-gpio.bin";
firmware-name = "zynq-gpio.bin";
gpio1: gpio@40000000 {
compatible = "xlnx,xps-gpio-1.00.a";
reg = <0x40000000 0x10000>;
gpio-controller;
#gpio-cells = <0x2>;
xlnx,gpio-width= <0x6>;
};
gpio1: gpio@40000000 {
compatible = "xlnx,xps-gpio-1.00.a";
reg = <0x40000000 0x10000>;
gpio-controller;
#gpio-cells = <0x2>;
xlnx,gpio-width= <0x6>;
};
};
@ -402,41 +394,37 @@ This example programs the FPGA to have two regions that can later be partially
configured. Each region has its own bridge in the FPGA fabric.
DT Overlay contains:
/dts-v1/ /plugin/;
/ {
fragment@0 {
target = <&fpga_region0>;
#address-cells = <1>;
#size-cells = <1>;
__overlay__ {
#address-cells = <1>;
#size-cells = <1>;
firmware-name = "base.rbf";
/dts-v1/;
/plugin/;
fpga-bridge@4400 {
compatible = "altr,freeze-bridge-controller";
reg = <0x4400 0x10>;
&fpga_region0 {
#address-cells = <1>;
#size-cells = <1>;
fpga_region1: fpga-region1 {
compatible = "fpga-region";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
};
};
firmware-name = "base.rbf";
fpga-bridge@4420 {
compatible = "altr,freeze-bridge-controller";
reg = <0x4420 0x10>;
fpga-bridge@4400 {
compatible = "altr,freeze-bridge-controller";
reg = <0x4400 0x10>;
fpga_region2: fpga-region2 {
compatible = "fpga-region";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
};
};
fpga_region1: fpga-region1 {
compatible = "fpga-region";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
};
};
fpga-bridge@4420 {
compatible = "altr,freeze-bridge-controller";
reg = <0x4420 0x10>;
fpga_region2: fpga-region2 {
compatible = "fpga-region";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
};
};
};
@ -451,28 +439,23 @@ differences are that the FPGA is partially reconfigured due to the
"partial-fpga-config" boolean and the only bridge that is controlled during
programming is the FPGA based bridge of fpga_region1.
/dts-v1/ /plugin/;
/ {
fragment@0 {
target = <&fpga_region1>;
#address-cells = <1>;
#size-cells = <1>;
__overlay__ {
#address-cells = <1>;
#size-cells = <1>;
/dts-v1/;
/plugin/;
firmware-name = "soc_image2.rbf";
partial-fpga-config;
&fpga_region1 {
#address-cells = <1>;
#size-cells = <1>;
gpio@10040 {
compatible = "altr,pio-1.0";
reg = <0x10040 0x20>;
clocks = <0x2>;
altr,ngpio = <0x4>;
#gpio-cells = <0x2>;
gpio-controller;
};
};
firmware-name = "soc_image2.rbf";
partial-fpga-config;
gpio@10040 {
compatible = "altr,pio-1.0";
reg = <0x10040 0x20>;
clocks = <0x2>;
altr,ngpio = <0x4>;
#gpio-cells = <0x2>;
gpio-controller;
};
};

24
Bindings/fpga/xilinx-pr-decoupler.txt
View File

@ -7,13 +7,24 @@ changes from passing through the bridge. The controller can also
couple / enable the bridges which allows traffic to pass through the
bridge normally.
Xilinx LogiCORE Dynamic Function eXchange(DFX) AXI shutdown manager
Softcore is compatible with the Xilinx LogiCORE pr-decoupler.
The Dynamic Function eXchange AXI shutdown manager prevents AXI traffic
from passing through the bridge. The controller safely handles AXI4MM
and AXI4-Lite interfaces on a Reconfigurable Partition when it is
undergoing dynamic reconfiguration, preventing the system deadlock
that can occur if AXI transactions are interrupted by DFX
The Driver supports only MMIO handling. A PR region can have multiple
PR Decouplers which can be handled independently or chained via decouple/
decouple_status signals.
Required properties:
- compatible : Should contain "xlnx,pr-decoupler-1.00" followed by
"xlnx,pr-decoupler"
"xlnx,pr-decoupler" or
"xlnx,dfx-axi-shutdown-manager-1.00" followed by
"xlnx,dfx-axi-shutdown-manager"
- regs : base address and size for decoupler module
- clocks : input clock to IP
- clock-names : should contain "aclk"
@ -22,6 +33,7 @@ See Documentation/devicetree/bindings/fpga/fpga-region.txt and
Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
Example:
Partial Reconfig Decoupler:
fpga-bridge@100000450 {
compatible = "xlnx,pr-decoupler-1.00",
"xlnx-pr-decoupler";
@ -30,3 +42,13 @@ Example:
clock-names = "aclk";
bridge-enable = <0>;
};
Dynamic Function eXchange AXI shutdown manager:
fpga-bridge@100000450 {
compatible = "xlnx,dfx-axi-shutdown-manager-1.00",
"xlnx,dfx-axi-shutdown-manager";
regs = <0x10000045 0x10>;
clocks = <&clkc 15>;
clock-names = "aclk";
bridge-enable = <0>;
};

86
Bindings/gpio/brcm,bcm6345-gpio.yaml Normal file
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@ -0,0 +1,86 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/brcm,bcm6345-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM6345 GPIO controller
maintainers:
- Álvaro Fernández Rojas <noltari@gmail.com>
- Jonas Gorski <jonas.gorski@gmail.com>
description: |+
Bindings for Broadcom's BCM63xx memory-mapped GPIO controllers.
These bindings can be used on any BCM63xx SoC. However, BCM6338 and BCM6345
are the only ones which don't need a pinctrl driver.
BCM6338 have 8-bit data and dirout registers, where GPIO state can be read
and/or written, and the direction changed from input to output.
BCM6345 have 16-bit data and dirout registers, where GPIO state can be read
and/or written, and the direction changed from input to output.
BCM6318, BCM6328, BCM6358, BCM6362, BCM6368 and BCM63268 have 32-bit data
and dirout registers, where GPIO state can be read and/or written, and the
direction changed from input to output.
properties:
compatible:
enum:
- brcm,bcm6318-gpio
- brcm,bcm6328-gpio
- brcm,bcm6345-gpio
- brcm,bcm6358-gpio
- brcm,bcm6362-gpio
- brcm,bcm6368-gpio
- brcm,bcm63268-gpio
gpio-controller: true
"#gpio-cells":
const: 2
gpio-ranges:
maxItems: 1
native-endian: true
reg:
maxItems: 2
reg-names:
items:
- const: dirout
- const: dat
required:
- compatible
- reg
- reg-names
- gpio-controller
- '#gpio-cells'
additionalProperties: false
examples:
- |
gpio@fffe0406 {
compatible = "brcm,bcm6345-gpio";
reg-names = "dirout", "dat";
reg = <0xfffe0406 2>, <0xfffe040a 2>;
native-endian;
gpio-controller;
#gpio-cells = <2>;
};
- |
gpio@0 {
compatible = "brcm,bcm63268-gpio";
reg-names = "dirout", "dat";
reg = <0x0 0x8>, <0x8 0x8>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 52>;
#gpio-cells = <2>;
};

77
Bindings/gpio/fairchild,74hc595.yaml Normal file
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@ -0,0 +1,77 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/fairchild,74hc595.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Generic 8-bit shift register
maintainers:
- Maxime Ripard <mripard@kernel.org>
properties:
compatible:
enum:
- fairchild,74hc595
- nxp,74lvc594
reg:
maxItems: 1
gpio-controller: true
'#gpio-cells':
description:
The second cell is only used to specify the GPIO polarity.
const: 2
registers-number:
description: Number of daisy-chained shift registers
enable-gpios:
description: GPIO connected to the OE (Output Enable) pin.
maxItems: 1
spi-max-frequency: true
patternProperties:
"^(hog-[0-9]+|.+-hog(-[0-9]+)?)$":
type: object
properties:
gpio-hog: true
gpios: true
output-high: true
output-low: true
line-name: true
required:
- gpio-hog
- gpios
additionalProperties: false
required:
- compatible
- reg
- gpio-controller
- '#gpio-cells'
- registers-number
additionalProperties: false
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
gpio5: gpio5@0 {
compatible = "fairchild,74hc595";
reg = <0>;
gpio-controller;
#gpio-cells = <2>;
registers-number = <4>;
spi-max-frequency = <100000>;
};
};

78
Bindings/gpio/realtek,otto-gpio.yaml Normal file
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@ -0,0 +1,78 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/realtek,otto-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Realtek Otto GPIO controller
maintainers:
- Sander Vanheule <sander@svanheule.net>
- Bert Vermeulen <bert@biot.com>
description: |
Realtek's GPIO controller on their MIPS switch SoCs (Otto platform) consists
of two banks of 32 GPIOs. These GPIOs can generate edge-triggered interrupts.
Each bank's interrupts are cascased into one interrupt line on the parent
interrupt controller, if provided.
This binding allows defining a single bank in the devicetree. The interrupt
controller is not supported on the fallback compatible name, which only
allows for GPIO port use.
properties:
$nodename:
pattern: "^gpio@[0-9a-f]+$"
compatible:
items:
- enum:
- realtek,rtl8380-gpio
- realtek,rtl8390-gpio
- const: realtek,otto-gpio
reg:
maxItems: 1
"#gpio-cells":
const: 2
gpio-controller: true
ngpios:
minimum: 1
maximum: 32
interrupt-controller: true
"#interrupt-cells":
const: 2
interrupts:
maxItems: 1
required:
- compatible
- reg
- "#gpio-cells"
- gpio-controller
additionalProperties: false
dependencies:
interrupt-controller: [ interrupts ]
examples:
- |
gpio@3500 {
compatible = "realtek,rtl8380-gpio", "realtek,otto-gpio";
reg = <0x3500 0x1c>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <24>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&rtlintc>;
interrupts = <23>;
};
...

82
Bindings/gpio/rockchip,gpio-bank.yaml Normal file
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@ -0,0 +1,82 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/rockchip,gpio-bank.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip GPIO bank
maintainers:
- Heiko Stuebner <heiko@sntech.de>
properties:
compatible:
enum:
- rockchip,gpio-bank
- rockchip,rk3188-gpio-bank0
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
gpio-controller: true
"#gpio-cells":
const: 2
interrupt-controller: true
"#interrupt-cells":
const: 2
required:
- compatible
- reg
- interrupts
- clocks
- gpio-controller
- "#gpio-cells"
- interrupt-controller
- "#interrupt-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
pinctrl: pinctrl {
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio0: gpio@2000a000 {
compatible = "rockchip,rk3188-gpio-bank0";
reg = <0x2000a000 0x100>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates8 9>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio@2003c000 {
compatible = "rockchip,gpio-bank";
reg = <0x2003c000 0x100>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates8 10>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};

3
Bindings/gpio/socionext,uniphier-gpio.yaml
View File

@ -43,8 +43,7 @@ properties:
gpio-ranges: true
gpio-ranges-group-names:
$ref: /schemas/types.yaml#/definitions/string-array
gpio-ranges-group-names: true
socionext,interrupt-ranges:
description: |

2
Bindings/gpu/arm,mali-bifrost.yaml
View File

@ -69,6 +69,8 @@ properties:
where voltage is in V, frequency is in MHz.
dma-coherent: true
required:
- compatible
- reg

2
Bindings/hwmon/ti,ads7828.yaml
View File

@ -49,7 +49,7 @@ examples:
#size-cells = <0>;
adc@48 {
comatible = "ti,ads7828";
compatible = "ti,ads7828";
reg = <0x48>;
vref-supply = <&vref>;
ti,differential-input;

98
Bindings/i2c/i2c-mpc.yaml Normal file
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@ -0,0 +1,98 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/i2c-mpc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: I2C-Bus adapter for MPC824x/83xx/85xx/86xx/512x/52xx SoCs
maintainers:
- Chris Packham <chris.packham@alliedtelesis.co.nz>
allOf:
- $ref: /schemas/i2c/i2c-controller.yaml#
properties:
compatible:
oneOf:
- items:
- enum:
- mpc5200-i2c
- fsl,mpc5200-i2c
- fsl,mpc5121-i2c
- fsl,mpc8313-i2c
- fsl,mpc8543-i2c
- fsl,mpc8544-i2c
- const: fsl-i2c
- items:
- const: fsl,mpc5200b-i2c
- const: fsl,mpc5200-i2c
- const: fsl-i2c
reg:
maxItems: 1
interrupts:
maxItems: 1
fsl,preserve-clocking:
$ref: /schemas/types.yaml#/definitions/flag
description: |
if defined, the clock settings from the bootloader are
preserved (not touched)
fsl,timeout:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
I2C bus timeout in microseconds
fsl,i2c-erratum-a004447:
$ref: /schemas/types.yaml#/definitions/flag
description: |
Indicates the presence of QorIQ erratum A-004447, which
says that the standard i2c recovery scheme mechanism does
not work and an alternate implementation is needed.
required:
- compatible
- reg
- interrupts
unevaluatedProperties: false
examples:
- |
/* MPC5121 based board */
i2c@1740 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5121-i2c", "fsl-i2c";
reg = <0x1740 0x20>;
interrupts = <11 0x8>;
interrupt-parent = <&ipic>;
clock-frequency = <100000>;
};
/* MPC5200B based board */
i2c@3d00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5200b-i2c", "fsl,mpc5200-i2c", "fsl-i2c";
reg = <0x3d00 0x40>;
interrupts = <2 15 0>;
interrupt-parent = <&mpc5200_pic>;
fsl,preserve-clocking;
};
/* MPC8544 base board */
i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc8544-i2c", "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
clock-frequency = <400000>;
fsl,timeout = <10000>;
};
...

2
Bindings/i2c/xlnx,xps-iic-2.00.a.yaml
View File

@ -4,7 +4,7 @@
$id: "http://devicetree.org/schemas/i2c/xlnx,xps-iic-2.00.a.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: ilinx IIC controller Device Tree Bindings
title: Xilinx IIC controller Device Tree Bindings
maintainers:
- info@mocean-labs.com

6
Bindings/i3c/cdns,i3c-master.txt
View File

@ -10,19 +10,19 @@ Required properties:
- reg: I3C master registers
Mandatory properties defined by the generic binding (see
Documentation/devicetree/bindings/i3c/i3c.txt for more details):
Documentation/devicetree/bindings/i3c/i3c.yaml for more details):
- #address-cells: shall be set to 1
- #size-cells: shall be set to 0
Optional properties defined by the generic binding (see
Documentation/devicetree/bindings/i3c/i3c.txt for more details):
Documentation/devicetree/bindings/i3c/i3c.yaml for more details):
- i2c-scl-hz
- i3c-scl-hz
I3C device connected on the bus follow the generic description (see
Documentation/devicetree/bindings/i3c/i3c.txt for more details).
Documentation/devicetree/bindings/i3c/i3c.yaml for more details).
Example:

7
Bindings/i3c/i3c.yaml
View File

@ -157,9 +157,10 @@ examples:
i2c-scl-hz = <100000>;
/* I2C device. */
nunchuk: nunchuk@52 {
compatible = "nintendo,nunchuk";
reg = <0x52 0x0 0x10>;
eeprom@57 {
compatible = "atmel,24c01";
reg = <0x57 0x0 0x10>;
pagesize = <0x8>;
};
/* I3C device with a static I2C address. */

2
Bindings/i3c/silvaco,i3c-master.yaml
View File

@ -49,7 +49,7 @@ additionalProperties: true
examples:
- |
i3c-master@a0000000 {
compatible = "silvaco,i3c-master";
compatible = "silvaco,i3c-master-v1";
clocks = <&zynqmp_clk 71>, <&fclk>, <&sclk>;
clock-names = "pclk", "fast_clk", "slow_clk";
interrupt-parent = <&gic>;

6
Bindings/i3c/snps,dw-i3c-master.txt
View File

@ -9,19 +9,19 @@ Required properties:
- reg: Offset and length of I3C master registers
Mandatory properties defined by the generic binding (see
Documentation/devicetree/bindings/i3c/i3c.txt for more details):
Documentation/devicetree/bindings/i3c/i3c.yaml for more details):
- #address-cells: shall be set to 3
- #size-cells: shall be set to 0
Optional properties defined by the generic binding (see
Documentation/devicetree/bindings/i3c/i3c.txt for more details):
Documentation/devicetree/bindings/i3c/i3c.yaml for more details):
- i2c-scl-hz
- i3c-scl-hz
I3C device connected on the bus follow the generic description (see
Documentation/devicetree/bindings/i3c/i3c.txt for more details).
Documentation/devicetree/bindings/i3c/i3c.yaml for more details).
Example:

68
Bindings/iio/accel/bosch,bmi088.yaml Normal file
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@ -0,0 +1,68 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/accel/bosch,bmi088.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Bosch BMI088 IMU accelerometer part
maintainers:
- Mike Looijmans <mike.looijmans@topic.nl>
description: |
Acceleration part of the IMU sensor with an SPI interface
Specifications about the sensor can be found at:
https://www.bosch-sensortec.com/media/boschsensortec/downloads/datasheets/bst-bmi088-ds001.pdf
properties:
compatible:
enum:
- bosch,bmi088-accel
reg:
maxItems: 1
spi-max-frequency: true
vdd-supply: true
vddio-supply: true
interrupts:
minItems: 1
maxItems: 2
description: |
Type should be either IRQ_TYPE_LEVEL_HIGH or IRQ_TYPE_LEVEL_LOW.
Two configurable interrupt lines exist.
interrupt-names:
description: Specify which interrupt line is in use.
items:
enum:
- INT1
- INT2
minItems: 1
maxItems: 2
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
spi {
#address-cells = <1>;
#size-cells = <0>;
bmi088-accel@1 {
compatible = "bosch,bmi088-accel";
reg = <1>;
spi-max-frequency = <10000000>;
interrupt-parent = <&gpio6>;
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "INT2";
};
};
...

5
Bindings/iio/adc/brcm,iproc-static-adc.yaml
View File

@ -53,11 +53,6 @@ examples:
#address-cells = <1>;
#size-cells = <1>;
ts_adc_syscon: ts_adc_syscon@180a6000 {
compatible = "brcm,iproc-ts-adc-syscon","syscon";
reg = <0x180a6000 0xc30>;
};
adc {
compatible = "brcm,iproc-static-adc";
adc-syscon = <&ts_adc_syscon>;

1
Bindings/iio/adc/mediatek,mt2701-auxadc.yaml
View File

@ -34,6 +34,7 @@ properties:
- items:
- enum:
- mediatek,mt8183-auxadc
- mediatek,mt8195-auxadc
- mediatek,mt8516-auxadc
- const: mediatek,mt8173-auxadc

1
Bindings/iio/adc/st,stm32-dfsdm-adc.yaml
View File

@ -102,7 +102,6 @@ patternProperties:
st,adc-channel-names:
description: List of single-ended channel names.
$ref: /schemas/types.yaml#/definitions/string-array
st,filter-order:
description: |

181
Bindings/iio/adc/ti,ads131e08.yaml Normal file
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@ -0,0 +1,181 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/adc/ti,ads131e08.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments ADS131E0x 4-, 6- and 8-Channel ADCs
maintainers:
- Tomislav Denis <tomislav.denis@avl.com>
description: |
The ADS131E0x are a family of multichannel, simultaneous sampling,
24-bit, delta-sigma, analog-to-digital converters (ADCs) with a
built-in programmable gain amplifier (PGA), internal reference
and an onboard oscillator.
The communication with ADC chip is via the SPI bus (mode 1).
https://www.ti.com/lit/ds/symlink/ads131e08.pdf
properties:
compatible:
enum:
- ti,ads131e04
- ti,ads131e06
- ti,ads131e08
reg:
maxItems: 1
spi-max-frequency: true
spi-cpha: true
clocks:
description: |
Device tree identifier to the clock source (2.048 MHz).
Note: clock source is selected using CLKSEL pin.
maxItems: 1
clock-names:
items:
- const: adc-clk
interrupts:
description: |
IRQ line for the ADC data ready.
maxItems: 1
vref-supply:
description: |
Optional external voltage reference. If not supplied, internal voltage
reference is used.
ti,vref-internal:
description: |
Select the internal voltage reference value.
0: 2.4V
1: 4.0V
If this field is left empty, 2.4V is selected.
Note: internal voltage reference is used only if vref-supply is not supplied.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
default: 0
'#address-cells':
const: 1
'#size-cells':
const: 0
required:
- compatible
- reg
- spi-cpha
- clocks
- clock-names
- interrupts
patternProperties:
"^channel@([0-7])$":
$ref: "adc.yaml"
type: object
description: |
Represents the external channels which are connected to the ADC.
properties:
reg:
description: |
The channel number.
Up to 4 channels, numbered from 0 to 3 for ti,ads131e04.
Up to 6 channels, numbered from 0 to 5 for ti,ads131e06.
Up to 8 channels, numbered from 0 to 7 for ti,ads131e08.
items:
minimum: 0
maximum: 7
ti,gain:
description: |
The PGA gain value for the channel.
If this field is left empty, PGA gain 1 is used.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 2, 4, 8, 12]
default: 1
ti,mux:
description: |
Channel input selection(muliplexer).
0: Normal input.
1: Input shorted to (VREFP + VREFN) / 2 (for offset or noise measurements).
3: MVDD (for supply measurement)
4: Temperature sensor
If this field is left empty, normal input is selected.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 3, 4]
default: 0
required:
- reg
additionalProperties: false
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
spi {
#address-cells = <1>;
#size-cells = <0>;
adc@0 {
compatible = "ti,ads131e08";
reg = <0>;
spi-max-frequency = <1000000>;
spi-cpha;
clocks = <&clk2048k>;
clock-names = "adc-clk";
interrupt-parent = <&gpio5>;
interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
vref-supply = <&adc_vref>;
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
reg = <0>;
};
channel@1 {
reg = <1>;
};
channel@2 {
reg = <2>;
ti,gain = <2>;
};
channel@3 {
reg = <3>;
};
channel@4 {
reg = <4>;
};
channel@5 {
reg = <5>;
};
channel@6 {
reg = <6>;
};
channel@7 {
reg = <7>;
ti,mux = <4>;
};
};
};

69
Bindings/iio/cdc/adi,ad7150.yaml Normal file
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@ -0,0 +1,69 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/cdc/adi,ad7150.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog device AD7150 and similar capacitance to digital convertors.
maintainers:
- Jonathan Cameron <jic23@kernel.org>
properties:
compatible:
enum:
- adi,ad7150
- adi,ad7151
- adi,ad7156
reg:
maxItems: 1
vdd-supply: true
interrupts: true
allOf:
- if:
properties:
compatible:
contains:
enum:
- adi,ad7150
- adi,ad7156
then:
properties:
interrupts:
minItems: 2
maxItems: 2
- if:
properties:
compatible:
contains:
const: adi,ad7151
then:
properties:
interrupts:
minItems: 1
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
cdc@48 {
compatible = "adi,ad7150";
reg = <0x48>;
interrupts = <25 2>, <26 2>;
interrupt-parent = <&gpio>;
};
};
...

2
Bindings/iio/gyroscope/nxp,fxas21002c.yaml
View File

@ -83,7 +83,7 @@ examples:
#size-cells = <0>;
gyroscope@0 {
compatible = "nxp,fxas2102c";
compatible = "nxp,fxas21002c";
reg = <0x0>;
spi-max-frequency = <2000000>;

9
Bindings/iio/imu/adi,adis16475.yaml
View File

@ -71,15 +71,6 @@ properties:
minimum: 0
maximum: 3
adi,scaled-output-hz:
description:
This property must be present if the clock mode is scaled-sync through
clock-names property. In this mode, the input clock can have a range
of 1Hz to 128HZ which must be scaled to originate an allowable sample
rate. This property specifies that rate.
minimum: 1900
maximum: 2100
required:
- compatible
- reg

1
Bindings/iio/light/capella,cm3605.yaml
View File

@ -48,7 +48,6 @@ properties:
vdd-supply: true
capella,aset-resistance-ohms:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [50000, 100000, 300000, 600000]
description: >
Sensitivity calibration resistance. Note that calibration curves

4
Bindings/iio/light/upisemi,us5182.yaml
View File

@ -11,12 +11,12 @@ maintainers:
properties:
compatible:
const: upisemi,asd5182
const: upisemi,usd5182
reg:
maxItems: 1
upsemi,glass-coef:
upisemi,glass-coef:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
glass attenuation factor - compensation factor of resolution 1000

37
Bindings/iio/proximity/google,cros-ec-mkbp-proximity.yaml Normal file
View File

@ -0,0 +1,37 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/proximity/google,cros-ec-mkbp-proximity.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ChromeOS EC MKBP Proximity Sensor
maintainers:
- Stephen Boyd <swboyd@chromium.org>
- Benson Leung <bleung@chromium.org>
- Enric Balletbo i Serra <enric.balletbo@collabora.com>
description: |
Google's ChromeOS EC sometimes has the ability to detect user proximity.
This is implemented on the EC as near/far logic and exposed to the OS
via an MKBP switch bit.
properties:
compatible:
const: google,cros-ec-mkbp-proximity
label:
description: Name for proximity sensor
required:
- compatible
additionalProperties: false
examples:
- |
proximity {
compatible = "google,cros-ec-mkbp-proximity";
label = "proximity-wifi-lte";
};

1
Bindings/iio/st,st-sensors.yaml
View File

@ -66,6 +66,7 @@ properties:
- st,lis3mdl-magn
- st,lis2mdl
- st,lsm9ds1-magn
- st,iis2mdc
# Pressure sensors
- st,lps001wp-press
- st,lps25h-press

7
Bindings/index.rst
View File

@ -1,12 +1,9 @@
.. SPDX-License-Identifier: GPL-2.0
===========
Device Tree
===========
.. toctree::
:maxdepth: 1
ABI
submitting-patches
writing-bindings
writing-schema
submitting-patches

2
Bindings/infiniband/hisilicon-hns-roce.txt
View File

@ -1,7 +1,7 @@
Hisilicon RoCE DT description
Hisilicon RoCE engine is a part of network subsystem.
It works depending on other part of network wubsytem, such as, gmac and
It works depending on other part of network subsystem, such as gmac and
dsa fabric.
Additional properties are described here:

32
Bindings/input/atmel,maxtouch.yaml
View File

@ -39,6 +39,13 @@ properties:
(active low). The line must be flagged with
GPIO_ACTIVE_LOW.
wake-gpios:
maxItems: 1
description:
Optional GPIO specifier for the touchscreen's wake pin
(active low). The line must be flagged with
GPIO_ACTIVE_LOW.
linux,gpio-keymap:
$ref: /schemas/types.yaml#/definitions/uint32-array
description: |
@ -53,6 +60,29 @@ properties:
or experiment to determine which bit corresponds to which input. Use
KEY_RESERVED for unused padding values.
atmel,wakeup-method:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
The WAKE line is an active-low input that is used to wake up the touch
controller from deep-sleep mode before communication with the controller
could be started. This optional feature used to minimize current
consumption when the controller is in deep sleep mode. This feature is
relevant only to some controller families, like mXT1386 controller for
example.
The WAKE pin can be connected in one of the following ways:
1) left permanently low
2) connected to the I2C-compatible SCL pin
3) connected to a GPIO pin on the host
enum:
- 0 # ATMEL_MXT_WAKEUP_NONE
- 1 # ATMEL_MXT_WAKEUP_I2C_SCL
- 2 # ATMEL_MXT_WAKEUP_GPIO
default: 0
wakeup-source:
type: boolean
required:
- compatible
- reg
@ -63,6 +93,7 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/input/atmel-maxtouch.h>
#include <dt-bindings/gpio/gpio.h>
i2c {
#address-cells = <1>;
@ -75,6 +106,7 @@ examples:
reset-gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
vdda-supply = <&ab8500_ldo_aux2_reg>;
vdd-supply = <&ab8500_ldo_aux5_reg>;
atmel,wakeup-method = <ATMEL_MXT_WAKEUP_I2C_SCL>;
};
};

7
Bindings/input/input.yaml
View File

@ -32,6 +32,11 @@ properties:
Duration in seconds which the key should be kept pressed for device to
power off automatically. Device with key pressed shutdown feature can
specify this property.
$ref: /schemas/types.yaml#/definitions/uint32
reset-time-sec:
description:
Duration in seconds which the key should be kept pressed for device to
reset automatically. Device with key pressed reset feature can specify
this property.
additionalProperties: true

843
Bindings/input/iqs626a.yaml Normal file
View File

@ -0,0 +1,843 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/input/iqs626a.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Azoteq IQS626A Capacitive Touch Controller
maintainers:
- Jeff LaBundy <jeff@labundy.com>
description: |
The Azoteq IQS626A is a 14-channel capacitive touch controller that features
additional Hall-effect and inductive sensing capabilities.
Link to datasheet: https://www.azoteq.com/
allOf:
- $ref: touchscreen/touchscreen.yaml#
properties:
compatible:
const: azoteq,iqs626a
reg:
maxItems: 1
interrupts:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 0
azoteq,suspend-mode:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
default: 0
description: |
Specifies the power mode during suspend as follows:
0: Automatic (same as normal runtime, i.e. suspend/resume disabled)
1: Low power (all sensing at a reduced reporting rate)
2: Ultra-low power (ULP channel proximity sensing)
3: Halt (no sensing)
azoteq,clk-div:
type: boolean
description: Divides the device's core clock by a factor of 4.
azoteq,ulp-enable:
type: boolean
description:
Permits the device to automatically enter ultra-low-power mode from low-
power mode.
azoteq,ulp-update:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3, 4, 5, 6, 7]
default: 3
description: |
Specifies the rate at which the trackpad, generic and Hall channels are
updated during ultra-low-power mode as follows:
0: 8
1: 13
2: 28
3: 54
4: 89
5: 135
6: 190
7: 256
azoteq,ati-band-disable:
type: boolean
description: Disables the ATI band check.
azoteq,ati-lp-only:
type: boolean
description: Limits automatic ATI to low-power mode.
azoteq,gpio3-select:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3, 4, 5, 6, 7]
default: 1
description: |
Selects the channel or group of channels for which the GPIO3 pin
represents touch state as follows:
0: None
1: ULP channel
2: Trackpad
3: Trackpad
4: Generic channel 0
5: Generic channel 1
6: Generic channel 2
7: Hall channel
azoteq,reseed-select:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
default: 0
description: |
Specifies the event(s) that prompt the device to reseed (i.e. reset the
long-term average) of an associated channel as follows:
0: None
1: Proximity
2: Proximity or touch
3: Proximity, touch or deep touch
azoteq,thresh-extend:
type: boolean
description: Multiplies all touch and deep-touch thresholds by 4.
azoteq,tracking-enable:
type: boolean
description:
Enables all associated channels to track their respective reference
channels.
azoteq,reseed-offset:
type: boolean
description:
Applies an 8-count offset to all long-term averages upon either ATI or
reseed events.
azoteq,rate-np-ms:
minimum: 0
maximum: 255
default: 150
description: Specifies the report rate (in ms) during normal-power mode.
azoteq,rate-lp-ms:
minimum: 0
maximum: 255
default: 150
description: Specifies the report rate (in ms) during low-power mode.
azoteq,rate-ulp-ms:
multipleOf: 16
minimum: 0
maximum: 4080
default: 0
description: Specifies the report rate (in ms) during ultra-low-power mode.
azoteq,timeout-pwr-ms:
multipleOf: 512
minimum: 0
maximum: 130560
default: 2560
description:
Specifies the length of time (in ms) to wait for an event before moving
from normal-power mode to low-power mode, or (if 'azoteq,ulp-enable' is
present) from low-power mode to ultra-low-power mode.
azoteq,timeout-lta-ms:
multipleOf: 512
minimum: 0
maximum: 130560
default: 40960
description:
Specifies the length of time (in ms) to wait before resetting the long-
term average of all channels. Specify the maximum timeout to disable it
altogether.
touchscreen-inverted-x: true
touchscreen-inverted-y: true
touchscreen-swapped-x-y: true
patternProperties:
"^ulp-0|generic-[0-2]|hall$":
type: object
description:
Represents a single sensing channel. A channel is active if defined and
inactive otherwise.
properties:
azoteq,ati-exclude:
type: boolean
description:
Prevents the channel from participating in an ATI event that is
manually triggered during initialization.
azoteq,reseed-disable:
type: boolean
description:
Prevents the channel from being reseeded if the long-term average
timeout (defined in 'azoteq,timeout-lta') expires.
azoteq,meas-cap-decrease:
type: boolean
description:
Decreases the internal measurement capacitance from 60 pF to 15 pF.
azoteq,rx-inactive:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2]
default: 0
description: |
Specifies how inactive CRX pins are to be terminated as follows:
0: VSS
1: Floating
2: VREG (generic channels only)
azoteq,linearize:
type: boolean
description:
Enables linearization of the channel's counts (generic and Hall
channels) or inverts the polarity of the channel's proximity or
touch states (ULP channel).
azoteq,dual-direction:
type: boolean
description:
Specifies that the channel's long-term average is to freeze in the
presence of either increasing or decreasing counts, thereby permit-
ting events to be reported in either direction.
azoteq,filt-disable:
type: boolean
description: Disables raw count filtering for the channel.
azoteq,ati-mode:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
description: |
Specifies the channel's ATI mode as follows:
0: Disabled
1: Semi-partial
2: Partial
3: Full
The default value is a function of the channel and the device's reset
user interface (RUI); reference the datasheet for further information
about the available RUI options.
azoteq,ati-base:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [75, 100, 150, 200]
description:
Specifies the channel's ATI base. The default value is a function
of the channel and the device's RUI.
azoteq,ati-target:
$ref: /schemas/types.yaml#/definitions/uint32
multipleOf: 32
minimum: 0
maximum: 2016
description:
Specifies the channel's ATI target. The default value is a function
of the channel and the device's RUI.
azoteq,cct-increase:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 16
default: 0
description:
Specifies the degree to which the channel's charge cycle time is to
be increased, with 0 representing no increase. The maximum value is
limited to 4 in the case of the ULP channel, and the property is un-
available entirely in the case of the Hall channel.
azoteq,proj-bias:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
default: 0
description: |
Specifies the bias current applied during projected-capacitance
sensing as follows:
0: 2.5 uA
1: 5 uA
2: 10 uA
3: 20 uA
This property is unavailable in the case of the Hall channel.
azoteq,sense-freq:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
description: |
Specifies the channel's sensing frequency as follows (parenthesized
numbers represent the frequency if 'azoteq,clk-div' is present):
0: 4 MHz (1 MHz)
1: 2 MHz (500 kHz)
2: 1 MHz (250 kHz)
3: 500 kHz (125 kHz)
This property is unavailable in the case of the Hall channel. The
default value is a function of the channel and the device's RUI.
azoteq,ati-band-tighten:
type: boolean
description:
Tightens the ATI band from 1/8 to 1/16 of the desired target (ULP and
generic channels only).
azoteq,proj-enable:
type: boolean
description: Enables projected-capacitance sensing (ULP channel only).
azoteq,filt-str-np-cnt:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
default: 0
description:
Specifies the raw count filter strength during normal-power mode (ULP
and generic channels only).
azoteq,filt-str-lp-cnt:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
default: 0
description:
Specifies the raw count filter strength during low-power mode (ULP and
generic channels only).
azoteq,filt-str-np-lta:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
default: 0
description:
Specifies the long-term average filter strength during normal-power
mode (ULP and generic channels only).
azoteq,filt-str-lp-lta:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
default: 0
description:
Specifies the long-term average filter strength during low-power mode
(ULP and generic channels only).
azoteq,rx-enable:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 8
items:
minimum: 0
maximum: 7
description:
Specifies the CRX pin(s) associated with the channel.
This property is unavailable in the case of the Hall channel. The
default value is a function of the channel and the device's RUI.
azoteq,tx-enable:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 8
items:
minimum: 0
maximum: 7
description:
Specifies the TX pin(s) associated with the channel.
This property is unavailable in the case of the Hall channel. The
default value is a function of the channel and the device's RUI.
azoteq,local-cap-size:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3, 4]
default: 0
description: |
Specifies the capacitance to be added to the channel as follows:
0: 0 pF
1: 0.5 pF
2: 1.0 pF
3: 1.5 pF
4: 2.0 pF
This property is unavailable in the case of the ULP or Hall channels.
azoteq,sense-mode:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 8, 9, 12, 14, 15]
description: |
Specifies the channel's sensing mode as follows:
0: Self capacitance
1: Projected capacitance
8: Self inductance
9: Mutual inductance
12: External
14: Hall effect
15: Temperature
This property is unavailable in the case of the ULP or Hall channels.
The default value is a function of the channel and the device's RUI.
azoteq,tx-freq:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
default: 0
description: |
Specifies the inductive sensing excitation frequency as follows
(parenthesized numbers represent the frequency if 'azoteq,clk-div'
is present):
0: 16 MHz (4 MHz)
1: 8 MHz (2 MHz)
2: 4 MHz (1 MHz)
3: 2 MHz (500 kHz)
This property is unavailable in the case of the ULP or Hall channels.
azoteq,invert-enable:
type: boolean
description:
Inverts the polarity of the states reported for proximity, touch and
deep-touch events relative to their respective thresholds (generic
channels only).
azoteq,comp-disable:
type: boolean
description:
Disables compensation for the channel (generic channels only).
azoteq,static-enable:
type: boolean
description:
Enables the static front-end for the channel (generic channels only).
azoteq,assoc-select:
$ref: /schemas/types.yaml#/definitions/string-array
minItems: 1
maxItems: 6
items:
enum:
- ulp-0
- trackpad-3x2
- trackpad-3x3
- generic-0
- generic-1
- generic-2
- hall
description:
Specifies the associated channels for which the channel serves as a
reference channel. By default, no channels are selected. This prop-
erty is only available for the generic channels.
azoteq,assoc-weight:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 255
default: 0
description:
Specifies the channel's impact weight if it acts as an associated
channel (0 = 0% impact, 255 = 200% impact). This property is only
available for the generic channels.
patternProperties:
"^event-(prox|touch|deep)(-alt)?$":
type: object
description:
Represents a proximity, touch or deep-touch event reported by the
channel in response to a decrease in counts. Node names suffixed with
'-alt' instead correspond to an increase in counts.
By default, the long-term average tracks an increase in counts such
that only events corresponding to a decrease in counts are reported
(refer to the datasheet for more information).
Specify 'azoteq,dual-direction' to freeze the long-term average when
the counts increase or decrease such that events of either direction
can be reported. Alternatively, specify 'azoteq,invert-enable' to in-
vert the polarity of the states reported by the channel.
Complementary events (e.g. event-touch and event-touch-alt) can both
be present and specify different key or switch codes, but not differ-
ent thresholds or hysteresis (if applicable).
Proximity events are unavailable in the case of the Hall channel, and
deep-touch events are only available for the generic channels. Unless
otherwise specified, default values are a function of the channel and
the device's RUI.
properties:
azoteq,thresh:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 255
description: Specifies the threshold for the event.
azoteq,hyst:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 15
description:
Specifies the hysteresis for the event (touch and deep-touch
events only).
linux,code:
$ref: /schemas/types.yaml#/definitions/uint32
description: Numeric key or switch code associated with the event.
linux,input-type:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 5]
description:
Specifies whether the event is to be interpreted as a key (1) or
a switch (5). By default, Hall-channel events are interpreted as
switches and all others are interpreted as keys.
dependencies:
linux,input-type: ["linux,code"]
additionalProperties: false
dependencies:
azoteq,assoc-weight: ["azoteq,assoc-select"]
additionalProperties: false
"^trackpad-3x[2-3]$":
type: object
description:
Represents all channels associated with the trackpad. The channels are
collectively active if the trackpad is defined and inactive otherwise.
properties:
azoteq,ati-exclude:
type: boolean
description:
Prevents the trackpad channels from participating in an ATI event
that is manually triggered during initialization.
azoteq,reseed-disable:
type: boolean
description:
Prevents the trackpad channels from being reseeded if the long-term
average timeout (defined in 'azoteq,timeout-lta') expires.
azoteq,meas-cap-decrease:
type: boolean
description:
Decreases the internal measurement capacitance from 60 pF to 15 pF.
azoteq,rx-inactive:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
default: 0
description: |
Specifies how inactive CRX pins are to be terminated as follows:
0: VSS
1: Floating
azoteq,linearize:
type: boolean
description: Inverts the polarity of the trackpad's touch state.
azoteq,dual-direction:
type: boolean
description:
Specifies that the trackpad's long-term averages are to freeze in
the presence of either increasing or decreasing counts, thereby
permitting events to be reported in either direction.
azoteq,filt-disable:
type: boolean
description: Disables raw count filtering for the trackpad channels.
azoteq,ati-mode:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
default: 0
description: |
Specifies the trackpad's ATI mode as follows:
0: Disabled
1: Semi-partial
2: Partial
3: Full
azoteq,ati-base:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 6
maxItems: 9
items:
minimum: 45
maximum: 300
default: [45, 45, 45, 45, 45, 45, 45, 45, 45]
description: Specifies each individual trackpad channel's ATI base.
azoteq,ati-target:
$ref: /schemas/types.yaml#/definitions/uint32
multipleOf: 32
minimum: 0
maximum: 2016
default: 0
description: Specifies the trackpad's ATI target.
azoteq,cct-increase:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 4
default: 0
description:
Specifies the degree to which the trackpad's charge cycle time is to
be increased, with 0 representing no increase.
azoteq,proj-bias:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
default: 0
description: |
Specifies the bias current applied during projected-capacitance
sensing as follows:
0: 2.5 uA
1: 5 uA
2: 10 uA
3: 20 uA
azoteq,sense-freq:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
default: 0
description: |
Specifies the trackpad's sensing frequency as follows (parenthesized
numbers represent the frequency if 'azoteq,clk-div' is present):
0: 4 MHz (1 MHz)
1: 2 MHz (500 kHz)
2: 1 MHz (250 kHz)
3: 500 kHz (125 kHz)
azoteq,ati-band-tighten:
type: boolean
description:
Tightens the ATI band from 1/8 to 1/16 of the desired target.
azoteq,thresh:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 6
maxItems: 9
items:
minimum: 0
maximum: 255
default: [0, 0, 0, 0, 0, 0, 0, 0, 0]
description:
Specifies each individual trackpad channel's touch threshold.
azoteq,hyst:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 15
default: 0
description: Specifies the trackpad's touch hysteresis.
azoteq,lta-update:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3, 4, 5, 6, 7]
default: 0
description: |
Specifies the update rate of the trackpad's long-term average during
ultra-low-power mode as follows:
0: 2
1: 4
2: 8
3: 16
4: 32
5: 64
6: 128
7: 255
azoteq,filt-str-trackpad:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
default: 0
description: Specifies the trackpad coordinate filter strength.
azoteq,filt-str-np-cnt:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
default: 0
description:
Specifies the raw count filter strength during normal-power mode.
azoteq,filt-str-lp-cnt:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
default: 0
description:
Specifies the raw count filter strength during low-power mode.
linux,keycodes:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 6
description: |
Specifies the numeric keycodes associated with each available gesture
in the following order (enter 0 for unused gestures):
0: Positive flick or swipe in X direction
1: Negative flick or swipe in X direction
2: Positive flick or swipe in Y direction
3: Negative flick or swipe in Y direction
4: Tap
5: Hold
azoteq,gesture-swipe:
type: boolean
description:
Directs the device to interpret axial gestures as a swipe (finger
remains on trackpad) instead of a flick (finger leaves trackpad).
azoteq,timeout-tap-ms:
multipleOf: 16
minimum: 0
maximum: 4080
default: 0
description:
Specifies the length of time (in ms) within which a trackpad touch
must be released in order to be interpreted as a tap.
azoteq,timeout-swipe-ms:
multipleOf: 16
minimum: 0
maximum: 4080
default: 0
description:
Specifies the length of time (in ms) within which an axial gesture
must be completed in order to be interpreted as a flick or swipe.
azoteq,thresh-swipe:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 255
default: 0
description:
Specifies the number of points across which an axial gesture must
travel in order to be interpreted as a flick or swipe.
dependencies:
azoteq,gesture-swipe: ["linux,keycodes"]
azoteq,timeout-tap-ms: ["linux,keycodes"]
azoteq,timeout-swipe-ms: ["linux,keycodes"]
azoteq,thresh-swipe: ["linux,keycodes"]
additionalProperties: false
required:
- compatible
- reg
- interrupts
- "#address-cells"
- "#size-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
iqs626a@44 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "azoteq,iqs626a";
reg = <0x44>;
interrupt-parent = <&gpio>;
interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
azoteq,rate-np-ms = <16>;
azoteq,rate-lp-ms = <160>;
azoteq,timeout-pwr-ms = <2560>;
azoteq,timeout-lta-ms = <32768>;
ulp-0 {
azoteq,meas-cap-decrease;
azoteq,ati-base = <75>;
azoteq,ati-target = <1024>;
azoteq,rx-enable = <2>, <3>, <4>,
<5>, <6>, <7>;
event-prox {
linux,code = <KEY_POWER>;
};
};
trackpad-3x3 {
azoteq,filt-str-np-cnt = <1>;
azoteq,filt-str-lp-cnt = <1>;
azoteq,hyst = <4>;
azoteq,thresh = <35>, <40>, <40>,
<38>, <33>, <38>,
<35>, <35>, <35>;
azoteq,ati-mode = <3>;
azoteq,ati-base = <195>, <195>, <195>,
<195>, <195>, <195>,
<195>, <195>, <195>;
azoteq,ati-target = <512>;
azoteq,proj-bias = <1>;
azoteq,sense-freq = <2>;
linux,keycodes = <KEY_VOLUMEUP>,
<KEY_VOLUMEDOWN>,
<KEY_NEXTSONG>,
<KEY_PREVIOUSSONG>,
<KEY_PLAYPAUSE>,
<KEY_STOPCD>;
azoteq,gesture-swipe;
azoteq,timeout-swipe-ms = <800>;
azoteq,timeout-tap-ms = <400>;
azoteq,thresh-swipe = <40>;
};
/*
* Preserve the default register settings for
* the temperature-tracking channel leveraged
* by reset user interface (RUI) 1.
*
* Scalar properties (e.g. ATI mode) are left
* untouched by simply omitting them; boolean
* properties must be specified explicitly as
* needed.
*/
generic-2 {
azoteq,reseed-disable;
azoteq,meas-cap-decrease;
azoteq,dual-direction;
azoteq,comp-disable;
azoteq,static-enable;
};
hall {
azoteq,reseed-disable;
azoteq,meas-cap-decrease;
event-touch {
linux,code = <SW_LID>;
};
};
};
};
...

75
Bindings/input/touchscreen/azoteq,iqs5xx.yaml Normal file
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@ -0,0 +1,75 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/input/touchscreen/azoteq,iqs5xx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Azoteq IQS550/572/525 Trackpad/Touchscreen Controller
maintainers:
- Jeff LaBundy <jeff@labundy.com>
description: |
The Azoteq IQS550, IQS572 and IQS525 trackpad and touchscreen controllers
employ projected-capacitance sensing and can track up to five independent
contacts.
Link to datasheet: https://www.azoteq.com/
allOf:
- $ref: touchscreen.yaml#
properties:
compatible:
enum:
- azoteq,iqs550
- azoteq,iqs572
- azoteq,iqs525
reg:
maxItems: 1
interrupts:
maxItems: 1
reset-gpios:
maxItems: 1
wakeup-source: true
touchscreen-size-x: true
touchscreen-size-y: true
touchscreen-inverted-x: true
touchscreen-inverted-y: true
touchscreen-swapped-x-y: true
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
touchscreen@74 {
compatible = "azoteq,iqs550";
reg = <0x74>;
interrupt-parent = <&gpio>;
interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
reset-gpios = <&gpio 22 (GPIO_ACTIVE_LOW |
GPIO_PUSH_PULL)>;
touchscreen-size-x = <800>;
touchscreen-size-y = <480>;
};
};
...

119
Bindings/input/touchscreen/hycon,hy46xx.yaml Normal file
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@ -0,0 +1,119 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/input/touchscreen/hycon,hy46xx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Hycon HY46XX series touchscreen controller bindings
description: |
There are 6 variants of the chip for various touch panel sizes and cover lens material
Glass: 0.3mm--4.0mm
PET/PMMA: 0.2mm--2.0mm
HY4613(B)-N048 < 6"
HY4614(B)-N068 7" .. 10.1"
HY4621-NS32 < 5"
HY4623-NS48 5.1" .. 7"
Glass: 0.3mm--8.0mm
PET/PMMA: 0.2mm--4.0mm
HY4633(B)-N048 < 6"
HY4635(B)-N048 < 7" .. 10.1"
maintainers:
- Giulio Benetti <giulio.benetti@benettiengineering.com>
allOf:
- $ref: touchscreen.yaml#
properties:
compatible:
enum:
- hycon,hy4613
- hycon,hy4614
- hycon,hy4621
- hycon,hy4623
- hycon,hy4633
- hycon,hy4635
reg:
maxItems: 1
interrupts:
maxItems: 1
reset-gpios:
maxItems: 1
vcc-supply: true
hycon,threshold:
description: Allows setting the sensitivity in the range from 0 to 255.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 255
hycon,glove-enable:
type: boolean
description: Allows enabling glove setting.
hycon,report-speed-hz:
description: Allows setting the report speed in Hertz.
minimum: 1
maximum: 255
hycon,noise-filter-enable:
type: boolean
description: Allows enabling power noise filter.
hycon,filter-data:
description: Allows setting how many samples throw before reporting touch
in the range from 0 to 5.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 5
hycon,gain:
description: Allows setting the sensitivity distance in the range from 0 to 5.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 5
hycon,edge-offset:
description: Allows setting the edge compensation in the range from 0 to 16.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 16
touchscreen-size-x: true
touchscreen-size-y: true
touchscreen-fuzz-x: true
touchscreen-fuzz-y: true
touchscreen-inverted-x: true
touchscreen-inverted-y: true
touchscreen-swapped-x-y: true
interrupt-controller: true
additionalProperties: false
required:
- compatible
- reg
- interrupts
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
touchscreen@1c {
compatible = "hycon,hy4633";
reg = <0x1c>;
interrupt-parent = <&gpio2>;
interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
};
};
...

73
Bindings/input/touchscreen/ilitek_ts_i2c.yaml Normal file
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@ -0,0 +1,73 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/input/touchscreen/ilitek_ts_i2c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ilitek I2C Touchscreen Controller
maintainers:
- Dmitry Torokhov <dmitry.torokhov@gmail.com>
allOf:
- $ref: touchscreen.yaml#
properties:
compatible:
enum:
- ilitek,ili2130
- ilitek,ili2131
- ilitek,ili2132
- ilitek,ili2316
- ilitek,ili2322
- ilitek,ili2323
- ilitek,ili2326
- ilitek,ili2520
- ilitek,ili2521
reg:
const: 0x41
interrupts:
maxItems: 1
reset-gpios:
maxItems: 1
wakeup-source:
type: boolean
description: touchscreen can be used as a wakeup source.
touchscreen-size-x: true
touchscreen-size-y: true
touchscreen-inverted-x: true
touchscreen-inverted-y: true
touchscreen-swapped-x-y: true
additionalProperties: false
required:
- compatible
- reg
- interrupts
- reset-gpios
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
touchscreen@41 {
compatible = "ilitek,ili2520";
reg = <0x41>;
interrupt-parent = <&gpio1>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
touchscreen-inverted-y;
wakeup-source;
};
};

87
Bindings/input/touchscreen/melfas,mms114.yaml Normal file
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@ -0,0 +1,87 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/input/touchscreen/melfas,mms114.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Melfas MMS114 family touchscreen controller bindings
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
allOf:
- $ref: touchscreen.yaml#
properties:
$nodename:
pattern: "^touchscreen(@.*)?$"
compatible:
items:
- enum:
- melfas,mms114
- melfas,mms134s
- melfas,mms136
- melfas,mms152
- melfas,mms345l
reg:
description: I2C address
clock-frequency:
description: I2C client clock frequency, defined for host
minimum: 100000
maximum: 400000
interrupts:
maxItems: 1
avdd-supply:
description: Analog power supply regulator on AVDD pin
vdd-supply:
description: Digital power supply regulator on VDD pin
touchscreen-size-x: true
touchscreen-size-y: true
touchscreen-fuzz-x: true
touchscreen-fuzz-y: true
touchscreen-fuzz-pressure: true
touchscreen-inverted-x: true
touchscreen-inverted-y: true
touchscreen-swapped-x-y: true
touchscreen-max-pressure: true
additionalProperties: false
required:
- compatible
- reg
- interrupts
- touchscreen-size-x
- touchscreen-size-y
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
touchscreen@48 {
compatible = "melfas,mms114";
reg = <0x48>;
interrupt-parent = <&gpio>;
interrupts = <39 IRQ_TYPE_EDGE_FALLING>;
avdd-supply = <&ldo1_reg>;
vdd-supply = <&ldo2_reg>;
touchscreen-size-x = <720>;
touchscreen-size-y = <1280>;
touchscreen-fuzz-x = <10>;
touchscreen-fuzz-y = <10>;
touchscreen-fuzz-pressure = <10>;
touchscreen-inverted-x;
touchscreen-inverted-y;
};
};
...

69
Bindings/input/touchscreen/mstar,msg2638.yaml Normal file
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@ -0,0 +1,69 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/input/touchscreen/mstar,msg2638.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MStar msg2638 touchscreen controller Bindings
maintainers:
- Vincent Knecht <vincent.knecht@mailoo.org>
allOf:
- $ref: touchscreen.yaml#
properties:
compatible:
const: mstar,msg2638
reg:
const: 0x26
interrupts:
maxItems: 1
reset-gpios:
maxItems: 1
vdd-supply:
description: Power supply regulator for the chip
vddio-supply:
description: Power supply regulator for the I2C bus
touchscreen-size-x: true
touchscreen-size-y: true
additionalProperties: false
required:
- compatible
- reg
- interrupts
- reset-gpios
- touchscreen-size-x
- touchscreen-size-y
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
touchscreen@26 {
compatible = "mstar,msg2638";
reg = <0x26>;
interrupt-parent = <&msmgpio>;
interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&msmgpio 100 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&ts_int_reset_default>;
vdd-supply = <&pm8916_l17>;
vddio-supply = <&pm8916_l5>;
touchscreen-size-x = <2048>;
touchscreen-size-y = <2048>;
};
};
...

11
Bindings/interconnect/qcom,rpmh.yaml
View File

@ -71,6 +71,16 @@ properties:
- qcom,sm8250-mmss-noc
- qcom,sm8250-npu-noc
- qcom,sm8250-system-noc
- qcom,sm8350-aggre1-noc
- qcom,sm8350-aggre2-noc
- qcom,sm8350-config-noc
- qcom,sm8350-dc-noc
- qcom,sm8350-gem-noc
- qcom,sm8350-lpass-ag-noc
- qcom,sm8350-mc-virt
- qcom,sm8350-mmss-noc
- qcom,sm8350-compute-noc
- qcom,sm8350-system-noc
'#interconnect-cells':
enum: [ 1, 2 ]
@ -82,7 +92,6 @@ properties:
this interconnect to send RPMh commands.
qcom,bcm-voter-names:
$ref: /schemas/types.yaml#/definitions/string-array
description: |
Names for each of the qcom,bcm-voters specified.

147
Bindings/interconnect/qcom,sdm660.yaml Normal file
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@ -0,0 +1,147 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,sdm660.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SDM660 Network-On-Chip interconnect
maintainers:
- AngeloGioacchino Del Regno <kholk11@gmail.com>
description: |
The Qualcomm SDM660 interconnect providers support adjusting the
bandwidth requirements between the various NoC fabrics.
properties:
reg:
maxItems: 1
compatible:
enum:
- qcom,sdm660-a2noc
- qcom,sdm660-bimc
- qcom,sdm660-cnoc
- qcom,sdm660-gnoc
- qcom,sdm660-mnoc
- qcom,sdm660-snoc
'#interconnect-cells':
const: 1
clocks:
minItems: 1
maxItems: 3
clock-names:
minItems: 1
maxItems: 3
required:
- compatible
- reg
- '#interconnect-cells'
- clock-names
- clocks
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
enum:
- qcom,sdm660-mnoc
then:
properties:
clocks:
items:
- description: Bus Clock.
- description: Bus A Clock.
- description: CPU-NoC High-performance Bus Clock.
clock-names:
items:
- const: bus
- const: bus_a
- const: iface
- if:
properties:
compatible:
contains:
enum:
- qcom,sdm660-a2noc
- qcom,sdm660-bimc
- qcom,sdm660-cnoc
- qcom,sdm660-gnoc
- qcom,sdm660-snoc
then:
properties:
clocks:
items:
- description: Bus Clock.
- description: Bus A Clock.
clock-names:
items:
- const: bus
- const: bus_a
examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/qcom,mmcc-sdm660.h>
bimc: interconnect@1008000 {
compatible = "qcom,sdm660-bimc";
reg = <0x01008000 0x78000>;
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
<&rpmcc RPM_SMD_BIMC_A_CLK>;
};
cnoc: interconnect@1500000 {
compatible = "qcom,sdm660-cnoc";
reg = <0x01500000 0x10000>;
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
<&rpmcc RPM_SMD_CNOC_A_CLK>;
};
snoc: interconnect@1626000 {
compatible = "qcom,sdm660-snoc";
reg = <0x01626000 0x7090>;
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
<&rpmcc RPM_SMD_SNOC_A_CLK>;
};
a2noc: interconnect@1704000 {
compatible = "qcom,sdm660-a2noc";
reg = <0x01704000 0xc100>;
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
<&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>;
};
mnoc: interconnect@1745000 {
compatible = "qcom,sdm660-mnoc";
reg = <0x01745000 0xa010>;
#interconnect-cells = <1>;
clock-names = "bus", "bus_a", "iface";
clocks = <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
<&rpmcc RPM_SMD_MMSSNOC_AXI_CLK_A>,
<&mmcc AHB_CLK_SRC>;
};
gnoc: interconnect@17900000 {
compatible = "qcom,sdm660-gnoc";
reg = <0x17900000 0xe000>;
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&xo_board>, <&xo_board>;
};

88
Bindings/interrupt-controller/apple,aic.yaml Normal file
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@ -0,0 +1,88 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/apple,aic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Apple Interrupt Controller
maintainers:
- Hector Martin <marcan@marcan.st>
description: |
The Apple Interrupt Controller is a simple interrupt controller present on
Apple ARM SoC platforms, including various iPhone and iPad devices and the
"Apple Silicon" Macs.
It provides the following features:
- Level-triggered hardware IRQs wired to SoC blocks
- Single mask bit per IRQ
- Per-IRQ affinity setting
- Automatic masking on event delivery (auto-ack)
- Software triggering (ORed with hw line)
- 2 per-CPU IPIs (meant as "self" and "other", but they are interchangeable
if not symmetric)
- Automatic prioritization (single event/ack register per CPU, lower IRQs =
higher priority)
- Automatic masking on ack
- Default "this CPU" register view and explicit per-CPU views
This device also represents the FIQ interrupt sources on platforms using AIC,
which do not go through a discrete interrupt controller.
allOf:
- $ref: /schemas/interrupt-controller.yaml#
properties:
compatible:
items:
- const: apple,t8103-aic
- const: apple,aic
interrupt-controller: true
'#interrupt-cells':
const: 3
description: |
The 1st cell contains the interrupt type:
- 0: Hardware IRQ
- 1: FIQ
The 2nd cell contains the interrupt number.
- HW IRQs: interrupt number
- FIQs:
- 0: physical HV timer
- 1: virtual HV timer
- 2: physical guest timer
- 3: virtual guest timer
The 3rd cell contains the interrupt flags. This is normally
IRQ_TYPE_LEVEL_HIGH (4).
reg:
description: |
Specifies base physical address and size of the AIC registers.
maxItems: 1
required:
- compatible
- '#interrupt-cells'
- interrupt-controller
- reg
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
aic: interrupt-controller@23b100000 {
compatible = "apple,t8103-aic", "apple,aic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x2 0x3b100000 0x0 0x8000>;
};
};

52
Bindings/interrupt-controller/idt,32434-pic.yaml Normal file
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@ -0,0 +1,52 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/idt,32434-pic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: IDT 79RC32434 Interrupt Controller Device Tree Bindings
maintainers:
- Thomas Bogendoerfer <tsbogend@alpha.franken.de>
allOf:
- $ref: /schemas/interrupt-controller.yaml#
properties:
"#interrupt-cells":
const: 1
compatible:
const: idt,32434-pic
reg:
maxItems: 1
interrupts:
maxItems: 1
interrupt-controller: true
required:
- "#interrupt-cells"
- compatible
- reg
- interrupt-controller
- interrupts
additionalProperties: false
examples:
- |
idtpic3: interrupt-controller@3800c {
compatible = "idt,32434-pic";
reg = <0x3800c 0x0c>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&cpuintc>;
interrupts = <3>;
};
...

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